WO2017156638A1 - Low-volume hybrid step-down dc-dc converter - Google Patents

Abstract

In some embodiments, there is provided a converter including a switched-capacitor voltage divider having input capacitors; a 2 input inductive converter; a flying capacitor, the switched-capacitor voltage divider and the 2 input inductive converter being connected across the flying capacitor; and a controller configured for controlling gate voltages applied to switches of the converter, maintaining a voltage across each of the input capacitors and the flying capacitor equal to or about equal to V_in/2. The converter may be a step-down DC-DC converter for use with a digital controller. The converter may, in some embodiments, be used for low-volume, portable applications.

Description

LOW-VOLUME HYBRID STEP-DOWN DC-DC CONVERTER

[0001] This application claims all benefit, including priority of, U.S. Application No. 62/309797, dated 17-Mar-2016, entitled "LOW-VOLUME HYBRID STEP-DOWN DC-DC CONVERTER", incorporated herein by reference. FIELD

[0002] The present disclosure generally relates to the field of power conversion and more specifically converters for DC-DC power conversion.

INTRODUCTION

[0003] In modern battery powered portable applications, such as laptops, tablet computers, smart phones etc., many dc-dc switched mode power supplies (SMPS) are utilized to provide multiple voltage levels for various functional blocks.

[0004] A challenge with the implementation of the SMPS is their size. In numerous portable devices, SMPS are among the largest contributors to the overall size and weight of the entire device and large consumers of printed circuit board (PCB) space. [0005] This is primarily due to the bulky and costly reactive components of the SMPS output filters, where the inductors are the largest and heaviest components of the filters.

[0006] In numerous emerging electronics devices, the size of the inductors is a main obstacle in attempts to further minimize the size of the devices, extend battery operating time, and/or prevents implementation of new functional blocks. [0007] For example, in mobile applications, reduction of the inductor size volume would allow for the use of a larger capacity battery pack and/or introduction of new sensing and data processing circuits that would increase functionality of the devices. In some embodiments, similar functionality advantages could be achieved in other consumer and industrial electronics products. In weight and volume constrained avionics and automotive applications reduction of the size of the inductors and, therefore, the overall size and weight of the power supplies would ultimately transfer into a significant reduction of the carbon footprint and significant savings in implementation of electric power management systems. [0008] In conventional power converters, it is possible to reduce the size of the converter by operating them at higher switching frequencies. However, this results in a reduced power processing efficiency and, in some case increased cooling system size. Both of these often nullify advantages obtained through high frequency operation. [0009] Some embodiments present a potential solution for minimizing the size of the power supplies while, at the same time, improving power processing efficiency.

SUM MARY

[0010] In an aspect, there is provided a converter comprising: a switched-capacitor (SC) voltage divider having input capacitors; a 2 input inductive converter; a flying capacitor, the switched-capacitor voltage divider and the 2 input inductive converter being connected across the flying capacitor; and a controller configured for complementarily controlling gate voltages applied to switches of the converter, maintaining a voltage across each of the input capacitors and the flying capacitor equal to or about equal to V_in/2.

[0011] It should be noted that the presented connection is not a conventional serial connection of a switched-capacitor and an inductive based converter (buck in some scenarios).

[0012] In conventional implementations, the input of one converter is directly connected to the output of the other converter, both converters process the full amount of the output power, and the system level power processing efficiency is the product of the efficiencies of the two stages.

[0013] As it will be described later, in some implementations described below, the SC only processes a portion of the output power and, as a result, the system level efficiency is improved.

[0014] In another aspect, the converter is used, but not limited, in battery powered applications where an input voltage of the converter can vary based on an input battery's state-of-the-charge, and wherein, in one possible embodiment, the converter is configured to vary its duty ratio (D) to provide a fixed desired output voltage. The same or a similar topology can be used in numerous other applications where the input voltage can vary. Also, multiple other control methods such as constant on (or off) time variable frequency control and current programmed mode can potentially be used as well.

[0015] In an aspect, a converter having the topology as illustrated further in FIG. 1 is provided. [0016] In another aspect, the switches SW,, SW₂, SW₃, SW₄, SW₅, and SW₆ are controlled complementarily to maintain an equilibrium voltage across the input capacitors

[0017] In another aspect, for operation between V_out < M2\/_jn, the switching node, v_x operates between V 2 and ground (0 V). [0018] In another aspect, for operation between V_out > 1/2 V_in, the switching node, v_x operates between V_in and VJ2.

[0019] In another aspect, for operation at or about V_out = 1/2 V_in, the switching node, v_x is at or about a constant voltage, V 2.

[0020] In another aspect, there is provided a converter including a switched-capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched-capacitor voltage divider, the switched- capacitor voltage divider receiving an input voltage Vin; a two input inductive converter receiving an input voltage vx and providing an output voltage Vout; a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx; and a controller configured for controlling a plurality of gate signals applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout, the plurality of gate signals controlled to maintain (or restrict or clamp) a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2. [0021] In another aspect, the first plurality of switches includes switches SW1 , SW2, SW3, and SW4; wherein SW1 and SW2 in combination, control power delivery to a first node, vx1 of the flying capacitor unit, and wherein SW3 and SW4 in combination, control power delivery to a second node, vx2 of the flying capacitor unit; wherein the second plurality of switches includes switches SW5 and SW6; and wherein SW5 and SW6, in combination, control power delivery to the two input inductive converter through the input voltage vx.

[0022] In another aspect, the switches SW1 , SW2, SW3, SW4, SW5, and SW6 are controlled complementarily to maintain an equilibrium voltage across the first input capacitor and the second input capacitor. [0023] In another aspect, the controller is configured for three modes of operation, a first mode of operation in use when Vout < ½ Vin, a second mode of operation in use when ½ Vin < Vout < Vin, and a third mode of operation in use when Vout = ½ Vin.

[0024] In another aspect, for the first mode of operation, vx operates between Vin/2 and ground (0 V). [0025] In another aspect, for the second mode of operation, vx operates between Vin and Vin/2.

[0026] In another aspect, for the third mode of operation, vx operates at or about a constant voltage, Vin/2.

[0027] In another aspect, for each of the first, second, and third modes of operation, SW1 , SW3, and SW6 are active during a first time interval T1 , and SW2, SW4, and SW5 are active during a second time interval T2.

[0028] There may be another time interval where the flying capacitor is disconnected (e.g., not in parallel with either input capacitor).

[0029] In another aspect, during the duration of T1 , the switches SW1 , SW3, and SW6 are controlled to enable a parallel connection between the flying capacitor and the first input capacitor; and wherein during the duration of T2, the switches SW2, SW4, and SW5 are controlled to enable a parallel connection between the flying capacitor and the second input capacitor.

[0030] In another aspect, during the duration of T1 and the duration of T2, the input voltage vx is Vin/2. [0031] In another aspect, in the first mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter charges as the inductor resists a change in current flow passing through the inductor.

[0032] In another aspect, in the second mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter discharges as the inductor resists a change in current flow passing through the inductor.

[0033] In another aspect, in the third mode of operation, the duration of T1 and the duration of T2 are the same, and in combination, the duration of T1 and the duration of T2 span across a switching period of the converter.

[0034] In another aspect, the first mode of operation and in the second mode of operation, the duration of T1 is provided during a portion of a first half of a switching period of the converter, and the duration of T2 is provided during a portion of a second half of the switching period of the converter.

[0035] In another aspect, in the duration of T1 and the duration of T2 are determined by the controller to maintain an overall constant average current through the inductor during the switching period of the converter.

[0036] In another aspect, the flying capacitor unit is configured to restrict or clamp voltages passing through the first plurality of switches to Vin/2.

[0037] In another aspect, the the flying capacitor unit is configured to restrict or clamp voltages passing through the second plurality of switches to Vin/2. [0038] In another aspect, the controller is configured to apply voltage programmed mode control to complementarily control the plurality of gate signals. [0039] In another aspect, the controller is configured to apply current programmed mode control to complementarily control the plurality of gate signals.

[0040] In another aspect, at least one of the first plurality of switches and the second plurality of switches are rated for Vin/2. [0041] In various further aspects, the disclosure provides corresponding systems and devices, and logic structures such as machine-executable coded instruction sets for implementing such systems, devices, and methods. Such coded instruction sets may be used, for example, in the control of switches, gates, etc.

[0042] It should be noted that an embodiment of the controller for this circuit is also possible through a mixed-signal implementation and other control methods such as current programmed mode control. In that case an implementation based on an analog current loop and digital voltage loop is also possible.

[0043] In this respect, before explaining at least one embodiment in detail, it is to be understood that the embodiments are not limited in application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting.

[0044] Many further features and combinations thereof concerning embodiments described herein will appear to those skilled in the art following a reading of the instant disclosure.

DESCRIPTION OF THE FIGURES

[0045] In the figures, embodiments are illustrated by way of example. It is to be expressly understood that the description and figures are only for the purpose of illustration and as an aid to understanding. [0046] Embodiments will now be described, by way of example only, with reference to the attached figures, wherein in the figures: [0047] FIG. 1 is a view of an example of hybrid dc-dc converter with the dual use of the flying capacitor and complementary digital (or a mixed-signal) controller, according to some embodiments.

[0048] FIG. 2A is a waveform diagram illustrative of gating signals, switching node and inductor current waveforms for V_out< VJ2, according to some embodiments.

[0049] FIGS. 2B, 2C and 2D are equivalent circuits of the converter for three distinguishable time intervals inside a one switching cycle. Note, the switching cycle in this case has 4 intervals where one of them repeats twice.

[0050] FIG. 3A is a waveform diagram illustrative of gating signals, switching node and inductor current waveforms for \/_ouf> V 2, according to some embodiments.

[0051] FIGS. 3B, 3C and 3D are equivalent circuits of the converter for three distinguishable time intervals inside a one switching cycle. Note, the switching cycle in this case has 4 intervals where one of them repeats twice.

[0052] FIG. 4 is a waveform diagram illustrative of gating signals, switching node and inductor current waveforms for V_0U{= VJ2, according to some embodiments.

[0053] FIG. 5 is a graph illustrative of normalized output filter inductance value vs. duty ratio for buck converters compared to the converter of some embodiments.

[0054] FIG. 6 is a graph illustrative of an efficiency comparison with a 12-to-1 V buck converter, according to some embodiments. [0055] FIG. 7 is a graph illustrating a breakdown of the losses for 12-to-1 V operating condition, according to some embodiments.

[0056] FIG. 8 is a graph providing comparisons of 12 V-to-5 V operation, according to some embodiments.

[0057] FIG. 9 is a graph providing comparisons of 12 V-to-5 V operation, according to some embodiments. [0058] FIG. 10 is a graph providing comparisons of 8 V-to-5 V operation, according to some embodiments.

[0059] FIG. 11 is a waveform diagram illustrative of comparisons of 10 V-to-5 V operation, according to some embodiments. [0060] FIG. 12 is a method diagram illustrative of a method to control power delivery, according to some embodiments.

DETAILED DESCRIPTION

[0061] Embodiments of methods, systems, and apparatus are described through reference to the drawings. [0062] The following discussion provides many example embodiments of inventive subject matter. Although each embodiment represents a single combination of inventive elements, inventive subject matter is considered to include all possible combinations of the disclosed elements. Thus if one embodiment comprises elements A, B, and C, and a second embodiment comprises elements B and D, then the inventive subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly disclosed.

[0063] Referring to FIG. 1 , in some embodiments, a hybrid step-down dc-dc converter 100 is provided. The hybrid step-down dc-dc converter 100 may be targeted for battery powered portable applications where low-volume implementation is a factor. Volume, for example, may refer to the size of the converter 100 and/or possible form factors thereof.

[0064] The converter 100 includes a switched-capacitor voltage divider 102 having a first input capacitor (C_ini) and a second input capacitor (C^) and a first plurality of switches (for example, SW1-SW4) for controlling power flow to the switched-capacitor voltage divider 102, the switched-capacitor voltage divider receiving an input voltage V_in. [0065] The converter 100 includes an inductive converter (e.g., a two input buck converter, but other types of inductive converters are also possible and contemplated) 106 receiving an input voltage v_x and providing an output voltage V_out. [0066] The converter 100 includes a flying capacitor unit 104 connecting the switched- capacitor voltage divider and the two input buck converter together, the flying capacitor unit 104 including a flying capacitor (C_fi_y) and a second plurality of switches (SW5, SW6) controlling power flow to the two input buck converter by controlling the input voltage v_x; [0067] The converter 100 is connected to controller 108 that may be configured for complementarily controlling gate signals applied to both the first plurality of switches (SW1- SW4) and the second plurality of switches (SW5-SW6) based at least on the output voltage V_out, the plurality of gate signals controlled to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to V_in/2. Other variations of mechanisms and groupings of switches are possible (e.g., that alternatively place C_fi_y in parallel alternatively with C_ini or C_itl2, and/or disconnect C_fly altogether), and SW1-SW6 are provided as examples.

[0068] Potential advantages for converter 100 may include a relatively smaller inductor value / size required and also lower losses/higher efficiency. Higher efficiency may lead to longer battery life for battery powered devices and also lower losses may also result in less thermal dissipation, reducing the cooling requirement.

[0069] The introduced architecture, as depicted in FIG. 1 , combining switched-capacitor (SC) 102 and inductor based circuits 106, may provide low-volume for implementation by reducing the size of the filter. For example, some implementations require size decreases of components (e.g., by 4 times and the output capacitor by 2 times). In addition to supporting wide input-output range for step down voltage conversions, the introduced architecture demonstrates up to 15% power processing efficiency improvement compared to buck converter and faster dynamic response.

[0070] These advantages are obtained by a dual use of the flying capacitor unit 104 that may be used in, for example, SC converters.

[0071] The flying capacitor unit 104 is used for both balancing of the front-end stage and reducing voltage swing/stress of the components. [0072] Experimental results from a 5V, 25W, 500kHz prototype are provided to describe some potential advantages of a converter 100, according to some embodiments. The experimental results are provided in the form of examples, and variations may be possible.

[0073] In modern battery powered portable applications, such as laptops, tablet computers, smart phones etc., many dc-dc switch mode power supplies (SMPS) are utilized to provide multiple voltage levels for various functional blocks.

[0074] One of the main challenges with the implementation of SMPS is their size. In numerous portable devices SMPS are among the largest contributors to the overall size and weight of the entire device, and large consumers of printed circuit board (PCB) space. This is primarily due to the bulky and costly reactive components of the SMPS output filters, where the inductors are the largest and heaviest components of the filters.

[0075] The ever increasing demand for lower volume DC-DC converters for battery powered portable electronics has primarily been met by switching at higher frequencies, up to tens of MHz, allowing smaller filter size. However, higher switching frequency comes with a penalty of increased switching losses, negatively affecting the battery life.

[0076] To reduce the volume requirement of SMPS, two-stage compact and power efficient solutions can be used. In these solutions, a switched-capacitor (SC) fixed-ratio front-end stage performs a large portion of voltage conversion at the peak efficiency, and an inductor based downstream stage then provides final regulation. This solution reduces the voltage swing at the switching node of the inductor based stage, relaxing the requirement of the filter inductor, while improving the efficiency at the same time, due to lower input-to- output voltage conversion ratio.

[0077] However, in the series SC-inductive architectures, the output voltage is limited by the conversion ratios of the front-end SC stage and hence, some of these solutions cannot be widely adopted for applications requiring wide input-output voltage range of operation.

[0078] In some embodiments, a wide-input hybrid DC-DC converter 100 for battery- powered applications is provided that may provide for volume reduction of the reactive components and efficiency improvement. [0079] In this converter 100, shown in FIG. 1 , a first portion is a switched-capacitor voltage divider (SI/l _1- , C_/n1, C_/n2, and C_ny). However, the second portion can be a 2-input buck converter (SW_5t6, L, C_out) connected across flying capacitor, Cn_y.

[0080] As noted earlier, this configuration is different from straightforward connection of two stages and provides improved power processing efficiency than the conventional two stage solutions where both serial stages are processing the full amount of power.

[0081] By looking at FIG. 3, for example, it can be noticed that during the first interval the power from the output is directly transferred to the buck stage without going through the SC stage. Similarly, when operating for Vout<1/2Vin (FIG. 2A), the power is not passing through the SC stage during the third interval.

[0082] During second intervals in both modes of operation, the power is delivered through two parallel paths, through the flying capacitor and the divider. These parallel paths reduce (e.g., minimize, in some embodiments) the conduction losses compared to the conventional operation, where power is always delivered directly from the output. [0083] Also, in comparison with the conventional SC-inductive based configuration a need for a dedicated output capacitor of the SC is reduced or otherwise eliminated.

[0084] Therefore, some embodiments potentially advantageously require a smaller number of components than the conventional implementations consisting of the conventional 4-capacitor SC stage followed by a buck converter. These components may also have lighter (e.g., less strict) requirements than a conventional implementation as voltage stress / swing is reduced, and thereby miniaturization, volume reduction, and/or cost reduction may be achieved.

[0085] Other types of inductive converters are also contemplated. In some topologies, the flying capacitor unit 104 has dual uses. The flying capacitor C_fi_y is adapted for balancing of the capacitor divider, and at the same time reduces voltage stress/swing of the components to a ½ of V_in. [0086] A combined SC voltage divider and inductor based architecture can be used where two inductors are connected to intermediate nodes of a SC voltage divider, to provide three separate output voltages. However, in this configuration, the output voltages are correlated, due to their fixed input-to-output voltage ratios, and hence, cannot be controlled independently.

[0087] The converter 100 in FIG. 1 allows the switching node, v_x of the output filter to have 3 possible values of V_in, V 2 and 0 V, resulting in, for some embodiments, an up to 4 times reduction of the output filter inductor, L and up to a 2 times reduction of output capacitor, Cout, for approximately the same semiconductor losses. [0088] Furthermore, practical implementation illustrates that in some embodiments, all the switches can be rated for a half of the voltages required for a buck converter, improving power processing efficiency by up to 15%, by reducing conduction and switching losses.

[0089] For example, in some mobile applications the input voltage could vary between 2.7 V and 20 V, depending on the type of application and the number of battery cells utilized, i.e. type of the battery pack.

[0090] As shown in FIG. 1 , during the circuit operation the voltages across each of the input capacitors (C_/ni_,2) and flying capacitor, C_fly are equal to V_in/2.

[0091] Depending on the operating conditions, i.e., the input and output voltages, the converter 100 changes the gating sequences. [0092] As described below, this voltage equilibrium across each of the input capacitors, C;m,2, is maintained by equal charge sharing through the flying capacitor.

[0093] In reference to FIG. 1 , a first plurality of switches includes switches SW1 , SW2, SW3, and SW4, and SW1 and SW2 in combination, control power delivery to a first node, v_x1 of the flying capacitor unit 104. SW3 and SW4 in combination, control power delivery to a second node, v_x2 of the flying capacitor unit 104.

[0094] A second plurality of switches includes switches SW5 and SW6. SW5 and SW6, in combination, control power delivery to the converter 106 through the input voltage v_x. [0095] The controller 108 controls switches SW1 , SW2, SW3, SW4, SW5, and SW6 complementarily to maintain an equilibrium voltage (or substantially equal) across the first input capacitor and the second input capacitor. There may one or more modes of operation of the controller 108, each mode of operation provided by way of signal control of the gating of SW1 , SW2, SW3, SW4, SW5, and SW6. In some embodiments, there are three modes of operation, each mode of operation provided in the enumerated sections below. There may be other, different, alternative, modes of operation, and the below are provided as examples.

[0096] The duration of T1 and T2, in some embodiments, may be determined dynamically by controller 108 (e.g., to maintain a predefined average current across the inductor, averaged across the switching period), or in some embodiments, may be provided to controller 108.

[0097] Depending on the application, the inductor current ripple usually ranges from 20 % to 40 % of the nominal dc current, that ranges between few hundred mA and tens of amps. In some cases, the current can exceed 100 A. [0098] In some embodiments, the controller may be provided separately from the converter, for example, as a a controller adapted for use with a converter having a switched- capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched-capacitor voltage divider, the switched-capacitor voltage divider receiving an input voltage Vin; a two input inductive converter receiving an input voltage vx and providing an output voltage Vout; and a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx; the controller comprising: a gate control circuit (e.g., a configured PWM on an ASIC or FPGA) configured for generating a plurality of gate signals (e.g., current control or voltage control signals) applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout, the plurality of gate signals controlled to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2. A. Operation for Vout < 1/2 Vin

[0099] In case of V_out < M2V_in, the switching node, v_x operates between V 2 and ground (0 V). FIG. 2A shows the gating signals for SH _1-6, to achieve this operation. These gating signals are shown as examples, and other gating signals may be possible. [00100] The voltage V 2 at the switching node is achieved during time intervals 7Ί and 7₂, through two different gating sequences.

[00101] During SH _{1 3i6} are turned on, while during 7₂, SW_{2 ,5} are on. This is because in order to maintain equal voltage across input capacitors (C_{/n1 ,2}), the flying capacitor, C_ny, needs to be placed in parallel to each of C_/n1 and C_in2 for an equal duration of time. [00102] During the time period Ti (FIG. 2A), C _y is placed across Cm by turning on SW^ and SW₃. Similarly, during the time period T₂, Cn_y is placed across C_m by turning on SW₂ and SW₄. This results in equal charge balancing across the two input capacitors while providing V 2 at the switching node, v_x of the output filter.

[00103] Furthermore, the effective switching frequency (1/r_sw-eff) at the switching node, v_x is twice the switching frequency f_sw =^/T_sw. As it will be shown later, the lower voltage swing at the switching node, combined with higher effective switching frequency results in drastic reduction of the output filter L and C_out.

[00104] Equivalent circuits 200B, 200C, and 200D are provided for ease of reference as FIGS. 2B-2D. [00105] FIG. 2B illustrates an equivalent circuit 200B when SW1 , SW3, and SW6 are on (duration T^.

[00106] FIG. 2C illustrates an equivalent circuit 200C when SW4, and SW6 are on (during the period that is not duration Ti nor T₂).

[00107] FIG. 2D illustrates an equivalent circuit 200D when SW2, SW4, and SW5 are on (duration T₂). [00108] As illustrated in FIG. 2A, the inductor of the converter 106 may charge or discharge as it resists a change in current flow passing through the inductor.

[00109] As shown in the gating signal diagram 200A of FIG. 2A, the sequence provided is illustrated in the sequence of equivalent circuits. Practical resistances (e.g., parasitic elements) and various control switches (e.g., SWFT-FET and SW_BATFET) are also shown on the equivalent circuits.

[00110] Starting at the left hand side of the diagram 200A, the first equivalent circuit is 200B, where SW1 , SW3, and SW6 are on during period ΤΊ. The inductor current is increasing during this time. As illustrated in 200B, the flying capacitor is placed in parallel with Cjni during this time.

[0011 1] The next equivalent circuit is 200C, where SW4 and SW6 are on following period T (when the inductor is current is decreasing).

[00112] The next equivalent circuit is 200D, where SW2, SW4, and SW5 are on during period T₂. The inductor current is increasing during this time. As illustrated in 200D, the flying capacitor is placed in parallel with C_m2 during this time.

[00113] The next equivalent circuit is 200C, where SW4 and SW6 are on following period T (when the inductor is current is decreasing).

[00114] This cycle is repeated for each switching period, and accordingly, the effective switching period is half of the switching period (as illustrated in diagram 200A). v_x operates between V 2 and ground (0 V), as illustrated at diagram 200A.

[00115] In some embodiments, the periods Ti and T₂ can be determined by the controller, for example, in relation to the proportion of the switching period necessary to provide for an equilibrium value of the inductor current as it charges and discharges (e.g., to balance the increase and the decrease throughout the switching period). In other embodiments, the duration of periods and T₂ can be selected and/or provided to the controller.

B. Operation for 1/2 Vin<Vout<Vin [00116] In case of V_out > 1/2 V_in, the switching node, v_x operates between V_in and VJ2.

[00117] FIG. 3A shows the gating signals for SW_1-6, to achieve this operation. Similar to the previous case, V_in/2 at the switching node is achieved during time intervals and 7₂, by two different gating sequences. These gating signals are shown as examples, and other gating signals may be possible. Practical resistances (e.g., parasitic elements) and various control switches (e.g., SW_FT-FET and SW_BATFET) are also shown on the equivalent circuits.

[00118] During SH _{1 3i6} are turned on, while during 7₂, SW_{2 ,5} are on. During the time period (FIG. 3A) , C_fi_y is placed across Cm by turning on SIA^ and SW₃. Similarly, during the time period 7₂, C_ny is placed across C_/n2 by turning on SW₂ and SW₄. Again, this results in equal charge balancing across the two input capacitors while providing V 2 at the switching node, v_x of the output filter.

[00119] It can be seen that in both of these modes of operation the flying capacitor has dual use. It provides balancing of the input capacitive divider and, at the same time, reduces voltage stress/swing of the components to a ½ of V_in (or approximations thereof). [00120] Equivalent circuits 300B, 300C, and 300D are provided for ease of reference as FIGS. 3B-3D.

[00121] FIG. 3B illustrates an equivalent circuit 300B when SW1 , and SW5 are on (during the period that is not duration ΤΊ nor T₂).

[00122] FIG. 3C illustrates an equivalent circuit 300C when SW1 , SW3, and SW6 are on (duration ΤΊ).

[00123] FIG. 3D illustrates an equivalent circuit 300D when SW2, SW4, and SW5 are on (duration T₂).

[00124] As illustrated in FIG. 3A, the inductor of the converter 106 may charge or discharge as it resists a change in current flow passing through the inductor. [00125] As shown in the gating signal diagram 300A of FIG. 3A, the sequence provided is illustrated in the sequence of equivalent circuits. [00126] Starting at the left hand side of the diagram 300A, the first equivalent circuit is 300B, when SW1 , and SW5 are on (during the period that is not duration ΤΊ nor T₂). During this time, v_x = V_in. The inductor current is increasing during this time.

[00127] The next equivalent circuit is 300C, where SW1 , SW3, and SW6 are on following period (when the inductor is current is decreasing). As illustrated in 300C, the flying capacitor is placed in parallel with C_ini during this time.

[00128] The next equivalent circuit is 300B, where SW4 and SW6 are on following period Ti (when the inductor is current is increasing).

[00129] The next equivalent circuit is 300D, where SW2, SW4, and SW5 are on during period T₂. The inductor current is decreasing during this time. As illustrated in 300D, the flying capacitor is placed in parallel with C_in2 during this time.

[00130] This cycle is repeated for each switching period, and accordingly, the effective switching period is half of the switching period (as illustrated in diagram 300A). v_x operates between V_in andi VJ2, as illustrated at diagram 300A. [00131] In some embodiments, the periods Ti and T₂ can be determined by the controller, for example, in relation to the proportion of the switching period necessary to provide for an equilibrium value of the inductor current as it charges and discharges (e.g., to balance the increase and the decrease throughout the switching period). In other embodiments, the duration of periods Ti and T₂ can be selected and/or provided to the controller. C. Operations for Vout = 1/2 Vin

[00132] In case of V_out = 1/2 V_in, the switching node, v_x is at a constant voltage, VJ2.

[00133] FIG. 4 shows the gating signals for SH _1-6, to achieve this mode of operation. The voltage VJ2 at the switching node is maintained during the entire switching period, T_sw, by two different gating sequences over subintervals T-, and T₂. In this case, T-, and T₂ constitute the entire switching period, T_sw. [00134] During ΤΊ , SW _i3i6 are turned on, while during T₂, SH 2,4,5 are on. During the time period Τ (FIG. 2A), C_ny is placed across C_/n1 by turning on and SW₃. Similarly, during the time period T₂, Cn_y is placed across C_/n2 by turning on SW₂ and SW₄. This results in charge balancing across the two input capacitors while providing VJ2 at the switching node, v_x of the output filter.

[00135] During this mode of operation the voltage swing at the switching node, v_x is practically zero, resulting in zero inductor current ripple or nearly zero inductor current ripple.

D. Output filter volume reduction

[00136] In a buck converter the inductance is determined by the steady state ripple requirement , given by:

[00137] L = (^V» - ^V°^«)-^D , (1)

[00138] where, D is the duty ratio and A\_L is the steady state inductor current ripple.

[00139] Due to the combined reduction of voltage swing at the switching node, v_x and 2 times higher effective switching frequency (FIG. 2A, FIG. 3), the output filter inductor, L of the introduced architecture can be reduced. The reduction can be explained by the following equations:

[00140] j - ^v<- ₍ ^l _D) _D , for O < D < 0.5 (2) and

[00141] _{L =} ^y _in n __DHD_L , for 0.5 < D < 1 (3)

[00142] Comparing Equation (1 ) with (2), (3), normalized inductance values with respect to the worst case ripple condition of the buck converter 502 (D=0.5) is presented in FIG. 5. As shown in this figure, inductance reduction of the converter 100 can be at least 4 times, as shown by line 504. It should be noted that, depending on the required conversion ratios of the converter this reduction in the inductor size may potentially be even larger, in some embodiments.

[00143] This reduction is similar to multi-level (3-level) converter. In addition to the inductor being 4 times smaller, the converter 100, in some embodiments, provides a 2 times smaller output capacitor for the same ripple requirement.

[00144] This may be due to the same operating principle as a 3-level converter. However, the converter 100 has several practical implementation advantages over the 3-level converter.

PRACTICAL IMPLEMENTATION [00145] As shown in FIG. 1 , there are two additional switches in the introduced architecture compared to 4 switches in 3-level converters. The practical implementation considerations for the converter 100 are discussed below.

A. Semiconductor area for switches realization

[00146] In a buck converter, both switches need to be rated for V_in, due to the blocking voltage requirement of the switches. Although in the converter 100 of FIG. 1 there are 6 switches, these switches can be rated for VJ2. Since silicon area for switch realization is approximately proportional to V_ds ², (assuming the same R_on resistance of the switches) where V_ds is the blocking voltage of the switch, the semiconductor areas can be approximately equivalent, especially taking into account that not all transistors of the SC stage need to carry full load current as in the case of the conventional buck converter. Furthermore, in the targeted low power portable applications, the volume of the output filter is significantly larger than that of the semiconductor components. Since 4 times L and 2 times C_out reductions can be achieved, the increased number of switches may not contribute to any practical implementation challenges. [00147] For 3-level converter, the voltage swing at the switching node is also V 2, resulting in steady state blocking voltage requirement of the switches to be V_in/2. However, considering the flying capacitor could be completely discharged during startup, at least one of the switches need to be rated for full input voltage, resulting in increased silicon area for switch realization and/or additional losses.

[00148] Although the converter 100 has 2 extra switches compared to 3-level converter, the overall semiconductor requirement is not significantly increased. This is due to the fact that, two series connected capacitors C_M and C_/n2, which can be considered as the input filter capacitor of the converter, result in V 2 voltage at the center node of the four switches (SH _1-4) during startup (FIG. 1).

B. Converter losses and Efficiency

[00149] In terms of the efficiency of the converter 100 and potentially losses, in comparison with the conventional buck converter, a potential advantage of this topology comes from a potential reduction in the switching losses. Since the switching losses of converter are proportional to the C_SWV_SW ², where V_sw is the blocking voltage of the semiconductor switches and C_sw is the equivalent capacitance charged/discharged during each switching action, it can be seen that by reducing blocking voltage by a ½ switching losses across individual switches may potentially be reduced by 4 times.

[00150] Even though in some embodiments of the converter, the number of switches changing the state is larger than in the conventional buck (3 compared to 2 ) the overall switching losses are still smaller.

[00151] Furthermore, due to a smaller Miller capacitance, the gate drive losses of this topology may potentially be significantly smaller.

[00152] As discussed earlier, the increased number of switches in this topology compared to the conventional buck does not necessarily result in the increased conduction losses, since the reduction of the blocking voltage allows for a significant reduction of R_on. Furthermore, in this topology both the copper and core losses of the inductor can be reduced, due to the smaller allowable core volume and lower required inductance value.

[00153] As potential examples of some potential advantages, simulation test benches were developed in LTSpice for both the buck and introduced hybrid step-down converters, with actual models of semiconductor switches for detailed efficiency analysis. 12 V-to-1 V operating condition was selected for the comparison, where the buck and the converter 100 operate at 1 MHz and 500 kHz, respectively. As previously described, 500 kHz operation of the converter 100 results in 1 MHz inductor current ripple. 12 V Power MOSFETs from International Rectifier (IRF7476PbF) were utilized to model the performance of the buck converter under the operating condition with load currents ranging from 500 mA to 5 A.

[00154] In order to compare the performance of the introduced hybrid step-down converter 100, two different approaches were considered.

[00155] First, a conservative approach of 50% improvement in figure-of-merit (FoM) was considered for semiconductor switches, due to 50% reduced blocking voltage requirement of the switches (i.e., 6 V instead of 12 V). In this case the on-resistances (Rds_on) and gate capacitances (C_g) of the switches are considered to be 0.7 times of those of the buck switches.

[00156] Second, a more realistic estimation of 70% improvement in figure-of-merit (FoM) was considered for semiconductor switches due to 50% reduced blocking voltage requirement of the switches. In this case the on-resistances (Rds_on) and gate capacitances (Cg) of the switches are considered to be 0.55 times of those of the buck switches.

[00157] Furthermore, in both of these approaches two times smaller inductor (220 nH) with about half parasitic resistance (6 mQ) compared to the buck converter (470 nH, 11 mQ) were utilized.

[00158] As shown in FIG. 6, more than 15% efficiency improvement in the light load operating condition may be possible, potentially making the converter 100 an attractive solution for portable applications.

[00159] FIG. 7 shows the conduction, switching and gate drive losses breakdown for the buck and introduced step-down converters for 12 V-to-1 V operating condition with the load current varying between 500 mA and 5A. [00160] As shown in this figure, some of the efficiency improvements result from the reduction of the switching losses. This is due to improved FoM of the semiconductor switches with reduced blocking voltage requirements and operation with half the switching frequency (500 kHz instead of 1 MHz) of the introduced hybrid step-down converter. Hence, the maximum efficiency improvement may be demonstrated at light load operating condition, where the switching losses are the most dominant, as shown in FIG. 6.

[00161] In addition, compared to a 3-level converter, the converter 100 does not introduce the equivalent series resistance (ESR) of the flying capacitor in the conduction path of the inductor current . Depending on the size and the type of the flying capacitor, the ESR value can be in the range of 5-10 mQ, introducing additional conduction losses in the 3-level converter. However, in the introduced hybrid step-down converter 100, the switched- capacitor stage operates with the principle of charge sharing between the two input capacitors C_/n1 and C_in2 .

[00162] As a result, the ESR of the flying capacitor does not introduce any additional resistance in the conduction path of the inductor current.

C. Output voltage regulation and dynamic response

[00163] The converter 100 can provide potentially improved dynamic regulation compared to buck converter. This may be due to significantly smaller inductor size, which results in much higher slew rate than the buck converter . [00164] During light-to-heavy load transients, the voltage at the switching node, v_x can be V_in, by turning on SIA^ and SW₅ (FIG. 1). Similarly, during heavy-to-light load transients, 0 V appearing at v_x, by turning on SW₄ and SW_& will result in higher slew rate than a buck converter, due to significantly smaller inductance.

[00165] Furthermore, the converter 100 can achieve output voltage V_out = 1/2 V_in, with the gating sequence. In this mode of operation the voltage swing at the switching node is practically zero, resulting in zero current ripple for the inductor current. [00166] During this mode of operation the switched-capacitor stage operates as a voltage divider with 50 % duty ratio, whereas 2-input buck operates with zero voltage swing at the switching node, v_x (FIG. 4).

[00167] However, in 3-level converter operation with 50% duty ratio can result in large voltage transient spikes and hence, special control methods may need to be incorporated to eliminate them. Experimental results verifying proper operation of the introduced hybrid step- down DC-DC converter 100 with zero current ripple is provided below.

EXPERIMENTAL RESULTS

[00168] A discrete prototype on printed circuit board (PCB) was developed to verify proper functionality of the converter 100. The digital controller of FIG. 1 was developed using an FPGA system, consisting of PID Compensator, DPWM and Mode Control Logic blocks to determine the gating sequences, depending on operating conditions as described in Section II. FIGS. 8 to 11 show experimental results for different operating conditions, where the converter 100 and the buck converter operate with 500kHz and 1 MHz switching frequencies, respectively.

[00169] This results in the same effective switching frequencies for both the converters. The same inductor was used in both cases to demonstrate the reduction of the inductor current ripple, which will translate into proportional reduction of the inductance value for the same ripple requirement. [00170] FIG. 8 shows experimental waveforms for 12 V-to-5 V (D<0.5) operating condition. As shown in this figure, the converter 100, while operating at half the switching frequency results in about 65% reduction of inductor current ripple. 802 is the input voltage, 804 is the output voltage, 806 is the current ripple of a buck converter for comparison, 808 is the current ripple of a converter 100, 810 is the voltage v_x for the buck converter for comparison, and 812 is the voltage v_x for the converter 100. 814-824 provide the gating voltages.

[00171] This is due to 6 V voltage swing reduction at the switching node, v_x (FIG. 1). FIG. 9 shows a zoomed in version of FIG. 8 to demonstrate this mode of operation and gating sequences. 902 is the input voltage, 904 is the output voltage, 906 is the current ripple of a buck converter for comparison, 908 is the current ripple of a converter 100, 910 is the voltage v_x for the buck converter for comparison, and 912 is the voltage v_x for the converter 100. 914-924 provide the gating voltages.

[00172] FIG. 10 shows experimental waveforms for 8 V-to-5 V (D>0.5) operating condition. As shown in this figure, the converter 100, while operating at half the switching frequency results in about 60% reduction of inductor current ripple. 1002 is the input voltage, 1004 is the output voltage, 1006 is the current ripple of a buck converter for comparison, 1008 is the current ripple of a converter 100, 1010 is the voltage v_x for the buck converter for comparison, and 1012 is the voltage v_x for the converter 100. 1014-1024 provide the gating voltages.

[00173] FIG. 11 shows experimental waveforms for 10 V-to-5 V (D=0.5) operating condition. As shown in this figure, the converter 100 results in a zero current ripple condition. This provides experimental verification of operating condition with D=0.5 from FIG. 5, which shows while the buck converter reaches its maximum current ripple, the converter 100 has zero ripple current. 1102 is the input voltage, 1104 is the output voltage, 1106 is the current ripple of a buck converter for comparison, 1108 is the current ripple of a converter 100, 1110 is the voltage v_x for the buck converter for comparison, and 1112 is the voltage v_x for the converter 100. 1114-1124 provide the gating voltages.

[00174] As depicted in FIG. 1 , a hybrid step-down DC-DC converter 100, targeted for battery powered portable applications is provided by combining switched-capacitor and reduced voltage based buck converter circuits.

[00175] The novel converter 100 makes dual use of the flying capacitor usually existing in SC circuits, to provide SC cell balancing and to reduce the voltage stress/swing of the components. [00176] As a result, up to four times reduction of the output filter inductor and two times reduction of the output filter capacitor, which are by far the largest components in low power applications, is achieved. In addition to supporting wide input-output range for step down voltage conversions, the introduced architecture demonstrates up to a 15% efficiency improvement and superior dynamic regulation compared to buck converter.

[00177] Experimental and simulation results are indicative of potential advantages of the new topology over some other solutions. [00178] The embodiments of the devices, systems and methods described herein may be implemented in a combination of both hardware and software.

[00179] FIG. 12 is a method diagram 1200 illustrative of a method to control power delivery, according to some embodiments. In method diagram 1200, in step 1202, Vin and Vout are monitored (or their ratio is monitored) to determine an operating mode at 1204. At 1206A, 1206B, and 1206C, the operating mode determines the gating sequence to be applied as provided in FIGS. 2A, 3A, and 4.

[00180] Accordingly, in some embodiments, the operating sequence may be determined or in some cases continuously modified in accordance to a monitored input and/or output voltage. The method may be performed by the controller or an external device sending instructions to the controller. The controller may, for example, include non-transitory computer readable memory storing instructions that, when executed, cause a processor to perform the steps of method diagram 1200.

[00181] These embodiments may be implemented on programmable computers and/or programmable circuits, each computer including at least one processor, a data storage system (including volatile memory or non-volatile memory or other data storage elements or a combination thereof), and at least one communication interface. For example, such programmable computers may provide gating control, etc.

[00182] The term "connected" or "coupled to" may include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements).

[00183] The technical solution of embodiments may be in the form of a software product, such as a software product for gating control. The software product may be stored in a non- volatile or non-transitory storage medium, which can be a compact disk read-only memory (CD-ROM), a USB flash disk, or a removable hard disk. The software product includes a number of instructions that enable a computer device (personal computer, server, or network device) or a gating mechanism to execute the methods provided by the embodiments. [00184] Although the embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein.

[00185] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized. Accordingly, embodiments are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[00186] As can be understood, the examples described above and illustrated are intended to be exemplary only.

Claims

WHAT IS CLAIMED IS:

1. A converter comprising: a switched-capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched- capacitor voltage divider, the switched-capacitor voltage divider receiving an input voltage Vin; a two input inductive converter receiving an input voltage vx and providing an output voltage Vout; a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx; a controller configured for controlling a plurality of gate signals applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout, the plurality of gate signals controlled to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2.

2. The converter of claim 1 , wherein the first plurality of switches includes switches SW1 , SW2, SW3, and SW4; wherein SW1 and SW2 in combination, control power delivery to a first node, vx1 of the flying capacitor unit, and wherein SW3 and SW4 in combination, control power delivery to a second node, vx2 of the flying capacitor unit; wherein the second plurality of switches includes switches SW5 and SW6; and wherein SW5 and SW6, in combination, control power delivery to the two input inductive converter through the input voltage vx.

3. The converter of claim 2, wherein the switches SW1 , SW2, SW3, SW4, SW5, and SW6 are controlled to maintain an equilibrium voltage across the first input capacitor and the second input capacitor.

4. The converter of claim 3, wherein the controller is configured for three modes of operation, a first mode of operation in use when Vout < ½ Vin, a second mode of operation in use when ½ Vin < Vout < Vin, and a third mode of operation in use when Vout = ½ Vin.

5. The converter of claim 4, wherein for the first mode of operation, vx operates between Vin/2 and ground (0 V).

6. The converter of claim 4, wherein for the second mode of operation, vx operates between Vin and Vin/2.

7. The converter of claim 4, wherein for the third mode of operation, vx operates at or about a constant voltage, Vin/2.

8. The converter of claim 6, wherein for each of the first, second, and third modes of operation, SW1 , SW3, and SW6 are active during a first time interval T1 , and SW2, SW4, and SW5 are active during a second time interval T2.

9. The converter of claim 8, wherein during the duration of T1 , the switches SW1 , SW3, and SW6 are controlled to enable a parallel connection between the flying capacitor and the first input capacitor; and wherein during the duration of T2, the switches SW2, SW4, and SW5 are controlled to enable a parallel connection between the flying capacitor and the second input capacitor.

10. The converter of claim 9, wherein during the duration of T1 and the duration of T2, the input voltage vx is Vin/2.

11. The converter of claim 10, wherein in the first mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter charges as the inductor resists a change in current flow passing through the inductor.

12. The converter of claim 10, wherein in the second mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter discharges as the inductor resists a change in current flow passing through the inductor.

13. The converter of claim 10, wherein in the third mode of operation, the duration of T1 and the duration of T2 are the same, and in combination, the duration of T1 and the duration of T2 span across a switching period of the converter.

14. The converter of claim 10, wherein the first mode of operation and in the second mode of operation, the duration of T1 is provided during a portion of a first half of a switching period of the converter, and the duration of T2 is provided during a portion of a second half of the switching period of the converter.

15. The converter of claim 14, wherein in the duration of T1 and the duration of T2 are determined by the controller to maintain an overall constant average current through the inductor during the switching period of the converter.

16. The converter of claim 1 , wherein the flying capacitor unit is configured to restrict or clamp voltages passing through the first plurality of switches to Vin/2.

17. The converter of claim 1 , wherein the the flying capacitor unit is configured to restrict or clamp voltages passing through the second plurality of switches to Vin/2.

18. The converter of claim 1 , wherein the controller is configured to apply voltage programmed mode control to control the plurality of gate signals.

19. The converter of claim 1 , wherein the controller is configured to apply current programmed mode control to control the plurality of gate signals.

20. The converter of claim 1 , wherein at least one of the first plurality of switches and the second plurality of switches are rated for Vin/2.

21. A method for transferring power using a switched-capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched-capacitor voltage divider, the switched-capacitor voltage divider receiving an input voltage Vin, a two input inductive converter receiving an input voltage vx and providing an output voltage Vout, and a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx, the method comprising: controlling a plurality of gate signals applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2.

22. The method of claim 21 , wherein the first plurality of switches includes switches SW1 , SW2, SW3, and SW4; wherein SW1 and SW2 in combination, control power delivery to a first node, vx1 of the flying capacitor unit, and wherein SW3 and SW4 in combination, control power delivery to a second node, vx2 of the flying capacitor unit; wherein the second plurality of switches includes switches SW5 and SW6; and wherein SW5 and SW6, in combination, control power delivery to the two input inductive converter through the input voltage vx.

23. The method of claim 22, wherein the switches SW1 , SW2, SW3, SW4, SW5, and SW6 are controlled to maintain an equilibrium voltage across the first input capacitor and the second input capacitor.

24. The method of claim 23, further comprising: monitoring the voltages Vin and Vout; selecting a single mode of operation from three modes of operation based at least on the voltages Vin and Vout: a first mode of operation in use when Vout < ½ Vin, a second mode of operation in use when ½ Vin < Vout < Vin, and a third mode of operation in use when Vout = ½ Vin; wherein the controlling of the plurality of gate signals is based on the selected mode of operation.

25. The method of claim 24, wherein for the first mode of operation, vx is controlled to operate between Vin/2 and ground (0 V).

26. The method of claim 24, wherein for the second mode of operation, vx is controlled to operate between Vin and Vin/2.

27. The method of claim 24, wherein for the third mode of operation, vx is controlled to operate at or about a constant voltage, Vin/2.

28. The method of claim 26, wherein for each of the first, second, and third modes of operation, SW1 , SW3, and SW6 are active during a first time interval T1 , and SW2, SW4, and SW5 are active during a second time interval T2.

29. The method of claim 28, wherein during the duration of T1 , the switches SW1 , SW3, and SW6 are controlled to enable a parallel connection between the flying capacitor and the first input capacitor; and wherein during the duration of T2, the switches SW2, SW4, and SW5 are controlled to enable a parallel connection between the flying capacitor and the second input capacitor.

30. The method of claim 29, wherein during the duration of T1 and the duration of T2, the input voltage vx is Vin/2.

31. The method of claim 30, wherein in the first mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter charges as the inductor resists a change in current flow passing through the inductor.

32. The method of claim 30, wherein in the second mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter discharges as the inductor resists a change in current flow passing through the inductor.

33. The method of claim 30, wherein in the third mode of operation, the duration of T1 and the duration of T2 are the same, and in combination, the duration of T1 and the duration of T2 span across a switching period of the converter.

34. The method of claim 30, wherein in the first mode of operation and in the second mode of operation, the duration of T1 is provided during a portion of a first half of a switching period of the converter, and the duration of T2 is provided during a portion of a second half of the switching period of the converter.

35. The method of claim 34, wherein the duration of T1 and the duration of T2 are determined by the controller to maintain an overall constant average current through the inductor during the switching period of the converter.

36. The method of claim 21 , wherein the flying capacitor unit is configured to restrict or clamp voltages passing through the first plurality of switches to Vin/2.

37. The method of claim 21 , wherein the the flying capacitor unit is configured to restrict or clamp voltages passing through the second plurality of switches to Vin/2.

38. The method of claim 21 , wherein voltage programmed mode control is applied to control the plurality of gate signals.

39. The method of claim 21 , wherein current programmed mode control is applied to control the plurality of gate signals.

40. The method of claim 21 , wherein at least one of the first plurality of switches and the second plurality of switches are rated for Vin/2.

41. A computer readable medium storing machine readable instructions, which when executed by a processor, cause the processor to perform steps of a method for controlling power transfer through a switched-capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched-capacitor voltage divider, the switched-capacitor voltage divider receiving an input voltage Vin, a two input inductive converter receiving an input voltage vx and providing an output voltage Vout, and a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx, the method for controlling power transfer comprising: controlling a plurality of gate signals applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2.

42. The computer readable medium of claim 41 , wherein the first plurality of switches includes switches SW1 , SW2, SW3, and SW4; wherein SW1 and SW2 in combination, control power delivery to a first node, vx1 of the flying capacitor unit, and wherein SW3 and SW4 in combination, control power delivery to a second node, vx2 of the flying capacitor unit; wherein the second plurality of switches includes switches SW5 and SW6; and wherein SW5 and SW6, in combination, control power delivery to the two input inductive converter through the input voltage vx.

43. The computer readable medium of claim 42, wherein the machine readable instructions, when executed by the processor, cause the switches SW1 , SW2, SW3, SW4, SW5, and SW6 to be controlled to maintain an equilibrium voltage across the first input capacitor and the second input capacitor.

44. The computer readable medium of claim 43, wherein the machine readable instructions, when executed by the processor, further cause the processor to perform the steps of: monitoring the voltages Vin and Vout; selecting a single mode of operation from three modes of operation based at least on the voltages Vin and Vout: a first mode of operation in use when Vout < ½ Vin, a second mode of operation in use when ½ Vin < Vout < Vin, and a third mode of operation in use when Vout = ½ Vin; wherein the controlling of the plurality of gate signals is based on the selected mode of operation.

45. The computer readable medium of claim 44, wherein for the first mode of operation, vx is controlled to operate between Vin/2 and ground (0 V).

46. The computer readable medium of claim 44, wherein for the second mode of operation, vx is controlled to operate between Vin and Vin/2.

47. The computer readable medium of claim 44, wherein for the third mode of operation, vx is controlled to operate at or about a constant voltage, Vin/2.

48. The computer readable medium of claim 46, wherein for each of the first, second, and third modes of operation, SW1 , SW3, and SW6 are active during a first time interval T1 , and SW2, SW4, and SW5 are active during a second time interval T2.

49. The computer readable medium of claim 48, wherein during the duration of T1 , the switches SW1 , SW3, and SW6 are controlled to enable a parallel connection between the flying capacitor and the first input capacitor; and wherein during the duration of T2, the switches SW2, SW4, and SW5 are controlled to enable a parallel connection between the flying capacitor and the second input capacitor.

50. The computer readable medium of claim 49, wherein during the duration of T1 and the duration of T2, the input voltage vx is Vin/2.

51. The computer readable medium of claim 50, wherein in the first mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter charges as the inductor resists a change in current flow passing through the inductor.

52. The computer readable medium of claim 50, wherein in the second mode of operation, during the duration of T1 and the duration of T2, an inductor of the two input inductive converter discharges as the inductor resists a change in current flow passing through the inductor.

53. The computer readable medium of claim 50, wherein in the third mode of operation, the duration of T1 and the duration of T2 are the same, and in combination, the duration of T1 and the duration of T2 span across a switching period of the converter.

54. The computer readable medium of claim 50, wherein in the first mode of operation and in the second mode of operation, the duration of T1 is provided during a portion of a first half of a switching period of the converter, and the duration of T2 is provided during a portion of a second half of the switching period of the converter.

55. The computer readable medium of claim 54, wherein the duration of T1 and the duration of T2 are determined by the controller to maintain an overall constant average current through the inductor during the switching period of the converter.

56. The computer readable medium of claim 51 , wherein the flying capacitor unit is configured to restrict or clamp voltages passing through the first plurality of switches to Vin/2.

57. The computer readable medium of claim 51 , wherein the the flying capacitor unit is configured to restrict or clamp voltages passing through the second plurality of switches to Vin/2.

58. The computer readable medium of claim 51 , wherein voltage programmed mode control is applied to control the plurality of gate signals.

59. The computer readable medium of claim 51 , wherein current programmed mode control is applied to control the plurality of gate signals.

60. The computer readable medium of claim 51 , wherein at least one of the first plurality of switches and the second plurality of switches are rated for Vin/2.

61. The converter of claim 1 , wherein the controller is comprised of a PID compensator, a digital pulse width modular circuit, and a mode control logic circuit.

62. A controller for a converter having a switched-capacitor voltage divider having a first input capacitor and a second input capacitor and a first plurality of switches for controlling power flow to the switched-capacitor voltage divider, the switched-capacitor voltage divider receiving an input voltage Vin; a two input inductive converter receiving an input voltage vx and providing an output voltage Vout; and a flying capacitor unit connecting the switched-capacitor voltage divider and the two input inductive converter, the flying capacitor unit including a flying capacitor and a second plurality of switches controlling power flow to the two input inductive converter by controlling the input voltage vx; the controller comprising: a gate control circuit configured for generating a plurality of gate signals applied to both the first plurality of switches and the second plurality of switches based at least on the output voltage Vout, the plurality of gate signals controlled to maintain a voltage across each of the first input capacitor, the second input capacitor, and the flying capacitor equal to or about equal to Vin/2.