Publications
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda and Anshul Kumar. "Evaluation of
Bus Based Interconnect Mechanisms in Clustered VLIW Architectures",
IEEE/ACM Design Automation and Test in Europe (DATE05), Mar 2005, Munich, Germany.
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Anup Gangwar, M. Balakrishnan and Anshul Kumar. "Impact of Inter-cluster
Communication Mechanisms on ILP in Clustered VLIW Architectures",
2nd Workshop on Application Specific Processors
(WASP-2), in conjuction with 36 th IEEE/ACM Annual International Symposium on
Microarchitecture (MICRO-36), Dec 2003, San Diego, USA.
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Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant K. Dwivedi,
M. Balakrishnan and Anshul Kumar, "SoC Synthesis With Automatic Interface Generation",
16th IEEE/ACM International Conference on VLSI Design
(VLSI-2003), Jan 2003, New Delhi, India.
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Bhuvan Middha, Varun Raj, Anup Gangwar, Anshul Kumar, M. Balakrishnan
and Paole Ienne, "A Trimaran Based Framework for Exploring Design Space of VLIW ASIPs With
Coarse Grain Functional Units", 15th IEEE/ACM International Symposium on System
Synthesis (ISSS'02), Oct 2002, Kyoto, Japan.
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Refereed Technical Reports
Anup Gangwar, Jos T. J. van Eijndhoven, M. Balakrishnan and
Anshul Kumar, "Multi-Processor Multi-Tasking Performance Data Measurement and Visualization",
M.Tech thesis carried out partially at Philips Research Laboratories Eindhoven
and also available as Nat. Lab. Technical Note 2001/9 (Philips Company Restricted).
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Refereed Forum/Poster Presentations
Anup Gangwar, M. Balakrishnan and Anshul Kumar. "Customizing
Clustered VLIW Architectures with Focus on Interconnects and Functional Units",
SIGDA Ph.D. Forum at 41st IEEE/ACM Design Automation Conference
(DAC-41), Jun 2004, San Diego, USA.
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, and
Subhashis Banerjee, "SMPS: An FPGA-based Prototyping Environment for Multiprocessor Embedded Systems",
IEEE/ACM Thirteenth International Symposium on Field Programmable Gate Arrays (FPGA-2005),
Feb 2005, Monterey, USA.
Seminars
- A Tutorial on VHDL Synthesis, Place and Route for FPGA and ASIC Technologies
[ZIPPED PDF],
Embedded Systems Group Seminar Series, Oct 2004, Department of Computer Science and Engineering,
IIT Delhi, India.
- Implementation Characterstics of Interconnect Mechanisms in Clustered VLIW Architectures,
[ZIPPED PDF],
Ph.D. Thursday Seminar Series, Aug 2004, Department of Computer Science and Engineering,
IIT Delhi, India.
- Inter-cluster Communication in Clustered VLIW Architectures,
Inter Research Institute Student Seminars (IRISS-2004), Mar 2004,
Department of Computer Science and Engineering, IIT Bombay, India.
- Code Scheduling Techniques for VLIW Architectures and Their Applicability to
Clustered Architectures
[ZIPPED PDF],
Ph.D. Thursday Seminar Series, Mar 2004, Department of Computer Science and Engineering,
IIT Delhi, India.
- Evaluating Inter-cluster Communication in Clustered VLIW Architectures,
[ZIPPED PDF],
Ph.D. Thursday Seminar Series, Sep 2003, Department of Computer Science and Engineering,
IIT Delhi, India.
- Synthesis and Testing of LEON Soft Processor Core Over ADM-XRC
[ZIPPED PPT],
Embedded Systems Group Seminar Series, Aug 2002, Department of Computer Science and Engineering,
IIT Delhi, India.
- Ph.D. Research Plan Presentation
[ZIPPED PPT],
SRC Presentation, Jun 2002, Department of Computer Science and Engineering, IIT Delhi, India.
- Framework for studying effect of VLIW encoding and decoding schemes
[ZIPPED PPT],
Minor-project Presentation, Nov 2001, Department of Computer Science and Engineering,
IIT Delhi, India.
- A Brief Introduction to The Trimaran Compiler Research Infrastructure from
UIUC and NYU
[ZIPPED PPT],
Embedded Systems Group Seminar Series, Mar 2001, Department of Computer Science and Engineering,
IIT Delhi, India.
- Instruction Level Parallelism for Low-Power Embedded Processors (Ph.D. thesis of
Jean Michel-Puiatti, EPFL)
[ZIPPED PPT],
Embedded Systems Group Seminar Series, Jan 2001, Department of Computer Science and Engineering,
IIT Delhi, India.
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