Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456 DCC 2004 Accepted Abstracts
Designing Correct Circuits 2004
27-28 March, Barcelona
A satellite event of the ETAPS
2004 group of conferences
Abstracts Accepted for Presentation
Robert Clarisó and Jordi Cortadella
(Universitaat Politécnica de Catalunya)
Verification of Parametric Timed Circuits using
Octahedra [.ps]
Anthony Fox (University of Cambridge)
Formal Verification of the ARM Block Data Transfer
Instructions [.pdf]
René Krenz and Elena Dubrova
(Royal Institute of Technology, Stockholm)
Trading Completeness for Capacity using
Probabilistic Techniques [.pdf]
Koen Claessen and Jan-Willem Roorda
(Chalmers University of Technology)
Symbolic Trajectory Evaluation using a SAT Solver [.ps]
Anna Slobodová and Krishna Nagalla
(Intel)
Formal Verification of Floating Point
Multiply Add on Itanium® Processor [.ps]
Emil Axelsson, Koen Claessen, and Mary Sheeran
(Chalmers University of Technology)
Wired - a Language for Describing Non-Functional
Properties of Digital Circuits [.pdf]
Ganesh Gopalakrishnan and Ching-Tsun Chou
(University of Utah and Intel)
The Post-Silicon Verification Problem:
Designing Limited Observability Checkers
for Shared Memory Processors
[.pdf]
Mike Gordon
(University of Cambridge)
Applying theorem proving to formal property
languages [.pdf]
Warren A. Hunt, Jr. and Erik Reeber
(University of Texas at Austin)
A Hierarchical Modeling System [.pdf]
Mike Kishinevsky and Gérard Berry
(Intel and Esterel Technologies)
Late design changes (ECO) for sequentially
optimized high-level designs [.pdf]
Koen Claessen and Johan Mårtensson
(Safelogic AB, Chalmers University of Technology,
and Gothenburg University)
An Operational and Denotational Semantics for
Safety Properties in PSL [.ps]
Andrew K. Martin
(IBM)
HML: A language for high-level design of
high-frequency circuits [.pdf]
Maher Mneimneh and Karem Sakallah
(University of Michigan)
Structure-Driven Equivalence Verification
for Circuits Optimized by Retiming and
Combinational Synthesis [.pdf]
John O'Donnell
(University of Glasgow)
Integrating Formal Methods with Digital Circuit
Design in Hydra [.ps]
Jim Grundy, Tom Melham, and John O'Leary
(Intel and University of Oxford)
A Reflective Functional Language for Hardware
Design and Theorem Proving [.pdf]
Jin Yang, Rami Gil, and Eli Singerman
(Intel)
satGSTE: Combining the Abstraction of GSTE with the
Capacity of a SAT Solver [.ps]