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D J Greaves
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Dr. D J Greaves.

D J Greaves, MA, PhD, MIEE.

Senior Lecturer, member of Systems Research Group, Home Networking Subgroup and Computer Architecture Group, of the University of Cambridge Computer Laboratory.

DJ Greaves is a Senior Lecturer in Computing Science and a Fellow of Corpus Christi College .
Consult Google regarding:

Short (auto-)biography: Sep 07        Photo with a tie: A, B.

  • Jan 08: AutoHAN news: We have replaced pushlogic bytecode with .net IL bytecode at the compiler back end, for embedded tuplecore execution and for code reflection. Paper in preparation!

  • Jan 08: Describing Hardware with Parallel Programs, joint work with Satnam Singh, accepted for DCC'08.

  • Dec 07: Presentation at Configcon07. Slides (local access only): here.

  • Dec 07: Rediscovered an audio broadcast discussion the Cambridge iTV Trial LINK-WILLBE-HERE.

  • Nov 07: Compiled a first C# example to hardware RTL Times Table Demo.

  • Sept 07: DJG Sabbatical Leave Starts

  • Sept 07: Journal publication by my student B Bastani: High-level Open Evolvable Systems Design By Process-oriented Modeling: Application to DNA Replication Mechanism accepted for ACM Software Engineering Notes Nov 07.

  • Sept 07: Communication-centric computation (C3D) project grant approved by EPSRC (Moore, Mycroft, Mullins, Greaves).

  • June 07: Trade sale of Tenison EDA to Arc International. (Tenison was founded by DJG in March 2000.)

  • Older news link...

    • Reading Group

    Our reading group meets every tuesday during term in SC01 at 3:20 pm. WIKI. Reading group mission statement: "We look at joining components together. This involves having the components and the glue, of course, but also the necessary information to find and select the components, to know they will fit and to know what the consequences will be" .

    Current Activities Blog: 3Q07

  • Collaboration with Satnam Singh on Hardware Synthesis from .net CIL ByteCode: Timestable Demo.

  • Extending the Orangepath H2 compiler to generate logic with super pipelineing and out-of-order execution as required by random access times to cached DRAM banks, and a couple of related papers.

  • Experimenting with .net CIL version of Pushlogic.

  • Extending the Pushlogic bundle meta-info to support assume/guarantee reasoning capability rather than trying to model check the whole of a domain.

  • Viewing dynamic binding in IDE/UML systems.

    Research in Progress: System Design Methodology

    Older Research Areas,     Conference Program Committees,     Recent Publications,     Draft Publications,     Minor Research Notes,     Phd Students,     Undergraduate Teaching,     Miscellaneous Projects,     System Design Methodology.