Saar Drimer
Welcome.
As of October 2005, I am researching towards a PhD degree at the University of Cambridge, with the general topic being "hardware security". I am mainly interested in the security attributes of programmable logic devices, though I've been involved with several interesting projects on banking systems security. My research is funded by a generous grant from Xilinx.
I am part of the Security Research Group in the Computer Laboratory and am being supervised by Dr. Markus Kuhn. I'm a member of Darwin College. Previously, I worked as a Design Engineer for Xilinx's Advanced Product Division in San Jose, California after receiving my BSc in Computer Engineering from UC Santa Cruz.
I was born and raised in Israel, most of the years living in Jerusalem. Every now and then I write personal observations about the world on my weblog, "Side Channels".
I started and maintain the FPGA design security bibliography.
I am was convener of our group's security seminar series.
Contact Info
Saar Drimer
University of Cambridge
Computer Laboratory
15 JJ Thomson Avenue
Cambridge CB3 0FD
United Kingdom
<firstname>.<lastname>@cl.cam.ac.uk (email is by far the best way to reach me).
some output:
Saar Drimer, Tim Güneysu, Markus G. Kuhn and Christof Paar:
Protecting multiple cores in a single FPGA design,
Draft, written 5/2008, availavle on-line 8/2008.
Saar Drimer:
Securing SRAM FPGA designs in distribution and in operation,
invited talk, CryptArchi, 06/2008, Trégastel, France
Saar Drimer, Steven J. Murdoch and Ross Anderson:
Thinking inside the box: system-level failures of tamper proofing,
IEEE Symposium on Security and Privacy, 5/2008. Awarded "Most Practical Paper".
[extended version] [FAQ] [related BBC video]
Saar Drimer, Tim Güneysu and Christof Paar:
DSPs, BRAMs and a pinch of logic: new recipes for AES on FPGAs,
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 4/2008.
[bibtex] [source code]
Saar Drimer:
Volatile FPGA design security -- a survey,
unpublished, 4/2008 (version 0.96).
[bibtex]
Saar Drimer and Steven J. Murdoch:
Keep your enemies close: distance bounding against smartcard relay attacks,
16th USENIX Security Symposium, 8/2007. Awarded "Best Student Paper".
[bibtex] [USENIX slides] [poster] [related BBC video]
Saar Drimer:
Authentication of FPGA bitstreams: why and how,
3rd workshop of Applied Reconfigurable Computing, 3/2007.
[bibtex]
Austin Lesea, Saar Drimer, Joe Fabula, Carl Carmichael and Peter Alfke:
The Rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs,
IEEE Transactions on Device and Materials Reliability (invited paper), 9/2005.
[bibtex]
patents:
Saar Drimer, Jason Moore and Austin Lesea:
Circuit for and method of implementing a plurality of circuits on a programmable logic device,
US Patent #7408381, issued 8/2008 (filed 2/2006).
[USPTO]
Saar Drimer:
Total configuration memory cell validation built in self test (BIST) circuit,
US Patent #7409610, issued 8/2008 (filed 7/2005).
[USPTO]
Austin Lesea, Saar Drimer:
Method of measuring the performance of a transceiver in a programmable logic device,
US Patent #7218670, issued 5/2007 (filed 11/2003).
[USPTO]
Media (I appear in):
BBC Two's "Newsnight" segment on vulnerabilities in Chip and PIN "PIN entry devices" (PEDs), 2/2008. Part 1 and part 2.
BBC One's "Watchdog" segment on Chip and PIN relay attacks, 2/2007
Chip and PIN payment terminal playing Tetris (yes, that's my hand!), 12/2006
I sometimes write articles for our group's weblog, Light Blue Touch Paper [my posts].