SU674033A1 - Digital band-pass filter with finite duration function - Google Patents

Description

. : .one , ,, .;.;; The invention relates to a special camcorder van cf a computer monitor. 8 units can be used to process radar, acoustic and hydroacoustic signals. A digital filter is known that realizes the approximation of frequency characteristics by reference functions by means of a “trace” connection of a comb filter with uniform {assay of zeros in the IS-plane and a set of parallel p 30Hat opoB, the poles of which are combined with the corresponding zero of the comb filter G11. The disadvantage of the filter is a large amount of RAM. The closest technical solution to the present invention is a bandpass filter with a finite length of the weighting function, containing the first and second memory blocks, the first and second address counters, registers, AND elements, multiplier, adder and analog, digital converter, and ne: gaLe / INPUT of the first memory block is connected to the n by the formation input of the device, the second input is from | the first address counter, and alhDO, to the input of the first register, the output of which is connected to the first input of the multiplier, the second input of the multiplier is connected to the output of the element I, and the output to the input of the second register, the output of which is connected to the second input of the adder, the output of the second address iodine counter to the ne {th input of the second memory block, the output of which is connected to the input of the third register is connected to the first inputs of the element I, and the fourth register, the output of which is connected to the second input of the summat, output of the adder is connected to in The house of the analog-digital converter, the output of the latter is the information input of the device 21. The disadvantage of this filter is a large amount of RAM for recording the previous values of the input signal, as well as a large number of arithmetic operations for the quantum period (for example, the input signal). function. The purpose of the invention is to simplify the filter. The goal is achieved by introducing the fifth, sixth, seventh and eighth registers into the filter, the output of the adder being connected to the inputs five O and the sixth registers, with the second input of the second memory block and with the first inputs of the seventh and eighth registers, the outputs of which are connected to the third and fourth inputs of the AND element, the output of the fifth and sixth registers C vdinyon1 respectively with the hot and third inputs of the four-cheloved register , and the Bxojijibf of the seventh and eighth registers are connected to the yMHoxtkrena output, the second inputs of the third and sixth regiograms are connected to the information inputs of the device. In the drawing there is a block diagram of a janned bandpass filter. The filter contains blocks 1, 2 of memory, address counters 3, 4, registers 5-12, element I 13i multiplier 14, adder G5, en 1-digital converter 16 information) “ibnnye inputs 17, 18, in4H5rMATIONNY YIINSOD 19 .:, ; The algorithm of the proposed QF includes the following sequence of operations: quadratic modulation of the input signal) which makes it possible to combine the problem of full-field filtering of the wideband signal Xf relative to the center frequency; often l / v with sampling counting at the output: FILTER::;;,:, -.: V: I if V rnK. JJ W К «2 W ve (2 Ve« o Ve ee «vM f if vf mK where K O, 1, 2 , ... i irrt - keffvdien fractions, a multiple of the duration / V of the weight function he is low full filter, defined by the ratio of the input width of the input signal to the filter bandwidth}, restoration of the interface: 1 in-person sample of the signal from the output of the low-pass filter vJ.ng.-L - / - -, f. where is the weighting function interpol of the torus; quadrature modulation, which performs the reverse transfer of the spectrum of the filtered signal V to the central frequency region w, where the first computer clock begins with writing the current count of the input cHrHajna Xj / vfm + {niodni input 17, into the memory register 7 and the current reference modulating function in register. 5 from memory block 1 in the initial state of the address counter 3. With the opening of the element AND 13, the contents of the registers: S and 7 are fed to the corresponding arms of the multiplier 14. The result of the recording is written into the memory register 10. The current count of the modulating function is written to register 5 jnWgV from memory block 1 with the corresponding state of the address counter 3. The result of the product from the output of the multiplier 14 is filled into the register 9. To; The quadrature 18 input signals are stored in registers 9 and 1O for the entire time interval required for processing: According to the received addressing structure, the entire memory of memory block 2 is divided into four equal parts. memory cells inside each of the first steps — with the help of the address counter, 4 fogg. slots. Suppose for the moment you are looking at, the time of the 4 address is in the following state: fti - i, which corresponds to G Mu intermediate cycle, moreover, the weights are fed to the input of register 5 from memory 1; The sequence of the fault: computational cycles of operation of the device in RAM; low-pass filtering by thinning and restoring intermediate bills begins with the calculation of the current: The values of the intermediate variable V and the initial result of the partial amount for the current sample have none of the output of the transponder 5 The computational beat includes the following sequence of operations; zapar in register S of weight coefficient hu о j23 of memory block 1 with co .. fi-VmoOia -. , .. | the corresponding state of the address counter 3 ;; . write to register 7 Ps.r, from memory block 2; multiplying the contents of register 5 by; the contents of the regsptra 10 when opening the element And 13;

At the end of the computational taiga in question, a control pulse is fed to the input of the address counter 4 and, in accordance with the addressing system adopted, in the following computational cycle from # 5 and 5 of memory block 2 is sequentially written to register 7

R ivrb j i-5b VHi-i) mb

recording the product from the output of multiplier 14 to register 8;

overwriting the contents of register 7 into register 6 ;.

with the contents of the registers 6 and 8 on the combinational adder 15;

recording the amount received in the memory cell of memory 2;

recording to the registrar 7irntY j from the memory cell of memory block 2;

multiplying the contents of register 5 by the contents of register 9 with the opening of the element I 13 ;,

recording the output JmCWy tiVmodnj q output multiplied ate 14 to register 8;

niepeaanBcfe register contents 7 to register 6 ;.

summation of the contents of registries in 6 and 8 on the combiadion adder 15;

recording the amount received in the memory cell of memory 2;

writing to register 7 the numbers from memory location 2 TfTi of memory location 2;

multiplying the contents of register 5 by the contents of register 7 when opening the element I 13; f:

Record PROVISION LEVER VJM: ". 1to THN-UTLL

from the output of the multiplier 14 to the register 8;

setting register zero to 6;

the summation of the contents of registers 6 and 8 on the combinational adder 15;

write the amount received in the register

L1; : -. ;; -

writing to the register 7 the numbers from the memory cell of the i-i of the memory block 2; multiplying the contents of register 5 by the contents of register 7 when opening element 13;

recording the product im 1) n, 1 hw-vniodm from the output of the multiplier 14 to the register 8;

setting register zero to 6;

summarizing the contents of registers 6 and 8 on the combinational adder 15;

recording the amount received to register 12 At the same time, the weight coefficient is written to register 5 from the block 1 cc.

wrm-vmodm.vP as a result of performing a sequence of operations 1-13 in the memory cells / - i 1 and 3 - i ' 1, new values of the real and imaginary parts of the intermediate variables are recorded. Noah corresponding to the paccMaTptmame of time. In the following sequence of operations 14-25, for all computational cycles tO, instead of setting the register 6 to zero, the following operations are performed:

overwriting the contents of register 11 into register 6;

: overwriting the contents of register 12 into register 6. In this case, as a result of carrying out the sequence of operations 14-25, registers 11, 12 record the real and imaginary parts of the new value of the partial sum, -, respectively,

V.

V.il w-Vrnft m) N-m-V ™ xin,

At the end of the last computational cycle, the numbers are written in the corresponding memory cells of the pashgi block 2, the current values are intermediate between 1x and 1m, and the registers 11, 12 are recorded, respectively, of the actual values and sets of the current value of the incremented signal Vy at the interpolator output.

Claims (1)

 In the final computational cycle, the modulation of the signal V ;, is performed. For this purpose, in E numerical cycle - / real and imaginary part of the current value of the signal received halfway at the output of the combinational adder 15, in parallel with the record in register 11, 12 are recorded in registers 9, 10. The final computational beat is opened by writing to register 5 from the block Memory 1 of the current reference of the modulating function Cos WsjV- At the same time, the element E 13 n opens to the corresponding; The input input to the multiplier 14 is the contents of the register 10B to the EUSUZ, The resulting product e / jsU IcosS jV from the output of the multiplier 14; is written to register 8. Register 6 is set to zero cocrosraae, and the contents of register 8 are overwritten through the combinational adder 15 to register 11. When you open the AND 13 element, the contents of register 9 T C / Z are applied to the corresponding input of the multiplier 14, to the second input of which the current count is applied modulating function recorded in register S. The resulting sinWoV product from the output of multiplier 14 is written to register 8. At the same time, the contents of register 11 are overwritten in register 6. The current value of the output of the film is. - - - ---:. Re J COS w I fv | j Sm from the output of the combinational adder 15,: is written to the input register of the digital-to-analog converter 16. The design of the proposed structural implementation leads to y1 "4 reduction in the amount of RAM and the number of arithmetic operations per input count in comparison with the usual execute convolution operations by times, where t is the decimation factor of the input counts (E (interconnect), / determined from the ihirin spectrum of the 1st filter signal to its bandwidth, transmission. Thus, the considered algorithm Ltration is most effective when using narrowband filters with a finite duration of the weighting function. In addition, the introduction of a quad modulated structure allows the creation of filter filters to synthesize the corresponding low-pass filter, allowing for easy iiere tuning of the filter along the center frequency of the band; The invention of the Digital bandpass filter with a finite duration of the weighting function, containing the first and second memory blocks, the first and second address counters, registers, electronic The Ient, multiplier, adder and analog-to-digital converter, the first input of the first Pamzati unit is connected to the information input of the device, the second input to the output of the first iary counter, and the output to the input of the first register, whose output is connected to the first input of the multiplier, the second input of the multiplier is connected to the output of the element I, and the output is connected to the input of the second register, whose input is connected to the first input of the adder, the output of the second counterHoro counter is connected to the first 1 in 6 of the second memory block, the output of KOTOR is connected to the input The third register, the output of the third register is connected to the twisted inputs of the circuit I and I and the quad Sx3 register, the output of which is connected to the second input of the sum of the sum, the adder is connected to the input of the analogue converter, the output of the last is informational output, the output device, the output signal, that, in order to simplify the filter, we introduce a PY1MY, a shine, a seventh and a d6th registers, with the adder connected to the inputs of the fifth and sixth rvGySt) It, with the second Vtorush | 1C | IHaaaaaaaaaa ya and vrd.Shgyo jserHc ipp B what was done to exit uyo e1 ., Soviet Radio, 1973. / 2. Author's certificate 516043, cl. O 06 I 15/36, 1976, 18 4L t / tf