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US6909157B2 - Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors - Google Patents
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US6909157B2 - Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors - Google Patents

Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors Download PDF

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US6909157B2
US6909157B2 US10/652,307 US65230703A US6909157B2 US 6909157 B2 US6909157 B2 US 6909157B2 US 65230703 A US65230703 A US 65230703A US 6909157 B2 US6909157 B2 US 6909157B2
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layer
uniformity
nitrided
gate dielectric
highly
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Jay S. Burnham
James S. Nakos
James J. Quinlivan
Steven M. Shank
Deborah A. Tucker
Beth A. Ward
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Meta Platforms Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01346—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Definitions

  • the present invention relates to transistor design, and, in particular, a thermal nitrogen deposition method to improve the uniformity of the nitrided layer of a gate capacitor of a transistor.
  • CMOS devices have driven gate oxide thicknesses to less than 20 ⁇ , with inversion and physical thicknesses trending to less than 20 ⁇ .
  • the leakage currents through these gates exponentially increase due to more direct tunneling of electrons and holes through the potential barriers of the dielectric. This can affect device properties by causing higher standby power consumption, reliability problems, and degradation of certain chip functions such as timing.
  • Battery powered devices for mobile applications for example, have some of the strictest requirements for leakage current, where lower leakage currents produce longer battery life.
  • FIG. 1 shows a transistor structure with the gate dielectric ( 20 ).
  • Gate leakage current is defined as the current from gate to drain when Vg ( 22 ) is less than the threshold voltage of the device. This current is an exponential function of thickness, with the current increasing by 2-3X for every 1 ⁇ decrease in thickness, in the sub-20 ⁇ thickness range for a gate dielectric layer that is formed using SiO 2 .
  • RPN Remote plasma nitridation
  • DPN decoupled plasma nitridation
  • the present invention relates to a method for improving the uniformity of the nitrided layer that is formed over the base SiO 2 layer of a transistor gate dielectric, thus lowering the leakage current through the base SiO 2 layer.
  • FIG. 1 shows a transistor used to define gate leakage current.
  • FIG. 2 shows the cross-sectional profile of a wafer, comprising the base oxide layer and the nitrided layer formed by any nitrogen-deposition process.
  • FIG. 3 shows the cross sectional profile of a wafer, comprising a first base oxide layer, a second nitrided layer formed by any nitrogen-deposition process, and a third NO annealed layer.
  • FIG. 2 shows the cross sectional profile of a wafer used as a gate dielectric.
  • a base oxide layer for example, silicon dioxide (SiO 2 )
  • the base oxide layer can be between 5 ⁇ and 20 ⁇ thick.
  • the base oxide layer is usually approximately 10 ⁇ thick.
  • nitrogen is deposited in the base oxide layer using RPN or DPN, resulting in a highly-nitrided second layer ( 26 ) containing a high concentration of nitrogen.
  • This highly-nitrided second layer can be anywhere between 10 ⁇ -30 ⁇ thick.
  • RPN and DPN result in this highly-nitrided second layer having a non-uniform physical profile.
  • FIG. 2 shows the situation where the height of the second layer is greater in the middle than at the edges of the profile.
  • FIG. 2 shows only this one irregular profile.
  • Other irregular profiles such as where, for example, the edges of the highly nitrided layer are higher than the middle of the highly nitrided layer are possible as well, are not shown.
  • FIG. 2 defines h max as the highest point of the highly-nitrided second layer above the base oxide layer and h min as the lowest point of the highly-nitrided second layer above the base oxide layer.
  • RPN and DPN also results in a non-uniform deposition of nitrogen within the highly-nitrided second layer.
  • Table 2 shows nitrogen concentrations between the center and the edge of the highly-nitrided second layer differing by 3 ⁇ 10 14 atoms/cm 3 .
  • FIG. 2 Subjecting this structure shown in FIG. 2 (i.e., a two-layer structure comprising a base oxide layer and a highly-nitrided second layer) to a nitric thermal anneal process reduces the non-uniformity of the profile of the highly-nitrided second layer, resulting in the cross-sectional profile shown in FIG. 3 .
  • the resulting structure has a base oxide layer ( 24 ), a highly nitrided second layer ( 26 ), and a NO (nitric oxide) anneal layer ( 28 ).
  • the NO anneal layer can be between 1 ⁇ and 30 ⁇ thick, and is typically between 1 ⁇ and 5 ⁇ thick.
  • Subjecting this structure shown in FIG. 2 to a nitric thermal anneal process also reduces the non-uniformity of nitrogen deposition concentration within the highly-nitrided second layer, as shown in Table 2. Two methods can be used to carry out this nitric thermal anneal.
  • a plurality of wafers on which a base oxide layer and a highly-nitrided second layer have been formed are put into an annealing furnace.
  • the time, temperature, and pressure of the annealing process can be varied to achieve the maximum uniformity of the nitric anneal layer.
  • the wafers are exposed to a range of temperatures for times ranging from 5 minutes to 30 minutes.
  • the temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade.
  • the pressure to which the wafers are exposed during this process can range between 1-760 torr.
  • gas is allowed to flow over the surface of the wafers.
  • This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO.
  • the gas is heated to a temperature in the range of 800-1100 degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers.
  • the gas is heated to 950 degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers.
  • single wafer tools are used to perform the annealing process instead of an annealing furnace.
  • the annealing furnace allows a batch of wafers to undergo thermal annealing at one time
  • single wafers are subjected to the annealing process at one time.
  • the time, temperature, and pressure parameters to which the wafers are exposed are the same as in the first embodiment described previously.
  • the wafers are exposed to a range of temperatures for times ranging from 5 seconds to 30 minutes.
  • the temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade.
  • the pressure to which the wafers are exposed during this process can range between 1-760 torr.
  • gas is allowed to flow over the surface of the wafers.
  • This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO.
  • the gas is heated to a temperature in the range of 800-1200 degrees Centigrade before being allowed to pass over the wafers.
  • the gas is heated to 950 degrees Centigrade before being allowed to pass over the wafers.
  • the advantage of the first embodiment discussed above is that several wafers can be annealed at once.
  • the advantage of the second embodiment is that, in a single wafer process, the required temperature and pressure can be reached in a shorter period of time.
  • Table 1 shows the results obtained for two furnace annealing processes accomplished under the conditions shown. These data are obtained by optical measuring:
  • elliptical thickness represents the thickness of the highly-nitrided layer after the various processes shown
  • range shows the difference between the highest and lowest points of the cross-sectional profile of the top of the highly-nitrided layer. All unit measurements shown are in angstroms. As the data above shows, the furnace annealing processes reduces the range; that is, the difference between the highest and lowest points on the cross-sectional profile of the top of the highly nitrided layer.
  • Table 2 shows data obtained from the furnace annealing process measured by secondary ion mass spectrometry.
  • Process 1 yielded a physical elliptical uniformity of 2.85%.
  • Process 2 yielded a physical elliptical uniformity of 2.08%.
  • Process 3 yielded a physical elliptical uniformity of 1.42%.
  • Process 1 in which no anneal was performed, yielded a dose uniformity of 67% and a concentration uniformity of 77%.
  • Process 2 yielded a dose uniformity of 89% and a concentration uniformity of 100%.
  • Process 3 yielded a dose uniformity of 88% and a concentration uniformity of 97%.
  • the Furnace 1 process is a furnace annealing process for 13 minutes N 2 O 700 C (950C precombustion chamber temperature).
  • the Furnace 2 process is a furnace annealing process at 26 minutes N 2 O 800 C (950C precombustion chamber temperature).

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.

Description

REFERENCE TO RELATED APPLICATION
This is a division of application Ser. No. 10/206,427, filed Jul. 26,2002, now U.S. Pat. No. 6,706,644; issued Mar. 16,2004.
FIELD OF INVENTION
The present invention relates to transistor design, and, in particular, a thermal nitrogen deposition method to improve the uniformity of the nitrided layer of a gate capacitor of a transistor.
BACKGROUND OF THE INVENTION
The speed requirements for high-performance 0.13 um CMOS devices has driven gate oxide thicknesses to less than 20 Å, with inversion and physical thicknesses trending to less than 20 Å. As the dielectric layers are scaled thinner, the leakage currents through these gates exponentially increase due to more direct tunneling of electrons and holes through the potential barriers of the dielectric. This can affect device properties by causing higher standby power consumption, reliability problems, and degradation of certain chip functions such as timing. Battery powered devices for mobile applications for example, have some of the strictest requirements for leakage current, where lower leakage currents produce longer battery life.
FIG. 1 shows a transistor structure with the gate dielectric (20). Gate leakage current is defined as the current from gate to drain when Vg (22) is less than the threshold voltage of the device. This current is an exponential function of thickness, with the current increasing by 2-3X for every 1 Å decrease in thickness, in the sub-20 Å thickness range for a gate dielectric layer that is formed using SiO2.
Remote plasma nitridation (RPN) or decoupled plasma nitridation (DPN) are methods used to introduce large concentrations of nitrogen into the gate dielectric layer, thereby forming a silicon oxynitride gate dielectric. With the incorporation of nitrogen, the gate leakage current can by reduced. This is mainly due to increasing the capacitance of the layer which allows for larger physical thicknesses with the same electrical thickness. There is also some reduction in leakage current due to the change in chemical bonding at the dielectric-Si substrate interface. These particular processes are desirable due to their ability to incorporate large concentrations of nitrogen (>4×1021 at/cm3) and their ability to control the profile of the nitrogen throughout the dielectric layer. These process techniques however, can be inherently non-uniform, thus causing a large non-uniformity of device parameters across the wafer. Non-uniformity of device parameters can cause severe yield degradation in chip performance if certain specifications are out of range. These electrical parameters can include leakage current, electrical thickness, threshold voltage, and device current. This invention addresses this non-uniformity, and demonstrates that the physical thickness and nitrogen concentration is improved by making use of the techniques described in the invention.
SUMMARY OF THE INVENTION
The present invention relates to a method for improving the uniformity of the nitrided layer that is formed over the base SiO2 layer of a transistor gate dielectric, thus lowering the leakage current through the base SiO2 layer.
DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a transistor used to define gate leakage current.
FIG. 2 shows the cross-sectional profile of a wafer, comprising the base oxide layer and the nitrided layer formed by any nitrogen-deposition process.
FIG. 3 shows the cross sectional profile of a wafer, comprising a first base oxide layer, a second nitrided layer formed by any nitrogen-deposition process, and a third NO annealed layer.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 shows the cross sectional profile of a wafer used as a gate dielectric. First a base oxide layer (24), for example, silicon dioxide (SiO2), of the wafer is formed using known techniques, such as RTO or furnace oxidation. The base oxide layer can be between 5 Å and 20 Å thick. The base oxide layer is usually approximately 10 Å thick. Next, nitrogen is deposited in the base oxide layer using RPN or DPN, resulting in a highly-nitrided second layer (26) containing a high concentration of nitrogen. This highly-nitrided second layer can be anywhere between 10Å-30 Å thick. However, RPN and DPN result in this highly-nitrided second layer having a non-uniform physical profile. FIG. 2 shows the situation where the height of the second layer is greater in the middle than at the edges of the profile. FIG. 2 shows only this one irregular profile. Other irregular profiles, such as where, for example, the edges of the highly nitrided layer are higher than the middle of the highly nitrided layer are possible as well, are not shown. FIG. 2 defines hmax as the highest point of the highly-nitrided second layer above the base oxide layer and hmin as the lowest point of the highly-nitrided second layer above the base oxide layer.
In addition to RPN's and DPN's resulting in the non-uniform physical structure of this highly-nitrided second layer, RPN and DPN also results in a non-uniform deposition of nitrogen within the highly-nitrided second layer. For example, Table 2 shows nitrogen concentrations between the center and the edge of the highly-nitrided second layer differing by 3×1014 atoms/cm3.
Subjecting this structure shown in FIG. 2 (i.e., a two-layer structure comprising a base oxide layer and a highly-nitrided second layer) to a nitric thermal anneal process reduces the non-uniformity of the profile of the highly-nitrided second layer, resulting in the cross-sectional profile shown in FIG. 3. The resulting structure has a base oxide layer (24), a highly nitrided second layer (26), and a NO (nitric oxide) anneal layer (28). The NO anneal layer can be between 1 Å and 30 Å thick, and is typically between 1 Å and 5 Å thick. Subjecting this structure shown in FIG. 2 to a nitric thermal anneal process also reduces the non-uniformity of nitrogen deposition concentration within the highly-nitrided second layer, as shown in Table 2. Two methods can be used to carry out this nitric thermal anneal.
In a first embodiment of the present invention, a plurality of wafers on which a base oxide layer and a highly-nitrided second layer have been formed are put into an annealing furnace. The time, temperature, and pressure of the annealing process can be varied to achieve the maximum uniformity of the nitric anneal layer. The wafers are exposed to a range of temperatures for times ranging from 5 minutes to 30 minutes. The temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade. The pressure to which the wafers are exposed during this process can range between 1-760 torr. During the time when the wafers are in the furnace exposed to the annealing temperature and pressure, gas is allowed to flow over the surface of the wafers. This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO. The gas is heated to a temperature in the range of 800-1100 degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers. Preferably, the gas is heated to 950 degrees Centigrade before being admitted into the furnace and allowed to pass over the wafers.
In a second embodiment of the present invention, single wafer tools are used to perform the annealing process instead of an annealing furnace. In other words, while using the annealing furnace allows a batch of wafers to undergo thermal annealing at one time, in this embodiment, single wafers are subjected to the annealing process at one time. The time, temperature, and pressure parameters to which the wafers are exposed are the same as in the first embodiment described previously. The wafers are exposed to a range of temperatures for times ranging from 5 seconds to 30 minutes. The temperatures to which the wafers are exposed can range between 500-1100 degrees Centigrade. The pressure to which the wafers are exposed during this process can range between 1-760 torr. During the time when the wafers are exposed to the annealing temperature and pressure, gas is allowed to flow over the surface of the wafers. This gas can be any gas which under the temperature and pressure conditions under which the anneal is performed dissociates into NO. The gas is heated to a temperature in the range of 800-1200 degrees Centigrade before being allowed to pass over the wafers.
Preferably, the gas is heated to 950 degrees Centigrade before being allowed to pass over the wafers.
The advantage of the first embodiment discussed above is that several wafers can be annealed at once. The advantage of the second embodiment is that, in a single wafer process, the required temperature and pressure can be reached in a shorter period of time.
The following table (Table 1) shows the results obtained for two furnace annealing processes accomplished under the conditions shown. These data are obtained by optical measuring:
Furnace
Anneal for 26
Furnace Anneal minutes N2O
for 13 minutes 800 C (950C
N2O 700 C (950C precombustion
precombustion chamber
chamber temperature)
temperature) Elliptical Std. Elliptical Std.
Process/sequence thickness Range Dev. Thickness Range Dev.
RPN 21.44 A 2.24 A  0.5 A 21.34 A 1.91A 0.47A
RPN/Furnace 22.46 A 1.38 A 0.33 A 24.17 A 0.93 A 0.28 A
anneal
RTO/RPN 20.27 A 1.53 A 0.39 A 20.04 A 1.05 A 0.27 A
RTO/RPN/Furnace 23.04 A 0.70 A 0.18 A 26.11 A 0.98 A 0.24 A
Anneal
Where: (a) elliptical thickness represents the thickness of the highly-nitrided layer after the various processes shown; and (b) range shows the difference between the highest and lowest points of the cross-sectional profile of the top of the highly-nitrided layer. All unit measurements shown are in angstroms. As the data above shows, the furnace annealing processes reduces the range; that is, the difference between the highest and lowest points on the cross-sectional profile of the top of the highly nitrided layer.
The following table (Table 2) shows data obtained from the furnace annealing process measured by secondary ion mass spectrometry.
SIMS N
Elliptical TOF-SIMS SIMS N dose concentration
Process Wafer site thickness Thickness (e14 al/cm3) (e21 at/cm3)
1. RTO/RPN Center 20.14 A 15.0 A 9 4
(no anneal) Edge 19.02 A 17.0 A 6 3
Mean 19.65 A
2. RTO/RPN Center 23.24 A 20.0 A 9 4
and Furnace 1 Edge 22.29 A 19.0 A 8 4
anneal Mean 22.80 A
3. RTO/RPN Center 26.25 A 23.0 A 8 3.5
and Furnace 2 Edge 25.50 A 23.0 A 7 3.4
anneal Mean 25.79 A
Where physical elliptical uniformity is defined as 100*(max-min)/(2*mean), where max and min are the maximum height and minimum height, respectively, of the cross sectional profile of the highly nitrided layer, the processes listed above yielded the following data. Process 1 yielded a physical elliptical uniformity of 2.85%. Process 2 yielded a physical elliptical uniformity of 2.08%. Process 3 yielded a physical elliptical uniformity of 1.42%.
The table also shows the improvement in concentration uniformity gained by the annealing process. Process 1, in which no anneal was performed, yielded a dose uniformity of 67% and a concentration uniformity of 77%. By contrast, process 2 yielded a dose uniformity of 89% and a concentration uniformity of 100%. Process 3 yielded a dose uniformity of 88% and a concentration uniformity of 97%.
The Furnace 1 process is a furnace annealing process for 13 minutes N2O 700 C (950C precombustion chamber temperature). The Furnace 2 process is a furnace annealing process at 26 minutes N2O 800 C (950C precombustion chamber temperature).
The foregoing description encompasses only the preferred embodiments of the present invention. The following claims and their equivalents define the scope of the invention.

Claims (6)

1. A gate dielectric for an integrated circuit device, comprising
a base silicon oxide layer;
a highly nitrided second layer, wherein said nitrided layer has a first percent elliptical uniformity and a first percent nitrogen concentration uniformity; and
an NO annealed layer, wherein said annealed layer has a second percent elliptical uniformity less than said first percent elliptical uniformity, and a second percent nitrogen concentration uniformity higher than said first percent nitrogen concentration uniformity.
2. A gate dielectric for an integrated circuit device, according to claim 1, wherein each of said nitrided and said annealed layers have a nitrogen concentration of about 4×1021 atoms/cm3.
3. A gate dielectric for an integrated circuit device, according to claim 1, wherein the thickness of said silicon oxide layer is from about 5 Å to about 20 Å; the thickness of said nitrided layer is from about 10 Å to about 30 Å; and the thickness of said annealed layer is from about 1 Å to about 30 Å.
4. A gate dielectric for an integrated circuit device, according to claim 1, wherein said annealed layer has a physical elliptical uniformity of less than 2.10%.
5. A gate dielectric for an integrated circuit device, according to claim 1, wherein said annealed layer has a concentration uniformity of at least 96%.
6. A gate dielectric for an integrated circuit device, according to claim 1, wherein said annealed layer has a concentration uniformity of at least 97%.
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US7638442B2 (en) * 2008-05-09 2009-12-29 Promos Technologies, Inc. Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer
US8394688B2 (en) 2011-06-27 2013-03-12 United Microelectronics Corp. Process for forming repair layer and MOS transistor having repair layer
US8741784B2 (en) 2011-09-20 2014-06-03 United Microelectronics Corp. Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device
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