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US7732316B2 - Method for manufacturing a semiconductor device - Google Patents
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US7732316B2 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device Download PDF

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US7732316B2
US7732316B2 US12/344,992 US34499208A US7732316B2 US 7732316 B2 US7732316 B2 US 7732316B2 US 34499208 A US34499208 A US 34499208A US 7732316 B2 US7732316 B2 US 7732316B2
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hemispherical
silicon elements
manufacturing
single crystal
layer
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US20100062594A1 (en
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Chi Hwan Jang
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth

Definitions

  • the invention relates to a method of manufacturing a semiconductor device.
  • a design rule of a semiconductor device has been rapidly reduced to less than a 100 nm class, correspondingly, the length and width of channel of a transistor is decreased. Additionally, the concentration of doping to a junction area is increased such that a junction leakage current according to an increment of electric field is increased.
  • Vt a desired threshold voltage
  • Various embodiments of the invention are directed to providing a manufacturing method of a semiconductor device.
  • a method of manufacturing a semiconductor device includes forming a layer having a plurality of hemispherical single crystal silicon elements over a semiconductor substrate; forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements; forming a gate insulating layer on a surface of the plurality of hemispherical single crystal silicon elements, the semiconductor substrate, and the carbon nano tubes; and forming a gate material layer over the gate insulating layer.
  • the layer having a plurality of hemispherical single crystal silicon elements is formed by forming a photoresist pattern, which exposes an active region, on an upper portion of the semiconductor substrate; forming a layer having a plurality of hemispherical polycrystalline silicon elements over the active region; transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements; and removing the photoresist pattern.
  • the layer having a plurality of hemispherical polycrystalline silicon elements is formed with a material selected from the group consisting of a metastable polysilicon layer and a hemispherical silicon crystalline layer, and combinations thereof.
  • transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements includes performing a thermal process.
  • the thermal process can be selected from the group consisting of a rapid thermal annealing process and a furnace annealing process.
  • the thermal process is performed in a temperature in a range of about 600° C. to about 1000° C.
  • the rapid thermal annealing process is performed for a time in a range of one to thirty minutes.
  • the furnace annealing process is performed for a time in a range of twenty minutes to two hours.
  • transforming the hemispherical polycrystalline silicon elements into hemispherical single crystal silicon elements is performed using plasma.
  • transforming the hemispherical polycrystalline silicon elements includes performing an ion injection process using an inert gas.
  • an acceleration energy of the ion injection process ranges from 1 KeV to 10 KeV.
  • the carbon nano tubes are formed using a surface energy difference of the hemispherical single crystal silicon elements.
  • the carbon nano tubes are formed in an atmosphere of a mixed gas of hydrogen and carbon.
  • a height of the carbon nano tubes ranges from 10 nm to 200 nm.
  • the gate insulating layer is formed by an atomic layer deposition method.
  • the gate insulating layer can be formed, for example, with a material selected from the group consisting of Al 2 O 3 , HfO 2 , ZrO 2 , SiON, La 2 O 3 , Y 2 O 3 , TiO 2 , CeO 2 , N 2 O 3 , Ta 2 O 5 , BaTiO 3 , SrTiO 3 , BST, PZT, and combinations thereof.
  • FIGS. 1 a to 1 j are a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the invention.
  • FIG. 2 is a cross-sectional view of the layer having a plurality of hemispherical single crystal silicon elements illustrated in FIG. 1 d.
  • FIGS. 1 a to 1 j are a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the invention.
  • an isolation film (not shown) which defines an active region on a semiconductor substrate 100 is formed. Then, a photoresist pattern 102 which exposes the active region over the semiconductor substrate 100 is formed.
  • the active region can include, for example, the region in which a gate is formed.
  • a layer having a plurality of hemispherical polycrystalline silicon elements 104 is formed over the portion of the semiconductor substrate 100 exposed by the photoresist pattern 102 .
  • the layer having the plurality of hemispherical polycrystalline silicon elements 104 is formed with a material selected from the group consisting a metastable polysilicon layer (MPS), a hemispherical silicon grain layer (HSG), and combinations thereof.
  • MPS metastable polysilicon layer
  • HSG hemispherical silicon grain layer
  • a gap between adjacent hemispherical polycrystalline silicon elements 104 can be controlled according to the length and number of linear directions of the polycrystalline silicon elements 104 .
  • FIG. 1 b of the invention exemplifies the case where the polycrystalline silicon elements 104 are separated by a gap.
  • adjacent hemispherical polycrystalline silicon elements 104 can also be in contact with each other.
  • the photoresist pattern 102 is removed. So that the hemispherical polycrystalline silicon elements 104 have the same architectural features as the semiconductor substrate 100 , the hemispherical polycrystalline silicon elements 104 are transformed into hemispherical single crystal silicon elements 104 a .
  • the semiconductor substrate 100 locally having an embossing structure can be used to increase the surface area of the active region.
  • a thermal process can be performed to transform the hemispherical polycrystalline silicon elements 104 into the hemispherical single crystal silicon elements 104 a .
  • the thermal process is a rapid thermal annealing (RTA) process or a furnace annealing process. It is preferable that the thermal process is performed in a temperature range of about 600° C. to about 1000° C.
  • the rapid thermal annealing process is performed for about one minute to about thirty minutes.
  • the rapid thermal annealing process can be performed, for example, using a halogen lamp.
  • the furnace annealing process is performed for about twenty minutes to about two hours.
  • the furnace annealing process can be performed, for example, using a tungsten coil. Energy can be supplied to the hemispherical single crystal silicon elements 104 a using plasma instead of the thermal process.
  • an ion injection process can be used to supply energy to the hemispherical single crystal silicon elements 104 a .
  • the energy supplied to the hemispherical polycrystalline silicon elements 104 through the ion injection process using, for example, an inert gas, can transform the hemispherical polycrystalline silicon elements 104 into the hemispherical single crystal silicon elements 104 a .
  • the acceleration energy in the ion injection process ranges from about 1 KeV to about 10 KeV.
  • one or more carbon nano tubes (CNTs) 106 are formed over the semiconductor substrate 100 , between adjacent hemispherical single crystal silicon elements 104 a .
  • the CNT 106 formation process is performed in a mixed gas atmosphere of hydrogen and carbon.
  • the height of the CNTs 106 ranges from about 10 nm to about 200 nm.
  • the number of CNTs formed can be controlled by the concentration of the hemispherical single crystal silicon elements 104 a.
  • the CNTs 106 can be formed using the surface energy difference resulting from the hemispherical shape of the hemispherical single crystal silicon elements 104 a .
  • the invention uses the hemispherical shape of the hemispherical single crystal silicon elements 104 a thereby, being able to omit an additional metal layer forming process, which can simplify the process.
  • the CNTs 106 are grown between adjacent hemispherical single crystal silicon elements 104 a .
  • the CNTs can be formed by other materials having a lower resistance than the hemispherical single crystal silicon elements 104 a.
  • a gate insulating layer 108 is formed over the semiconductor substrate 100 , the hemispherical single crystal silicon elements 104 a , and the CNTs 106 .
  • the gate insulating layer 108 is formed by an atomic layer deposition ALD method.
  • the gate insulating layer 108 can be formed, for example, with a high dielectric material having a high dielectric constant (high-k), such as, a material selected from the group consisting of Al 2 O 3 , HfO 2 , ZrO 2 , SiON, La 2 O 3 , Y 2 O 3 , TiO 2 , CeO 2 , N 2 O 3 , Ta 2 O 5 , BaTiO 3 , SrTiO 3 , (BST) and PbZrTiO (PZT).
  • high-k high dielectric constant
  • a gate electrode layer 110 is formed over the gate insulating layer 108 .
  • the gate electrode layer 110 is etched by a photolithographic etching process using a gate mask (not shown) to form a gate electrode layer pattern 110 a .
  • a material layer for spacer 112 is formed over the semiconductor substrate 100 including the gate electrode layer pattern 110 a.
  • the invention forms the semiconductor substrate 100 having an embossing structure by forming a layer having hemispherical single crystal silicon elements 104 a .
  • the CNTs 106 are grown between adjacent hemispherical single crystal silicon elements 104 a such that currents flow through the hemispherical single crystal silicon elements 104 a and the CNTs 106 during transistor operation.
  • the resistance of the CNTs 106 is lower than that of the hemispherical single crystal silicon elements 104 a . Therefore, a current does not flow toward the hemispherical single crystal silicon elements 104 a but flows in the CNTs 106 .
  • a three dimensional channel can be built up using the hemispherical single crystal silicon elements 104 a and the CNTs 106 in a planar structure, such that an effective channel length can be easily increased.
  • the CNTs 106 are formed by using the surface energy of the hemispherical single crystal silicon elements 104 a without a seed layer, such as a metal layer, thereby the process can be simplified. Moreover, the number and length of the hemispherical single crystal silicon elements 104 a and CNTs 106 can be controlled to increase a effective channel length, such that characteristics of the transistor can be improved.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATION
Priority to Korean patent application number 10-2008-0087844, filed on Sep. 5, 2008, the disclosure of which is incorporated herein by reference in its entirety, is claimed.
BACKGROUND OF THE INVENTION
The invention relates to a method of manufacturing a semiconductor device. Recently, as a design rule of a semiconductor device has been rapidly reduced to less than a 100 nm class, correspondingly, the length and width of channel of a transistor is decreased. Additionally, the concentration of doping to a junction area is increased such that a junction leakage current according to an increment of electric field is increased. Thus, in a transistor structure having a conventional planer channel structure, it is difficult to obtain a desired threshold voltage Vt in a highly integrated device, while reaching uppermost limit in improving a refresh characteristic. Accordingly, implementation of a semiconductor device having various forms of recess channels capable of securing an effective channel length of a transistor and the implementation of a semiconductor device having a three-dimensional channel structure capable of extending a channel width and practical process development researches are actively progressing. However, in the process of implementing the semiconductor device having three-dimensional structure channel, a fault frequently happens.
BRIEF SUMMARY OF THE INVENTION
Various embodiments of the invention are directed to providing a manufacturing method of a semiconductor device.
According to an embodiment of the invention, a method of manufacturing a semiconductor device includes forming a layer having a plurality of hemispherical single crystal silicon elements over a semiconductor substrate; forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements; forming a gate insulating layer on a surface of the plurality of hemispherical single crystal silicon elements, the semiconductor substrate, and the carbon nano tubes; and forming a gate material layer over the gate insulating layer.
Preferably, the layer having a plurality of hemispherical single crystal silicon elements is formed by forming a photoresist pattern, which exposes an active region, on an upper portion of the semiconductor substrate; forming a layer having a plurality of hemispherical polycrystalline silicon elements over the active region; transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements; and removing the photoresist pattern. In accordance with an embodiment of the invention, it is preferable that the layer having a plurality of hemispherical polycrystalline silicon elements is formed with a material selected from the group consisting of a metastable polysilicon layer and a hemispherical silicon crystalline layer, and combinations thereof.
Preferably, transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements includes performing a thermal process. The thermal process can be selected from the group consisting of a rapid thermal annealing process and a furnace annealing process. The thermal process is performed in a temperature in a range of about 600° C. to about 1000° C. The rapid thermal annealing process is performed for a time in a range of one to thirty minutes. The furnace annealing process is performed for a time in a range of twenty minutes to two hours.
Preferably, transforming the hemispherical polycrystalline silicon elements into hemispherical single crystal silicon elements is performed using plasma. Preferably, transforming the hemispherical polycrystalline silicon elements includes performing an ion injection process using an inert gas. Preferably, an acceleration energy of the ion injection process ranges from 1 KeV to 10 KeV.
Preferably, the carbon nano tubes are formed using a surface energy difference of the hemispherical single crystal silicon elements. Preferably, the carbon nano tubes are formed in an atmosphere of a mixed gas of hydrogen and carbon. Preferably, a height of the carbon nano tubes ranges from 10 nm to 200 nm. Preferably, the gate insulating layer is formed by an atomic layer deposition method. The gate insulating layer can be formed, for example, with a material selected from the group consisting of Al2O3, HfO2, ZrO2, SiON, La2O3, Y2O3, TiO2, CeO2, N2O3, Ta2O5, BaTiO3, SrTiO3, BST, PZT, and combinations thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 a to 1 j are a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the invention.
FIG. 2 is a cross-sectional view of the layer having a plurality of hemispherical single crystal silicon elements illustrated in FIG. 1 d.
DESCRIPTION OF EMBODIMENTS
Hereinafter, an embodiment of the invention will be illustrated in detail with reference to the attached drawings.
FIGS. 1 a to 1 j are a cross-sectional view showing a manufacturing method of a semiconductor device according to an embodiment of the invention.
Referring to FIG. 1 a, an isolation film (not shown) which defines an active region on a semiconductor substrate 100 is formed. Then, a photoresist pattern 102 which exposes the active region over the semiconductor substrate 100 is formed. The active region can include, for example, the region in which a gate is formed.
Referring to FIG. 1 b, a layer having a plurality of hemispherical polycrystalline silicon elements 104 is formed over the portion of the semiconductor substrate 100 exposed by the photoresist pattern 102. Preferably the layer having the plurality of hemispherical polycrystalline silicon elements 104 is formed with a material selected from the group consisting a metastable polysilicon layer (MPS), a hemispherical silicon grain layer (HSG), and combinations thereof. After depositing an amorphous silicon layer, if the MPS performs a Si atomic migration by using a thermal process, the amorphous silicon is visualized, and transformed into poly-crystalline silicon.
A gap between adjacent hemispherical polycrystalline silicon elements 104 can be controlled according to the length and number of linear directions of the polycrystalline silicon elements 104. FIG. 1 b of the invention exemplifies the case where the polycrystalline silicon elements 104 are separated by a gap. However, adjacent hemispherical polycrystalline silicon elements 104 can also be in contact with each other.
Referring to FIGS. 1 c and 1 d, the photoresist pattern 102 is removed. So that the hemispherical polycrystalline silicon elements 104 have the same architectural features as the semiconductor substrate 100, the hemispherical polycrystalline silicon elements 104 are transformed into hemispherical single crystal silicon elements 104 a. The semiconductor substrate 100 locally having an embossing structure can be used to increase the surface area of the active region.
A thermal process can be performed to transform the hemispherical polycrystalline silicon elements 104 into the hemispherical single crystal silicon elements 104 a. Preferably, the thermal process is a rapid thermal annealing (RTA) process or a furnace annealing process. It is preferable that the thermal process is performed in a temperature range of about 600° C. to about 1000° C.
Preferably, the rapid thermal annealing process is performed for about one minute to about thirty minutes. The rapid thermal annealing process can be performed, for example, using a halogen lamp. Preferably, the furnace annealing process is performed for about twenty minutes to about two hours. The furnace annealing process can be performed, for example, using a tungsten coil. Energy can be supplied to the hemispherical single crystal silicon elements 104 a using plasma instead of the thermal process.
Moreover, an ion injection process can be used to supply energy to the hemispherical single crystal silicon elements 104 a. The energy supplied to the hemispherical polycrystalline silicon elements 104 through the ion injection process, using, for example, an inert gas, can transform the hemispherical polycrystalline silicon elements 104 into the hemispherical single crystal silicon elements 104 a. Preferably, the acceleration energy in the ion injection process ranges from about 1 KeV to about 10 KeV.
Referring to FIG. 1 e, one or more carbon nano tubes (CNTs) 106 are formed over the semiconductor substrate 100, between adjacent hemispherical single crystal silicon elements 104 a. Preferably, the CNT 106 formation process is performed in a mixed gas atmosphere of hydrogen and carbon. Preferably, the height of the CNTs 106 ranges from about 10 nm to about 200 nm. The number of CNTs formed can be controlled by the concentration of the hemispherical single crystal silicon elements 104 a.
The CNTs 106 can be formed using the surface energy difference resulting from the hemispherical shape of the hemispherical single crystal silicon elements 104 a. Specifically, with reference to a cross-sectional view of the hemispherical single crystal silicon elements 104 a illustrated in FIG. 2, a portion in which unpaired electrons of a silicon (Si) does not unite with another silicon (Si) exists. That is, a site A is a portion that can unite with another atom and has relatively large surface energy in comparison with other sites.
A high surface energy exists between adjacent hemispherical single crystal silicon elements 104 a. Therefore, a carbon nano tube 106 can be grown up between adjacent hemispherical single crystal silicon elements 104 a, where there is relatively high surface energy.
Generally, whereas the CNTs 106 are conventionally formed with a metal layer as a seed layer, the invention uses the hemispherical shape of the hemispherical single crystal silicon elements 104 a thereby, being able to omit an additional metal layer forming process, which can simplify the process. In the embodiment of the invention, it is exemplified that the CNTs 106 are grown between adjacent hemispherical single crystal silicon elements 104 a. However, the CNTs can be formed by other materials having a lower resistance than the hemispherical single crystal silicon elements 104 a.
Referring to FIG. 1 f, a gate insulating layer 108 is formed over the semiconductor substrate 100, the hemispherical single crystal silicon elements 104 a, and the CNTs 106. Preferably, the gate insulating layer 108 is formed by an atomic layer deposition ALD method.
The gate insulating layer 108 can be formed, for example, with a high dielectric material having a high dielectric constant (high-k), such as, a material selected from the group consisting of Al2O3, HfO2, ZrO2, SiON, La2O3, Y2O3, TiO2, CeO2, N2O3, Ta2O5, BaTiO3, SrTiO3, (BST) and PbZrTiO (PZT).
Referring to FIGS. 1 g to 1 i, a gate electrode layer 110 is formed over the gate insulating layer 108. The gate electrode layer 110 is etched by a photolithographic etching process using a gate mask (not shown) to form a gate electrode layer pattern 110 a. A material layer for spacer 112 is formed over the semiconductor substrate 100 including the gate electrode layer pattern 110 a.
As shown in FIG. 1 j, the invention forms the semiconductor substrate 100 having an embossing structure by forming a layer having hemispherical single crystal silicon elements 104 a. The CNTs 106 are grown between adjacent hemispherical single crystal silicon elements 104 a such that currents flow through the hemispherical single crystal silicon elements 104 a and the CNTs 106 during transistor operation.
The resistance of the CNTs 106 is lower than that of the hemispherical single crystal silicon elements 104 a. Therefore, a current does not flow toward the hemispherical single crystal silicon elements 104 a but flows in the CNTs 106.
Therefore, instead of forming the transistor of three dimensional structure by etching the semiconductor substrate, a three dimensional channel can be built up using the hemispherical single crystal silicon elements 104 a and the CNTs 106 in a planar structure, such that an effective channel length can be easily increased.
Moreover, the CNTs 106 are formed by using the surface energy of the hemispherical single crystal silicon elements 104 a without a seed layer, such as a metal layer, thereby the process can be simplified. Moreover, the number and length of the hemispherical single crystal silicon elements 104 a and CNTs 106 can be controlled to increase a effective channel length, such that characteristics of the transistor can be improved.
It will be apparent to those skilled in the art that various modifications and variations can be made in the invention without departing from the spirit or scope of the invention. Thus, it is intended that the invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (16)

1. A manufacturing method of a semiconductor device, the method comprising:
forming a layer comprising a plurality of hemispherical single crystal silicon elements over a semiconductor substrate;
forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements;
forming a gate insulating layer over the hemispherical single crystal silicon elements, the semiconductor substrate, and the carbon nano tubes; and
forming a gate material layer over the gate insulating layer.
2. The manufacturing method of claim 1, wherein forming the layer comprising the plurality of hemispherical single crystal silicon elements comprises:
forming a photoresist pattern, which exposes an active region, over the semiconductor substrate;
forming a layer comprising a plurality of hemispherical polycrystalline silicon elements over the active region;
transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements; and
removing the photoresist pattern.
3. The manufacturing method of claim 2, wherein the layer comprising the plurality of hemispherical polycrystalline silicon elements is formed with a material selected from the group consisting of a metastable polysilicon layer, a hemispherical silicon crystalline layer, and combinations thereof.
4. The manufacturing method of claim 2, comprising transforming the layer comprising the plurality of hemispherical polycrystalline silicon elements by performing a thermal process.
5. The manufacturing method of claim 4, wherein the thermal process is selected from the group consisting of a rapid thermal annealing process and a furnace annealing process.
6. The manufacturing method of claim 5, comprising performing the rapid thermal annealing process for a time in range of about one to about thirty minutes.
7. The manufacturing method of claim 4, comprising performing the thermal process at a temperature in a range of about 600° C. to about 1000° C.
8. The manufacturing method of claim 5, comprising performing the furnace annealing process for at time in a range of about twenty minutes to about two hours.
9. The manufacturing method of claim 2, comprising transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements by exposing the hemispherical polycrystalline silicon elements to a plasma.
10. The manufacturing method of claim 2, comprising transforming the hemispherical polycrystalline silicon elements into the hemispherical single crystal silicon elements by performing an ion injection process using an inert gas on the hemispherical polycrystalline silicon elements.
11. The manufacturing method of claim 10, wherein an acceleration energy of the ion injection process ranges from about 1 KeV to about 10 KeV.
12. The manufacturing method of claim 1, wherein forming the one or more carbon nano tubes uses a surface energy difference resulting from the hemispherical shape of the hemispherical single crystal silicon elements.
13. The manufacturing method of claim 1, wherein forming the carbon nano tubes is performed in an atmosphere of a mixed gas of hydrogen and carbon.
14. The manufacturing method of claim 1, wherein a height of the carbon nano tubes ranges from about 10 nm to about 200 nm.
15. The manufacturing method of claim 1, wherein forming the gate insulating layer is performed by an atomic layer deposition method.
16. The manufacturing method of claim 1, wherein the gate insulating layer is formed with a material selected from the group consisting of Al2O3, HfO2, ZrO2, SiON, La2O3, Y2O3, TiO2, CeO2, N2O3, Ta2O5, BaTiO3, SrTiO3, (Ba,Sr)TiO3 (BST), PbZrTiO (PZT), and combinations thereof.
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