WO2019019550A1 - Adaptive LDPC code error correction code system and method applied to flash memory - Google Patents

Abstract

Disclosed in the present invention are a self-adaptive LDPC code error correction code system and method applied to a flash memory. The system and method can improve the error correction capability of the error correction code in the flash memory, ensure the stability of stored data, and prolong the service life of the flash memory. According to the method, the self-adaptive encoding and decoding of an LDPC code improves the adaptation of a flash memory controller, greatly enhances the error correction capability of the flash memory controller, and prolongs the service life of the flash memory.

Description

Adaptive LDPC code error correction code system and method applied to flash memory Technical field

The present application relates to an adaptive LDPC code error correction code system and method applied to a flash memory, and belongs to the field of flash memory storage control.

Background technique

In various applications that require signal transmission, an error correcting code is often used. The error correcting code can correct the error when the signal is transmitted incorrectly and obtain the correct signal. The error correcting code can be applied to many systems. In the communication system, the signal transmission may be interfered by channel effects and noise, thereby causing the data stored in the flash memory device to be incorrect. The data stored in the flash memory device is data encoded by the error correction code device, and the error correction code is a necessary functional unit for the flash memory control device. As the process of memory becomes more and more advanced, the memory unit is getting smaller and smaller, and the data stored in the memory unit is gradually increasing, causing the error probability of the flash memory to be generated during the reading process to rise, and thus the flash controller It is especially necessary to use a suitable and strong error correction code decoding mechanism.

In addition, the key to measuring the quality of a flash memory controller is its adaptability, which can support flash memory from multiple vendors and different processes. Especially when the process of flash memory is more advanced, the volume is smaller, and the data stored in the flash memory cell is also increased, the probability of error caused by the flash memory during reading is also increasing. However, the error correction code decoding capability of the flash memory controller is an important factor in determining whether the flash memory controller is qualified. Therefore, it is inevitable that the flash memory controller has an adaptable error correction code.

LDPC (Low Density Parity Check) code is a packet error correction code with a sparse check matrix proposed by Robert Gallager in his doctoral thesis in 1962. It is suitable for all channels, its performance is close to Shannon limit, and its description and implementation are simple, the decoding is simple and parallel operation is possible, suitable for hardware implementation. LDPC codes have great application potential and are widely used in deep space communications, fiber optic communications, satellite communications, satellite digital video, digital watermarking, magnetic/optical/holographic storage, mobile and fixed wireless communications, cable modulation/demodulation and digital users. application. According to the increasingly advanced process of the flash memory device, the error correction capability of the error correction code in the flash memory control device also needs to be enhanced. In the current flash memory control device, the main error correction code is the BCH code. As the error probability increases, the space requirement and computing power of the BCH code are gradually increased. With the improvement of the flash memory storage process, the BCH code is corrected. The ability has gradually become unsuitable for the development of flash memory technology and its application, so it needs an error correction code with stronger error correction capability, more flexibility and adaptability. Therefore, it is more appropriate to select the LDPC code instead of the BCH code.

Technical solutions

The technical problem to be solved by the present application is to provide an adaptive LDPC code error correction code system and method for use in a flash memory, to improve the error correction capability of the error correction code of the flash memory, and to protect the stability of the stored data.

In order to solve the technical problem, the technical solution adopted by the present application is: an adaptive LDPC code error correction code system applied to a flash memory, including a host, a flash memory controller, and a flash memory, and a flash memory controller Adaptive LDPC code decoder, multi-level encoder, adaptive regulator, hard decision decoder, soft decision decoder, error detector, decider I, decider II, data processing And a pulse recovery device, the multi-level encoder is connected between the host and the flash memory, and the input of the multi-level encoder is connected with the adaptive regulator for corresponding encoding according to the adaptive regulator; the hard decision decoder The input end of the soft decision decoder is connected to the adaptive regulator and the decider I, and the input of the soft decision decoder is connected to the data processor, and the other end of the decider I and the data processor are connected to the flash memory, and the hard decision is made. The decoder judges whether to perform hard decision decoding according to the decider I, and judges the check matrix for decoding according to the adaptive adjuster, and the soft decision decoder According to the judger I, it is judged whether or not the soft decision decoding is performed, and the parity bit information outputted by the data processor is used for calculation to perform decoding, and the check matrix for decoding is determined according to the adaptive regulator; the hard decision decoder and the soft decision decoder The output is connected to the determiner II, the output of the determiner II is connected to the adaptive regulator, the host and the error detector respectively, the error detector is connected to the flash memory through the pulse recovery device, and the determiner II is used to judge the LDPC If the code is successfully connected and the number of data errors is wrong, the error detector judges the decoding failure according to the decider II, and uses the pulse recovery device to recover the data error in the flash memory.

The adaptive LDPC code error correction code system is applied to a flash memory, and the soft decision decoder includes a primary decoder, a secondary decoder, and a tertiary decoder.

The adaptive LDPC code error correction code system applied to the flash memory is applied in the present application, and the error correction capability of the hard decision decoder, the first stage decoder, the second level decoder, and the third stage decoder is sequentially enhanced.

The adaptive LDPC code error correction code system applied to the flash memory is applied to the flash memory. Based on the standard data bits and the parity bits, a portion of the data bits are used as check bits.

The adaptive LDPC code error correction code system applied to the flash memory is applied in the present application. The multi-level encoder adopts the Gallager construction method, the generalized LDPC code construction method, the Mackay construction method, the combinatorial construction method, and the finite geometry structure. Method implementation; hard decision decoder and soft decision decoder adopt bit flip method, sum product decoding algorithm, minimum sum product decoding algorithm, maximum likelihood decoding algorithm, decoding architecture implemented by hardware circuit, implemented by software or hardware matching processor The way of decoding is implemented.

The present application also discloses an adaptive LDPC error correction code method applied to a flash memory, the method comprising an adaptive coding process and an adaptive decoding process, the process of the adaptive coding process is: a01), according to error detection The detector selects the corresponding encoder; a02), encodes the codeword information correspondingly; a03), stores the encoded data and the check code into the flash memory; the process of the adaptive decoding process is: b01), Read the codeword information from the flash memory; b02), perform decoding judgment, if it meets the hard decision decoding execution step 3, if it meets the soft decision decoding execution step 7; b03), read the hard information of the codeword; b04), utilize Corresponding LDPC code hard decision decoding; b05), perform decoding judgment, if successful, end decoding, if not successful, enter the next decision; b06), if not continue decoding, end decoding, if continue decoding, execute step 7; b07) Read the soft information of the codeword and perform corresponding data processing; b08), use the corresponding LDPC code soft decision decoding; b09), decode the judgment, if the decoding succeeds, the decoding ends, if not Successfully enters the next decision; b10), if not continue decoding, the decoding is terminated, if the decoding continues, the error detector is started to determine the decoding error; b11), the internal data of the flash memory is pulse-recovered according to the error detector; b12 ), repeat steps 7 and 8; b13), the iteration reaches a certain number of times, and when the LDPC code decoding is unsuccessful, the decoding process is directly ended.

Advantageous Effects of the Invention: The adaptive LDPC code error correction code system and method applied to a flash memory according to the present application can improve the error correction capability of the error correction code of the flash memory, protect the stability of the stored data, and improve the flash memory. Service life. The method changes the LDPC code into adaptive encoding and decoding, improves the adaptability of the flash memory controller, greatly enhances the error correction capability of the flash memory controller, and improves the service life of the flash memory.

DRAWINGS

Figure 1 is a functional block diagram of a flash memory storage system;

2 is a schematic structural diagram of an adaptive LDPC code decoder;

3 is an overall block diagram of a multi-level encoder and a hard decision decoder, and a soft decision decoder;

Figure 4 is a comparison chart of the standard and adjusted flash village summer data storage;

FIG. 5 is a flowchart of adaptive LDPC code decoding according to the present application.

Detailed ways

The present application will be further described below in conjunction with the accompanying drawings and specific embodiments.

Example 1

The LDPC code is a type of linear block code which has all the characteristics of a linear block code. LDPC codes can be classified into two types: regular (regular-LDPC) and irregular (regular-LDPC). Assuming that the check matrix H ₀ is an m×n-order matrix, the regular LDPC code can be written as (n, j, k), where n is the code length and j is the weight of each column of the check matrix (ie, the number of 1 in the column) , referred to as column weight, k is the weight of each row of the check matrix (ie, the number of 1 in the row, referred to as the row weight), and generally has j>2, k>j. Instead of regular LDPC The parity check matrix of a code is not exactly the same number of ones per row and column. The iterative decoding method of LDPC codes can be roughly divided into two types: one is a hard decision method, and the other is a soft decision method. The bit flip method delivers binary hard information in the iterative process, while the soft decision method passes the real soft information related to probability in the iterative process. The hard decision method is simple to operate and easy to implement in hardware, but the error correction performance is general; The decision method has better performance, but the implementation complexity is higher. This embodiment proposes an adaptive LDPC code error correction code system applied to the flash memory.

As shown in FIG. 1 , which is a functional block diagram of a flash memory storage system, an adaptive LDPC code decoder is included in the flash memory controller. The flash memory controller is primarily responsible for data read and write and data storage and other functions. The flash memory controller obtains data from the host through an adaptive LDPC code decoder for encoding operations, and then stores the generated data into the flash memory. If the host wants to obtain data in the flash memory, it needs a flash memory controller to read it from the flash memory and decode it through an adaptive LDPC code decoder to generate data input to the host.

As shown in FIG. 2, which is a schematic structural diagram of an adaptive LDPC code decoder, the adaptive LDPC code decoder includes a multi-level encoder, an adaptive regulator, a hard decision decoder, a soft decision decoder, an error detector, and a decision. I, the determiner II, the data processor and the pulse recovery device, the multi-level encoder is connected between the host and the flash memory, and the input of the multi-level encoder is connected to the adaptive regulator for adapting the adaptive regulator Corresponding coding is performed; the input ends of the hard decision decoder and the soft decision decoder are connected to the adaptive regulator and the decider I, and the input of the soft decision decoder is connected to the data processor, the decider I, the data processor The other end is connected to the flash memory, and the hard decision decoder judges whether to perform hard decision decoding according to the decider I, and judges the check matrix for decoding according to the adaptive adjuster, and the soft decision decoder determines whether to perform the soft decision according to the decider I. Decoding, performing decoding by acquiring parity bit information outputted by the data processor, and determining the decoding moment for decoding according to the adaptive regulator The output of the hard decision decoder and the soft decision decoder are connected to the determiner II, the output of the determiner II is respectively connected to the adaptive regulator, the host and the error detector, and the error detector is connected by the pulse recovery device. To the flash memory, the determiner II is used to determine whether the LDPC code is successfully connected and the number of data errors. The error detector determines the decoding failure according to the decider II, and uses the pulse recovery device to recover the data error in the flash memory.

The role of each part is that the multi-level encoder is coded according to the adaptive regulator. The hard decision decoder determines whether to perform hard decision decoding according to the decider 1, and judges the application of the check matrix for decoding according to the adaptive adjuster. The soft decision decoder determines whether to perform soft decision decoding according to the decider I, obtains corresponding information of the check bit output by the data processor, performs corresponding operation to decode, and determines the application according to the adaptive regulator. The matrix is checked for decoding. The adaptive regulator makes corresponding adjustments according to the decider II, thereby performing higher level encoding and decoding to make the stored data reliable. The data processor is used to process the corresponding data processing after the data stored in the flash memory is quantized, which improves the data processing speed, thereby improving the decoding time, reducing the decoding delay, and improving the decoding performance of the LDPC code. The error detector mainly judges the decoding failure according to the determiner II, and uses the pulse recovery device to recover the data error in the flash memory. The pulse recovery device injects electrons into the corresponding gates according to the error detector to increase and recover data errors. The determiner I is mainly to determine what method to use for decoding. The determiner II is used to judge whether the LDPC code is decoded successfully and the number of bits of the data error.

As shown in FIG. 3, it is a schematic structural diagram of a multi-level encoder and a hard decision decoder and a soft decision decoder. The soft decision decoder includes a primary decoder, a secondary decoder, and a tertiary decoder. The multi-level LDPC code is mainly used to adapt the error correction bits of different LDPC codes. Flash memory With the increasing number of erases and writes, the probability of error in flash memory storage data will gradually increase; therefore, multi-level LDPC codes are needed to adapt to changes in flash memory. The LDPC code multi-level encoder in FIG. 3 mainly performs corresponding encoding processing according to the probability of data error in the flash memory, and corresponds to each level decoder of the LDPC code. In Figure 3, the LDPC code hard decision decoder is fast and has limited error correction capability. It can only correct a certain amount of error bits, and it performs corresponding hard decision decoding according to different levels of coding. In Figure 3, LDPC code soft decision decoding is divided into three levels, each level of error correction capability is different, the error correction capability of the primary decoder is greater than the hard decision decoding, and the secondary decoder is better than the primary decoder. The stage decoder is superior to the second stage decoder. The multi-level LDPC code design increases the useful life of the flash memory and enhances the adaptability of the flash controller.

As shown in FIG. 4, this is a comparison of the flash memory data storage of the patent. In Figure 4, the standard is a standard diagram of data stored in a flash memory whose data bits and check bits are set according to different processes of the flash memory. The adjustment is based on the multi-level LDPC code to increase the error correction capability and increase the corresponding parity bit to make the flash memory more reliable and longer. It is worthwhile to sacrifice a portion of the storage space for flash memory to increase reliability and lifetime.

In this embodiment, the LDPC code multi-level encoder can be implemented by using various algorithms and software and hardware architecture coding devices. For example, the LDPC code encoder can adopt the Gallager construction method, the generalized LDPC code construction method, the Mackay construction method, It is realized by combination of construction method and finite geometry construction method.

The LDPC code decoder can be implemented by using various algorithms and software and hardware architecture decoding devices. For example, the LDPC code decoder can adopt a bit flip method, a sum product decoding algorithm, a minimum sum product decoding algorithm, a maximum likelihood decoding algorithm, and a hardware circuit. The implemented decoding architecture is implemented by software or hardware with a processor to implement decoding.

Example 2

In this embodiment, an adaptive LDPC code error correction code method applied in a flash memory is proposed. The adaptive LDPC code error correction code adaptively adjusts the number of error correction bits according to the error probability of the flash memory to store data and different processes. The adaptive LDPC code error correcting code of the method can automatically expand the number of error correcting bits to improve the reliability of the data and the service life of the flash memory. The adaptability of the method is mainly embodied in the multi-level encoder and the multi-stage decoder of the LDPC code, which automatically adjusts the number of error correction bits according to the detecting error device, thereby adjusting the encoding mode and the decoding method thereof. The specific scheme of this scheme is divided into an encoding process and a decoding process. The specific process is as follows.

Adaptive LDPC code encoding process:

(1) Select the corresponding encoder according to the error detector;

(2) correspondingly coding the codeword information;

(3) The encoded data and the check code are stored in the flash memory.

The adaptive LDPC code decoding process is shown in Figure 5, specifically:

(1) reading codeword information from the flash memory;

(2) performing decoding judgment, if it conforms to hard decision decoding execution (3), if it conforms to soft decision decoding execution (7);

(3) reading the hard information of the codeword;

(4) Hard decision decoding using the corresponding LDPC code;

(5) Perform decoding judgment, if the decoding is successfully ended, if the decision is not successful, the next step is entered;

(6) If you do not want to continue decoding to end the decoding, if you want to continue decoding, go to (7);

(7) reading the soft information of the codeword and performing corresponding data processing;

(8) using the corresponding LDPC code soft decision decoding;

(9) Decoding judgment, if the decoding successfully ends the decoding, if the decision is not successful, the next step is entered;

(10) If the decoding is not continued, the error detector is started if the decoding is continued;

(11) performing pulse recovery on the internal data of the flash memory according to the error detector;

(12) repeating the processes of (7) and (8);

(13) If a certain number of iterations is reached, the LDPC code decoding is unsuccessful, and the decoding process is directly ended.

The present application is mainly directed to improving the error correction capability of the error correction code of the flash memory, protecting the stability of the stored data, and improving the lifetime of the flash memory. Changing the LDPC code into adaptive encoding and decoding improves the adaptability of the flash memory controller, and greatly enhances the error correction capability of the flash memory controller while improving the memory life of the flash memory.

The above description is only the basic principles and preferred embodiments of the present application, and the improvements and substitutions made by those skilled in the art according to the present application fall within the protection scope of the present application.

Claims (6)

An adaptive LDPC code error correction code system for use in a flash memory, comprising a host, a flash memory controller and a flash memory, characterized in that: an adaptive LDPC code decoder is provided in the flash memory controller, and the adaptive LDPC The code decoder includes a multi-level encoder, an adaptive regulator, a hard decision decoder, a soft decision decoder, an error detector, a decider I, a decider II, a data processor, and a pulse recovery device, and a multi-level encoder connection. Between the host and the flash memory, the input of the multi-level encoder is connected to the adaptive regulator for corresponding encoding according to the adaptive regulator; the input of the hard decision decoder and the soft decision decoder are both The adaptive regulator and the decider I are connected, and the input end of the soft decision decoder is connected to the data processor, the other end of the decider I and the data processor are connected to the flash memory, and the hard decision decoder determines whether to perform the hard decision according to the decider I. Decoding, and judging the parity check matrix for decoding according to the adaptive regulator, and the soft decision decoder determines whether to perform soft decision decoding according to the decider I. The decoding is performed by acquiring the parity bit information outputted by the data processor, and the parity check matrix is determined according to the adaptive regulator; the outputs of the hard decision decoder and the soft decision decoder are connected to the determiner II, and the decision is made. The output of the device II is connected to the adaptive regulator, the host and the error detector respectively, and the error detector is connected to the flash memory through the pulse recovery device, and the determiner II is used to determine whether the LDPC code is successfully connected and the number of data errors is incorrect. The error detector judges the decoding failure according to the determiner II, and uses the pulse recovery device to recover data errors in the flash memory. The adaptive LDPC code error correction code system for use in a flash memory according to claim 1, wherein the soft decision decoder comprises a primary decoder, a secondary decoder and a tertiary decoder. The adaptive LDPC code error correction code system for use in a flash memory according to claim 2, wherein the error correction capability of the hard decision decoder, the first stage decoder, the second stage decoder, and the third stage decoder Enhance in turn. The adaptive LDPC code error correction code system for use in a flash memory according to claim 1, wherein the flash memory uses a portion of the data bits as a parity bit on the basis of standard data bits and parity bits. . The adaptive LDPC error correction code system applied to a flash memory according to claim 1, wherein the multi-level encoder adopts a Gallager construction method, a generalized LDPC code construction method, a Mackay construction method, and a combination. Learning construction method, finite geometry construction method implementation; hard decision decoder and soft decision decoder adopt bit flip method, sum product decoding algorithm, minimum sum product decoding algorithm, maximum likelihood decoding algorithm, decoding architecture implemented by hardware circuit, Software or hardware is implemented in a way that the processor implements decoding. An adaptive LDPC code error correction code method applied to a flash memory, comprising: an adaptive coding process and an adaptive decoding process, wherein the process of the adaptive coding process is: a01), according to an error detector Selecting the corresponding encoder; a02), correspondingly encoding the codeword information; a03), storing the encoded data and the check code into the flash memory; the process of the adaptive decoding process is: b01), from the flash memory Reading the codeword information; b02), performing decoding judgment, if the hard decision decoding is performed, step 3 is performed, if the soft decision decoding is performed, step 7; b03), reading the hard information of the codeword; b04), using the corresponding LDPC Code hard decision decoding; b05), perform decoding judgment, if successful, end decoding, if not successfully enter the next decision; b06), if not continue decoding, end decoding, if continue decoding, execute step 7; b07), read The soft information of the codeword, and the corresponding data processing; b08), using the corresponding LDPC code soft decision decoding; b09), decoding judgment, if the decoding is successful, the decoding ends, if not successfully entered Next decision; b10), if not continue decoding, the decoding is terminated, if the decoding continues, the error detector is started to determine the decoding error; b11), the internal data of the flash memory is pulse-recovered according to the error detector; b12), Repeat steps 7 and 8; b13). When the iteration reaches a certain number of times and the LDPC code decoding is unsuccessful, the decoding process is directly ended.

Images