WO2024212202A1

WO2024212202A1 - System and method of a micro-led pixel driving circuit

Info

Publication number: WO2024212202A1
Application number: PCT/CN2023/088269
Authority: WO
Inventors: Hongyun Liu
Original assignee: Jade Bird Display Shanghai Ltd
Current assignee: Jade Bird Display Shanghai Ltd
Priority date: 2023-04-14
Filing date: 2023-04-14
Publication date: 2024-10-17
Anticipated expiration: 2025-10-14
Also published as: TW202443543A; CN120937069A

Abstract

A micro-light emitting diode (LED) pixel driving circuit comprises a logic operation module(A1) and a pixel driving module(A2). The logic operation module(A1) receives an N-bit image data signal(D), and N is a positive integer. The logic operation module(A1) comprises a conversion unit(A1-1), an AND logic unit(A1-2) connected to the conversion unit(A1-1), and a NOR logic unit(A1-3) connected to the AND logic unit(A1-2). The conversion unit(A1-1) is configured to convert the N-bit image data signal(D) of a first format into a second format upon a trigger signal. The AND logic unit(A1-2) is configured to convert the N-bit image data signal(D) of the second format and a time sequence control signal(SF) into a third format. The NOR logic unit(A1-3) is configured to convert the N-bit image data signal(D) of the third format into a fourth format to control the switching state of the pixel driving module(A2).

Description

SYSTEM AND METHOD OF A MICRO-LED PIXEL DRIVING CIRCUIT

TECHNICAL FIELD

The present disclosure relates generally to the technical field of displays, in particular to a micro light-emitting diode (LED) pixel driving circuit and system, and a process of driving the micro-LED pixel driving system.

BACKGROUND

Display technologies are becoming increasingly important in today's commercial electronic devices. These display panels are widely used in stationary large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode televisions (OLED TVs) as well as portable electronic devices such as laptop personal computers, smartphones, tablets and wearable electronic devices.

A Light-Emitting Diode (LED) chip generally includes an Organic Light-

Emitting Diode (OLED) chip, a Mini Light-Emitting Diode (Sub-millimeter Light-Emitting Diode) chip or a micro-LED (Micro Meter Light-Emitting Diode) chip and the like. LED is widely applied in the field of illumination. As the LED display screen gradually permeates towards the high-end market, the light emitting efficiency requirement of the LED display screen device is higher.

Pixels are composed of small squares of an image, and the small squares have a clear position and are assigned color values, and the color and position of the small squares determine the appearance of the image. The pixels may be viewed as inseparable units or elements throughout the image. Inseparable means that a pixel cannot be further cut into smaller units or elements, which are present in a single-color cell. Each dot matrix image contains a quantity of pixels that determine the size of the image presented on the screen.

Micro-LED display technology relates to micron-scale LED pixel units, which are assembled to a driving panel to form a high-density LED display array. Micro-LED display technology herein can also be referred to as μ-LED display technology. Since the micro-LED chip has attributes such as small in size, high in integration level, self-luminous, etc., the micro-LED chip has greater advantages in terms of brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like compared with an LCD and an OLED. In some approaches, the early LED display screen pixels are formed by combining LEDs with three primary colors of red, green and blue.

In some approaches, many switch transistors are included in the driving circuit of the micro-LED device to drive at least one single pixel, and the switch transistors are high-voltage transistors, which are referred to as Input/Output (I/O) transistors. The high-voltage transistors occupy most of the pixel area, which directly leads to a limited data buffer capacity of a single pixel, and a complex driving control. Therefore, a new driving circuit structure is needed, so that the data buffer capacity of a single pixel can be improved, and the control can be simplified.

As such, it would be desirable to provide a light emitting pixel driving circuit for display panels that addresses the above-mentioned drawbacks, amongst others.

SUMMARY

There is a need for improved display device designs that improve upon, and help to address the issues and shortcomings of the display systems, such as those described above. In particular, there is a need for a micro-LED pixel driving system with improved images and data buffer capacity.

The present disclosure relates to the technical field of displays, and discloses a Light-Emitting Diode (LED) pixel driving circuit and system, and a method of driving the micro-LED pixel system. In some embodiments, the present disclosure relates to a digital micro-LED pixel driving system. The technical drawbacks of limited data buffer capacity from a pixel light-emitting unit at present is solved.

The present disclosure includes, without limitation, the following exemplary embodiments.

Some exemplary embodiments of the present disclosure provide a micro light-emitting driving circuit, comprising: a logic operation module; and a pixel driving module electrically connected to the logic operation module. In some examples, the logic operation module receives an N-bit image data signal from an input end of the logic operation module, N is a positive integer, and the logic operation module comprises: a conversion unit; an AND logic unit connected to the conversion unit; and a NOR logic unit connected to the AND logic unit. In some examples, the conversion unit is configured to convert the N-bit image data signal of a first format into a second format; the AND logic unit is configured to convert the N-bit image data signal of the second format into a third format; and the NOR logic unit is configured to convert the N-bit image data signal of the third format into a fourth format.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the pixel driving module comprises a current source, a switch transistor and a micro-LED pixel. In some examples, the current source is electrically connected to a first terminal of the switch transistor, a gate of the switch transistor is electrically connected to an output end of the logic operation module, a second terminal of the switch transistor is electrically connected to a first electrode of the micro-LED pixel, and a second electrode of the micro-LED pixel is grounded.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the conversion unit is configured to convert the N-bit image data signal of the first format into the second format upon receiving a trigger signal, the N-bit image data signal of the second format is operable by a logic operator, and the conversion unit is an N-bit static random-access memory (SRAM) cell latch.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the AND logic unit is configured receive a time sequence control signal and the N-bit image data signal of the second format from the conversion unit and output the N-bit image data signal of the third format.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the conversion unit includes N parallel sub-conversion units, and each of the sub-conversion units is configured to convert one bit of the N-bit image data signal of the first format into the second format upon receiving a trigger signal.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the AND logic unit includes N parallel sub-AND logic units, and each of the sub-AND logic units is configured to receive a respective time sequence control signal for a respective bit of the N-bit image data signal of the second format from a respective sub-conversion unit of the conversion unit and output the respective bit of the N-bit image data signal of the third format.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the NOR logic unit is configured to receive the N-bit image data signal from the N parallel sub-AND logic units and output the N-bit image data signal of the fourth format.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the logic operation module is configured to output the N-bit image data signal of the fourth format to the gate of the switch transistor to control a switching state of the switch transistor.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, a time sequence control signal and the N-bit image data signal of the second format are both at a first level, the switch transistor is turned on, wherein the first level is a high level or a low level.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, N=2^k, wherein K is a non-negative integer.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the switch transistor is a high-voltage transistor, and the number of switch transistor is 1 for a single micro-LED pixel.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, the N-bit SRAM cell latch includes N 1-bit SRAM cell latches.

In some exemplary embodiments or any combination of exemplary embodiments of micro light-emitting driving circuit, each of the N 1-bit SRAM cell latches stores one bit of the N-bit image data signal.

Some exemplary embodiments of the present disclosure provide a micro light-emitting driving method, comprising: providing an N-bit image data signal to an input end a logic operation module, wherein N is a positive integer; converting the N-bit image data signal of a first format into a second format by a conversion unit of the logic operation module; converting the N-bit image data signal of the second format into a third format by an AND logic unit of the logic operation module; converting the N-bit image data signal of the third format into a fourth format by an NOR logic unit of the logic operation module; and connecting a pixel driving module to an output end of the logic operation module.

Some exemplary embodiments of the present disclosure provide a micro light-emitting display system, comprising: one or more micro-light-emitting-diode (micro-LED) pixels; a time sequence control circuit module; and a data buffer conversion module. In some examples, the data buffer conversion module comprises: a logic operation module; and a pixel driving module electrically connected to the logic operation module. In some examples, the logic operation module receives an N-bit image data signal from an input end of the logic operation module, N is a positive integer, and the logic operation module comprises: a conversion unit; an AND logic unit connected to the conversion unit; and a NOR logic unit connected to the AND logic unit. In some examples, the conversion unit is configured to convert the N-bit image data signal of a first format into a second format; the AND logic unit is configured to convert the N-bit image data signal of the second format into a third format; and the NOR logic unit is configured to convert the N-bit image data signal of the third format into a fourth format.

In order to solve the technical drawback that a pixel driving circuit occupies too much pixel area which directly causes the data buffer capacity of a single pixel to be low, the present disclosure herein introduces the I/O transistor of only one high-voltage transistor, and the other devices adopting the Core transistor, so that the data buffer capacity of a single pixel is improved, and the control simplification is achieved.

In some embodiments, in order to achieve the above objectives, the present disclosure provides the following aspects.

In some aspects, the micro-LED pixel driving circuit comprises a logic operation module and a pixel driving module, wherein the logic operation module and the pixel driving module are electrically connected.

In some examples, the logic operation module receives an N-bit image data signal D, a time sequence control signal SF for image time sequence control and a word line (WL) signal for converting the N-bit image data signal D into a data signal DL operable by a logic operator, and the logic operation module outputs an N-bit Y signal.

In some examples, the pixel driving module comprises a current source, a switch transistor and a micro-LED pixel, wherein the current source is connected to the source electrode of the switch transistor, the gate of the switch transistor is connected to the output end of the logic operation module and receives the Y signal, the drain electrode of the switch transistor is connected to the positive electrode of the micro-LED pixel, and the negative electrode of the micro-LED pixel is grounded.

According to the above embodiments, the pixel driving circuit with two or more I/O transistors is eliminated. Instead, an I/O transistor with only one high-voltage transistor is included in the pixel driving circuit for a single pixel, and the Core transistor is adopted in the other devices. In these embodiments, the logic operation module is included, the pixel driving circuit can also achieve the objectives of micro-LED pixel driving, and the pixel area occupied by the driving circuit is small, so that the data buffer capacity of a single pixel is improved, and the control simplification is achieved.

In some examples, the logic operation module comprises a conversion unit, an AND logic unit and a NOR logic unit. The input end of the conversion unit receives the image N bit data signal D and the WL signal used for converting the image N bit data signal D into a data signal DL which can be operated by the logic operator, and the output end of the conversion unit outputs a data signal DL which can be operated by the logic operator. The input end of the AND logic unit receives the DL signal and the SF signal and the AND logic unit outputs an operation result Y signal after performing AND logic operation on the two signals. The plurality of Y< N-1: 0 > signals are input into the NOR logic unit and the NOR logic unit carries out the NOR operation and transmits the NOR operation result to the gate of the switch transistor to control the switching state of the switch transistor. Herein, Y< N-1: 0 >means the number of Y signals is N including Y (0) , Y (1) , Y (2) , and Y (N-1) , wherein N is a positive integer.

According to the above embodiments, the logic operation module is included in the pixel driving circuit for a single pixel. When the time sequence control signal SF and the data signal DL are both at a high level, the switch transistor is turned on.

In some examples, the conversion unit is configured as an N-bit static random-access memory (SRAM) cell latch.

In some examples, the number of the AND logic units is N, the NOR logic unit may be a module for receiving N input, and the number of the switch transistors is 1.

In some examples, the N bit may be 1 bit, 4 bits, 8 bits, 16 bits or 2^k bits, wherein K is a non-negative integer.

In some examples, the switch transistor is a high-voltage transistor.

In some aspects, the novel micro-LED pixel driving system comprises a display matrix, a time sequence control system and a cache system, wherein the cache system is in data connection with the display matrix, the time sequence control system is in control connection with the display matrix, and the time sequence control system is used for controlling the cache system to transmit data to the display matrix.

According to the above embodiments, the pixel driving system of the pixel driving circuit is provided.

In some aspects, a micro-LED pixel driving method comprises the following steps:

Step 1: A latch receives a source image data signal D and converts the signal D to a signal DL under the trigger of a WL signal. Before the logic operation of the signal DL is completed, the signal D is stored in the latch and the latch locks the signal format conversion. Under the trigger of the next signal WL, the signal D is converted into the signal DL.The conversion of the following signal D follows the same pattern. For example, when data signal D is sent to the latch, the latch keeps the data signal D and the data signal D is not converted into DL until WL becomes a high state. When WL becomes the high state, the state of the data signal D is converted into the state of the signal DL.

Step 2: A time sequence control signal SF of N bits and a signal DL of N bits are synchronously operated on a plurality of AND logic operation branches respectively, and an output operation result is Y< N-1: 0 >. In some examples, the number of the plurality of AND logic operation branches is N.

Step 3: The result Y< N-1: 0 > of the synchronous operation from the plurality of AND logic operation branches is jointly operated on a NOR logic unit, and a VPX signal is an output from the NOR logic unit.

Step 4: The VPX signal is provided to the gate of the switch transistor in the pixel driving module, so as to control the switch, the brightness and the grayscale of a micro-LED pixel.

According to the above embodiments, the driving method of the pixel driving system based on the implementations of the logic operators is provided.

In some examples, the number of the NOR logic units is one or more.

According to the disclosure herein, the pixel driving circuit with more I/O transistors is eliminated, the I/O transistor with only one high-voltage transistor is designed, and the Core transistor is adopted in the other devices. In some embodiments, the logic operation module is implemented. The pixel driving circuit simplifies the control of the micro-LED pixel driving. The pixel area occupied by the driving circuit is small, so that the data buffer capacity of a single pixel is improved.

Note that the various embodiments described above may be combined with any other embodiments described herein. The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the present disclosure may be understood in greater detail, a more particular description may be had by reference to the features of various embodiments, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features.

For convenience, "up" is used to mean away from the substrate or circuit board/plate of a light emitting structure, "down" means toward the substrate, and other directional terms such as top, bottom, above, below, under, beneath, etc. are interpreted accordingly.

FIG. 1 illustrates a schematic diagram showing an exemplary external layout of a micro-LED display driving system.

FIG. 2 illustrates a circuit structure diagram of an exemplary micro-LED pixel driving system.

FIG. 3 illustrates a circuit structure diagram of an exemplary micro-LED pixel driving system.

FIG. 4 illustrates a schematic diagram of an exemplary micro-LED pixel driving circuit.

FIG. 5 illustrates a schematic diagram of an exemplary structure of a micro-LED pixel driving circuit.

FIG. 6 illustrates a structural diagram of an exemplary micro-LED pixel circuit driving 4-bit of image data.

The FIGS. include the following identifications of components: 01, display matrix; 02, time sequence control system; 03, frame buffer system; 1, micro-LED pixel unit; 2, time sequence control circuit module; 2-1, time sequence control unit; 2-2, subframe control unit; 3, data buffer conversion module; 3-1, bit conversion unit; 3-2, external data input port; 3-3, memory; 4, reference current module; 4-1, current source; 4-2, current mirror; A1, logic operation module; A1-1, conversion unit; A1-2, AND logic unit; A1-3, NOR logic unit; A2, pixel driving module; A2-1, current source; A2-2, switch transistor; and A2-3, micro-LED pixel.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.

DETAILED DESCRIPTION

Numerous details are described herein in order to provide a thorough understanding of the example embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known processes, components, and materials have not been described in exhaustive detail so as not to unnecessarily obscure pertinent aspects of the embodiments described herein.

The present application relates to the technical field of micro-LED display, and discloses a micro-LED pixel driving circuit and system and a driving method thereof. Specifically, how to drive a pixel when displaying an image picture through pixels is disclosed herein.

In both analog and digital technologies, the information or data, such as any video or audio, is transformed into electric signals. Different from the analog circuits, wherein the information or data is converted into electric pulses of varying amplitude, the digital circuits translate the information or data into binary format (zero or one) , wherein each bit of the data is representative of two distinct amplitudes.

At present, due to the fact that an excessive pixel area is occupied by a pixel driving circuit, there is a technical drawback of low data buffer capacity of a single pixel buffer. The present disclosure solves this technical drawback. In some embodiments, the micro-LED pixel driving circuit comprises a logic operation module and a pixel driving module. The logic operation module and the pixel driving module are electrically connected. In some examples, the logic operation module outputs N bits of Y signals. In some examples, the pixel driving module comprises a current source, a switch transistor and a micro-LED pixel. In some examples, the current source is connected to the source electrode of the switch transistor, the gate of the switch transistor is connected to the output end of the logic operation module and receives the Y signals, the drain electrode of the switch transistor is connected to the positive electrode of the micro-LED pixel, and the negative electrode of the micro-LED pixel is grounded. The present disclosure introduces the I/O transistor of only one high-voltage transistor, and the Core transistor is adopted by other devices, so that the data buffer capacity of a single pixel is improved, and the objective of simplifying control is achieved. For example, the data buffer capacity of the single pixel display is improved by 100%or more (at least doubling the previous data buffer capacity) . In some examples, the high-voltage transistors refer to low-leakage transistors. In some examples, the high-voltage transistors include the high-voltage field effect transistors (FETs) . In some examples, a low leakage transistor has a very low off-leakage current. In some examples, the high-voltage transistors handle input/output signals which require higher supply voltage (e.g., 1.8 V, 2.5 V, or 1.8 V to 3.3 V, or other ranges depending on the circuit) than other Core logic devices/transistors within the same integrated circuit chip/board. In some examples, the other Core logic transistors may need lower supply voltage (e.g., 0.9 V-1.2V, or other ranges depending on the circuit) than the high-voltage transistors. In some examples, the Core logic transistors include the Core FETs. The micro-LED pixel driving system disclosed herein drives the micro-LED pixels to display images on a display screen.

In one or more implementations, a micro-LED pixel driving system, as shown in FIG. 1, comprises a display matrix 01, a time sequence control system 02 and a frame buffer system (or cache system) 03. In the field of Micro-LED display, the display matrix 01 refers to an array composed of a plurality of Micro-LED pixels (such as 2040 *1080) , the time sequence control system 02 is an integrated control chip, and the frame buffer system 03 is a memory. In some examples, the frame buffer system 03 is used for accessing and storing external image data, and the frame buffer system 03 is in connection with the display matrix 01 for data transmission, so that the data stored in the frame buffer system 03 can be displayed by the display matrix 01. In practice, the image in the display matrix 01 needs to meet various color requirements. Therefore, it is necessary to control the time sequence of data transmission from the frame buffer system 03 to the display matrix 01 or the display brightness and grayscale of the display matrix 01. In some examples, the time sequence control system 02 is electrically connected between the display matrix 01 and the frame buffer system 03, so as to drive and load the data in the frame buffer system 03 through the time sequence control system 02.

FIG. 3 illustrates a circuit structure diagram of an exemplary micro-LED pixel driving system (e.g., the micro-LED pixel driving system of FIG. 2) .

In one or more implementations, a micro-LED pixel digital driving circuit, as illustrated in FIGS. 2-3, comprises the micro-LED pixel unit 1, a time sequence control circuit module 2, a data buffer conversion module 3, and a reference current module 4. In some examples, the reference current module 4 is used for supplying constant current to the micro-LED pixel unit 1. The data buffer conversion module 3 performs format conversion on the external input data and stores the external input data. The data buffer conversion module 3 is electrically connected to the micro-LED pixel unit 1, so that the data stored in the data buffer conversion module 3 can be displayed through the micro-LED pixel unit 1. The time sequence control circuit module 2 is electrically connected between the data buffer conversion module 3 and the micro-LED pixel unit 1 and is used for driving and controlling the display sequence and other display parameters of the micro-LED pixel unit 1. In FIG. 2, the display matrix 01 includes one or more of the micro-LED pixel units 1.

In some examples, the micro-LED pixel unit 1 is a single pixel in the display matrix 01. In some examples, as shown in FIG. 3, the reference current module 4 comprises a current source 4-1 and a current mirror 4-2, wherein one end of the current source 4-1 and one end of the current mirror 4-2 are electrically connected, and the other end of the current mirror 4-2 is used for supplying current to the micro-LED pixel unit 1. In some examples, the current mirror 4-2 duplicates the same current from the current source and supplies a constant current to each of the micro-LED pixel unit 1.

In some examples, the time sequence control circuit module 2 and the circuit structure of the data buffer conversion module 3 are arranged as follows: the components in the time sequence control circuit module 2 comprise a time sequence control unit 2-1, a subframe control unit 2-2 and subframe control switches SF0, SF1, …, and SFn, wherein the number of the subframe control switches may be N (N is positive integer) . In some examples, subframe control unit 2-2 controls global brightness of each of the pixels of the display matrix 01, and each of the pixels of the display matrix 01 is connected to the same set of subframe control switches SF0, SF1, …, and SFn for brightness control. Taking the number of the subframe control switches being 4 as an example, the subframe control switches comprise SF0, SF1, SF2 and SF3. The components in the data buffer conversion module 3 comprise a bit conversion unit 3-1, an external data input port 3-2, a memory 3-3, and data transmission switches B0, B1, …, and Bn. The number of the data transmission switches may be N. In this example, the number of the data transmission switches is set to 4 as an example, that is, the data transmission switches comprise B0, B1, B2, and B3. In some examples, the value of N is selected according to the number of bits of the image data or a fraction of the number of bits of the image data (for example, 1/2, 1/4, 1/8, 1/16, 1/32, etc. ) .

In some examples, high-voltage transistors are selected for SF0, SF1, SF2 and SF3 and B0, B1, B2 and B3. The source electrodes of SF0, SF1, SF2 and SF3 are connected to the current mirrors 4-2, the drain electrodes of SF0, SF1, SF2 and SF3 are respectively connected to the drain electrodes of B0, B1, B2 and B3, and the source electrodes of B0, B1, B2 and B3 are connected to the micro-LED pixel unit 1. In some examples, the subframe control switches and the data transmission switches are transistors, such as field-effect transistor (FET) , metal–oxide–semiconductor field-effect transistor (MOSFET) , bipolar junction transistor (BJT) .

In some examples, the gates of SF0, SF1, SF2 and SF3 are respectively connected to corresponding output ports on the subframe control unit 2-2. The time sequence control unit 2-1 is electrically connected to the subframe control unit 2-2. The gates of B0, B1, B2 and B3 are respectively connected to corresponding data output ports of the memory 3-3. The external data input port 3-2 is arranged on an input end of the memory 3-3, and the bit conversion unit 3-1 is arranged on an input end of the memory 3-3.

In some examples, each of the circuit structures of the time sequence control unit 2-1, the subframe control unit 2-2, the bit conversion unit 3-1, the external data input port 3-2, and the memory 3-3 may be understood and implemented by a person of ordinary skills in the art. For examples, the time sequence control unit 2-1, the subframe control unit 2-2, the bit conversion unit 3-1, the external data input port 3-2, and the memory 3-3 are implemented by application-specific integrated circuits (ASICs) using p-channel metal–oxide–semiconductor (PMOS) or n-channel metal–oxide–semiconductor (NMOS) , or other types of transistors. In some examples, the time sequence control unit 2-1, the subframe control unit 2-2, the bit conversion unit 3-1, the external data input port 3-2, and the memory 3-3 may be implemented by other integrated circuit chip or board including field-programmable gate array (FPGA) . The memory 3-3 may be implemented by static random-access memory (SRAM) , or dynamic random-access memory (DRAM) .

In the micro-LED pixel digital driving system described especially in FIG. 3, many switch transistors are included in the driving circuit of the micro-LED device to drive at least one single pixel, and the switch transistors are high-voltage transistors, which are referred to as Input/Output (I/O) devices. The high-voltage transistors occupy most of the pixel area, that directly leads to a limited data buffer capacity of a single pixel, and a complex control scheme. In some examples, an improved micro-LED pixel digital driving system is further described below, so that the data buffer capacity of a single pixel can be improved, and the control scheme for the micro-LED pixel digital driving system can be simplified.

In some examples, the structure of the micro-LED pixel driving circuit as described above in FIG. 1 is shown in conjunction with FIGS. 4-6. In some examples, the structures shown in FIGS. 4-6 are mainly applied to a pixel driving design with an extremely small size in the field (e.g., under 50 um, under 20 um, under 10 um, or preferably under 4 um, for example 2-20 um) .

In some examples, the structure comprises a logic operation module A1 and a pixel driving module A2. The logic operation module A1 and the pixel driving module A2 are electrically connected.

In some examples, the logic operation module A1 receives three types of signals, namely, first, an N-bit image data signal D; second, a time sequence control signal SF for controlling the time sequence of images; and third, a WL signal used for converting the N-bit image data signal D into a data signal DL which can be operated by the logic operators. Then, the logic operation module A1 outputs an N-bit Y signal. In some examples, the time sequence control signals SF adjust the rising and falling time of the data signals by controlling the on/off sequences of switches.

In some examples, the pixel driving module A2 comprises a current source A2-1, a switch transistor 2-2 and a micro-LED pixel A2-3. The current source A2-1 is connected to the source electrode of the switch transistor A2-2, the gate of the switch transistor A2-2 is connected to the output end of the logic operation module A1 and receives the Y signal, the drain electrode of the switch transistor A2-2 is connected to the positive electrode of the micro-LED pixel A2-3, and the negative electrode of the micro-LED pixel A2-3 is grounded.

In some examples, the logic operation module A1 comprises a conversion unit A1-1, an AND logic unit A1-2 and a NOR logic unit A1-3. The input end of the conversion unit A1-1 receives the N-bit image data signal D and the WL signal used for converting the N-bit image data signal D into a data signal DL which can be operated by the logic operator, and the output end of the conversion unit A1-1 outputs a data signal DL which can be operated by the logic operator. The input end of the AND logic unit A1-2 receives the DL signal and the SF signal and outputs an operation result Y signal after performing the AND logic operation on the two signals. The plurality of Y< N-1: 0 > signals are input into the NOR logic unit A1-3 to perform NOR logic operation and the result is transmitted to the gate of the switch transistor A2-2 to control the switching state of the switch transistor A2-2.

In some examples, especially as shown in FIG. 5 and FIG. 6, the conversion unit A1-1 is configured as an N-bit static random-access memory (SRAM) cell latch. In FIG. 6, the N-bit SRAM cell latch A1-1 is N 1-bit SRAM cells. The number of the AND logic units A1-2 is N (N is a positive integer) . The NOR logic unit A1-3 can be a module for realizing N input, for example, a combination module with a plurality of NOR logic units A1-3. The number of the switch transistors A2-2 is 1. N bit can be 1 bit, 4 bits, 8 bits or 16 bits. In some examples, N bit may be any number of bits. In some examples, N bit may be 2^k bit, wherein k is a non-negative integer. In some examples, the switch transistor A2-2 is a high-voltage transistor.

In some examples, a novel micro-LED pixel driving method uses a 4-bit image data type, and from FIG. 5 and FIG. 6 the method comprises the following steps:

Step 1: the conversion unit A1-1 receives the source image data signal D and converts the signal D into the signal DL under the trigger of the WL signal. Before the signal DL completes a logic operation, for example, the conversion to DL, the conversion unit A1-1 stores the signal D in the latch and locks the signal format conversion. Under the trigger of the next signal WL, the signal D is converted into the signal DL, and the next signal D follows the same conversion pattern. In some examples, WL may act like a switch. When WL is in a high state, DL and D are connected, and DL becomes the state of D, which may be either a high or low state. When WL is in a low state, DL and D are disconnected, and DL maintains the state of D before WL becomes the low state. For example, at a time T0, D is in a high state and WL is in a low state. At a time T1, WL becomes a high state, the state of D is transmitted to DL, and DL becomes a high state; At a time T2, WL becomes a low state and DL remains the high state. At a time T3, WL is in a low state, D is in a low state, and DL remains the high state. At a time T4, WL becomes a high state, the state of D is transmitted to DL, and DL becomes a low state. At a time T5, WL becomes a low state and DL remains the low state.

Step 2: a time sequence control signal SF of 4 bits and a signal DL of 4 bits are synchronously operated on a plurality of AND logic operation branches respectively, and an output operation result is Y< 3: 0 >. Herein, Y< 3: 0 > means Y0, Y1, Y2, and Y3.

Step 3: the result Y< 3: 0 > of the synchronous operation on a plurality of AND logic operation branches is jointly operated on a NOR logic operator, and a VPX signal is an output from the NOR logic operator by the NOR logic unit A1-3.

Step 4: the VPX signal is sent to the gate of the switch transistor A2-2 in the pixel driving module A2, so as to control the switch, and the brightness and the grayscale of the micro-LED pixel 2-3.

It is understood by those skilled in the art that, the micro-LED pixel driving system is not limited by the structure mentioned above, and may include more or less components than those as illustrated, or some components may be combined, or a different component may be utilized.

The above descriptions are merely embodiments of the present disclosure, and the present disclosure is not limited thereto. A modifications, equivalent substitutions and improvements made without departing from the conception and principle of the present disclosure shall fall within the protection scope of the present disclosure.

Further embodiments also include various subsets of the above embodiments including embodiments as shown in FIGS. 1-6 combined or otherwise re-arranged in various other embodiments.

Although the detailed description contains many specifics, these should not be construed as limiting the scope of the disclosure but merely as illustrating different examples and aspects of the disclosure. It should be appreciated that the scope of the disclosure includes other embodiments not discussed in detail above. For example, the approaches described above may be applied to the integration of functional devices other than LEDs and OLEDs with control circuitry other than pixel drivers. Examples of non-LED devices include vertical cavity surface emitting lasers (VCSEL) , photodetectors, micro-electro-mechanical system (MEMS) , silicon photonic devices, power electronic devices, and distributed feedback lasers (DFB) . Examples of other control circuitry include current drivers, voltage drivers, trans-impedance amplifiers, and logic circuits.

The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Features of the present disclosure may be implemented in, using, or with the assistance of a computer program product, such as a storage medium (media) or computer readable storage medium (media) having instructions stored thereon/in which may be used to program a processing system to perform any of the features presented herein. The storage medium may include, but is not limited to, high-speed random-access memory, such as DRAM, SRAM, DDR RAM or other random-access solid-state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. Memory optionally includes one or more storage devices remotely located from the CPU (s) . Memory or alternatively the non-volatile memory device (s) within the memory, comprises a non-transitory computer readable storage medium.

Stored on any machine readable medium (media) , features of the present disclosure may be incorporated in software and/or firmware for controlling the hardware of a processing system, and for enabling a processing system to interact with other mechanisms utilizing the results of the present disclosure. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments/containers.

It will be understood that, although the terms “first, ” “second, ” etc. may be used herein to describe various elements or steps, these elements or steps should not be limited by these terms. These terms are only used to distinguish one element or step from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. As used in the description of the embodiments and the appended claims, the singular forms “a, ” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising, ” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in accordance with a determination” or “in response to detecting, ” that a stated condition precedent is true, depending on the context. Similarly, the phrase “if it is determined [that a stated condition precedent is true] ” or “if [astated condition precedent is true] ” or “when [astated condition precedent is true] ” may be construed to mean “upon determining” or “in response to determining” or “in accordance with a determination” or “upon detecting” or “in response to detecting” that the stated condition precedent is true, depending on the context.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain principles of operation and practical applications, to thereby enable others skilled in the art to best utilize the disclosure and the various embodiments.

Claims

A micro light-emitting driving circuit, comprising:

a logic operation module; and

a pixel driving module electrically connected to the logic operation module,

wherein the logic operation module receives an N-bit image data signal from an input end of the logic operation module, N is a positive integer, and the logic operation module comprises:

a conversion unit;

an AND logic unit connected to the conversion unit; and

a NOR logic unit connected to the AND logic unit;

wherein

the conversion unit is configured to convert the N-bit image data signal of a first format into a second format;

the AND logic unit is configured to convert the N-bit image data signal of the second format into a third format; and

the NOR logic unit is configured to convert the N-bit image data signal of the third format into a fourth format.
The micro light-emitting driving circuit according to claim 1, wherein the pixel driving module comprises a current source, a switch transistor and a micro-LED pixel, wherein

the current source is electrically connected to a first terminal of the switch transistor,

a gate of the switch transistor is electrically connected to an output end of the logic operation module,

a second terminal of the switch transistor is electrically connected to a first electrode of the micro-LED pixel, and

a second electrode of the micro-LED pixel is grounded.
The micro light-emitting driving circuit according to claim 1, wherein the conversion unit is configured to convert the N-bit image data signal of the first format into the second format upon receiving a trigger signal, the N-bit image data signal of the second format is operable by a logic operator, and the conversion unit is an N-bit static random-access memory (SRAM) cell latch.
The micro light-emitting driving circuit according to claim 1, wherein the AND logic unit is configured receive a time sequence control signal and the N-bit image data signal of the second format from the conversion unit and output the N-bit image data signal of the third format.
The micro light-emitting driving circuit according to claim 1, wherein the conversion unit includes N parallel sub-conversion units, and each of the sub-conversion units is configured to convert one bit of the N-bit image data signal of the first format into the second format upon receiving a trigger signal.
The micro light-emitting driving circuit according to claim 5, wherein the AND logic unit includes N parallel sub-AND logic units, and each of the sub-AND logic units is configured to receive a respective time sequence control signal for a respective bit of the N-bit image data signal of the second format from a respective sub-conversion unit of the conversion unit and output the respective bit of the N-bit image data signal of the third format.
The micro light-emitting driving circuit according to claim 6, wherein the NOR logic unit is configured to receive the N-bit image data signal from the N parallel sub-AND logic units and output the N-bit image data signal of the fourth format.
The micro light-emitting driving circuit according to claim 2, wherein the logic operation module is configured to output the N-bit image data signal of the fourth format to the gate of the switch transistor to control a switching state of the switch transistor.
The micro light-emitting driving circuit according to claim 2, wherein a time sequence control signal and the N-bit image data signal of the second format are both at a first level, the switch transistor is turned on, wherein the first level is a high level or a low level.
The micro light-emitting driving circuit according to claim 1, wherein N=2^k, wherein K is a non-negative integer.
The micro light-emitting driving circuit according to claim 2, wherein the switch transistor is a high-voltage transistor, and the number of switch transistor is 1 for a single micro-LED pixel.
The micro light-emitting driving circuit according to claim 3, wherein the N-bit SRAM cell latch includes N 1-bit SRAM cell latches.
The micro light-emitting driving circuit according to claim 12, wherein each of the N 1-bit SRAM cell latches stores one bit of the N-bit image data signal.
A micro light-emitting driving method, comprising:

providing an N-bit image data signal to an input end a logic operation module, wherein N is a positive integer;

converting the N-bit image data signal of a first format into a second format by a conversion unit of the logic operation module;

converting the N-bit image data signal of the second format into a third format by an AND logic unit of the logic operation module;

converting the N-bit image data signal of the third format into a fourth format by an NOR logic unit of the logic operation module; and

connecting a pixel driving module to an output end of the logic operation module.
A micro light-emitting display system, comprising:

one or more micro-light-emitting-diode (micro-LED) pixels;

a time sequence control circuit module; and

a data buffer conversion module, wherein the data buffer conversion module comprises:

a logic operation module; and

a pixel driving module electrically connected to the logic operation module,

wherein the logic operation module receives an N-bit image data signal from an input end of the logic operation module, N is a positive integer, and the logic operation module comprises:

a conversion unit;

an AND logic unit connected to the conversion unit; and

a NOR logic unit connected to the AND logic unit;

wherein

the conversion unit is configured to convert the N-bit image data signal of a first format into a second format;

the AND logic unit is configured to convert the N-bit image data signal of the second format into a third format; and

the NOR logic unit is configured to convert the N-bit image data signal of the third format into a fourth format.