AU2008200600B2 - Channel coding/decoding apparatus and method for a CDMA mobile communication system - Google Patents

Description

AUSTRALIA Patents Act 1990 COMPLETE SPECIFICATION Standard Patent Applicant(s) SAMSUNG ELECTRONICS CO., LTD. Invention Title: CHANNEL CODING/DECODING APPARATUS AND METHOD FOR A CDMA MOBILE COMMUNICATION SYSTEM The following statement is a full description of this invention, including the best method for performing it known to me/us: CHANNEL CODING/DECODING APPARATUS AND METHOD FOR A CDMA MOBILE COMMUNICATION SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a code generator for a CDMA mobile communication system, and in particular, to a TFCI (Transport Format Combination Indicator) code generator and a method for embodying the same. 2. Description of the Related Art An IMT-2000 system, a future CDMA mobile communication system, transmits various service frames for supporting a voice service, an image service, and a data service within one physical channel. The service frames are transmitted at either a fixed data rate or a variable data rate. The different services transmitted at the fixed data rate are not required to separately notify a spreading rate to a receiver. However, the services transmitted at the variable data rate must inform the receiver of the spreading rates of the respective service frames, since the data rate may be changed during the services. The spreading rate is determined depending on the data rate. In the IMT-2000 system, the data rate is in inverse proportion to the data spreading rate. When the frames used by the respective services have different data rates, a TFCI (Transport Formation Combination Indicator) bit is used to indicate a combination of the currently transmitted services. The TFCI enables correct reception of the services. FIG. I illustrates a method of using the TFCI in an NB-TDD (Narrow Band-Time Division Duplex) system, by way of example. In particular, the NB TDD system uses 8PSK (8-ary Phase Shift Keying) modulation for high-speed data transmission, and codes the TFCI value with a length=24 code before transmission. Referring to FIG. 1, one frame is comprised of two subframes. The subframes each include 7 time slots TS#O-TS#6, a downlink pilot time slot 2 DwPTS, a guard period where no signal is transmitted, and an uplink pilot time slot UpPTS. The 7 time slots TS#0-TS#6 are divided into downlink time slots TS#O, TS#4, TS#5 and TS#6, and uplink time slots TS#l, TS#2 and TS#3. Each time slot comprises data fields for storing data symbols, two TFCI fields for storing TFCIs associated with the data symbols stored in the data fields, a field for storing a midamble, a field for storing SS symbols, and a field for storing TPC (Transmission Power Control) symbols. A time length of the frame is Tf=Oms, and a time length of the subframe is Tf=5ms. In addition, a time length of each time slot is Tsio=0.625ms. FIG. 2 illustrates a structure of a transmitter in the conventional NB-TDD CDMA mobile communication system. Referring to FIG. 2, a TFCI encoder 200 encodes input TFCI bits at a given coding rate and generates coded TFCI symbols. The coded TFCI symbols are provided to a first multiplexer (MUX) 210 as one input. At the same time, other signals comprised of the data symbols, the SS symbols and the TPC symbols included in one slot of FIG. I are provided to the first multiplexer 210 as another input. The coded TFCI symbols, the data symbols, the SS symbols, and the TPC symbols are multiplexed by the first multiplexer 210. The multiplexed signals are then channel-spread with an orthogonal code by a channel spreader 220. The channel spread-signal signals are scrambled with a scrambling code by a scrambler 230, and then provided to a second multiplexer 240 as one input. At the same time, a midamble signal is provided to the second multiplexer 240 as another input, and multiplexed with the scrambled signals. As a result, the second multiplexer 240 outputs a signal having the slot format shown in FIG. 1. The first and second multiplexers 210 and 240 output the frame format of FIG. 1, under the control of a controller (not shown). FIG. 3 illustrates a structure of a conventional NB-TDD receiver corresponding to the above-described transmitter. Referring to FIG. 3, a signal received from the transmitter is demultiplexed by a first demultiplexer (DEMUX) 340, so that a midamble signal is separated from the received signal. The midamble-removed signal is descrambled by a descrambler 330 with the scrambling code used by the transmitter. The descrambled signal is channel despread by a channel despreader 320 with the orthogonal code used by the 3 transmitter. The despread signal is demultiplexed (separated) into coded TFCI symbols and other signals by a second demultiplexer 310. The "other signals" refers to the data symbols, the SS symbols and the TPC symbols. The separated coded TFCI symbols are decoded into TFCI bits by a TFCI decoder 300. The TFCI bits indicate 2 to 4 combinations expressed with I to 2 bits according to combination of transmission information, and default TFCI bits indicate 8 to 32 combinations expressed with 3 to 5 bits. In addition, extended TFCI bits indicate 64 to 1024 combinations expressed with 6 to 10 bits. The TFCI bits are required information when the receiver analyzes transmission information of the received frames. Therefore, if a transmission error occurs in the TFCI bits, the receiver may not correctly receive the respective service frames. For this reason, the TFCI bits are encoded at the receiver using a high efficiency error correcting code capable of correcting a possible transmission error. FIG. 4 illustrates an error correction encoding scheme for a 5-bit default TFCI. In particular, FIG. 4 illustrates a structure of a (24,5) encoder by way of example. That is, the drawing shows a scheme for outputting a 24-symbol coded TFCI by encoding a 5-bit default TFCI. Referring to FIG. 4, a (16,5) bi-orthogonal code encoder 400 encodes 5 bit TFCI input information into a 16-symbol coded TFCI, and provides the 16 symbol coded TFCI to a repeater 410. The repeater 410 outputs the intact even numbered symbols out of the provided coded TFCI symbols, and repeats the odd numbered symbols, thus outputting a total of 24 coded TFCI symbols. Herein, the scheme has been described with reference to the 5-bit input TFCI. However, when the input TFCI is comprised of less than 5 bits, a zero (0) bit(s) is added at the head of the input TFCI to make a TFCI having a length of 5 bits. An intercode minimum distance of the (16,5) bi-orthogonal encoder 400 is 8. In addition, even the (24,5) code output from the repeater 410 also has the minimum distance of 8. In general, an error correcting capability of binary linear codes depends on the intercode minimum distance of the binary linear codes. A reference, An Updated Table of Minimum-Distance Bounds for Binary Linear 4 Codes (A.E. Brouwer and Tom Verhoeff, IEEE Transactions on information Theory, VOL 39, NO. 2, MARCH 1993), discloses an intercode minimum distance which depends on the input and output values of the binary liner codes to be optimal codes depending on the number of coded symbols generated by encoding input information bits. 5 Taking into consideration the fact that the TFCI transmitted in FIG. 4 is comprised of 5 bits and the coded TFCI is comprised of 24 symbols, the intercode minimum distance required in the above-stated reference is 12. However, since the minimum distance between the coded symbols output from the encoder shown in FIG. 4 is 8, the encoder does not have 10 the optimal codes. If the error correction encoding scheme of FIG. 4 fails to have the optimal codes, an error rate of the TFCI bits increases in the same channel environment. As a result, the receiver may erroneously recognise a data rate of the data frames, increasing frame error rate (FER). Therefore, there is a demand for an error correction encoding scheme capable of obtaining optimal codes through encoding of the TFCI bits. 15 SUMMARY OF THE INVENTION According to one aspect of the present invention there is provided an apparatus for encoding k input information bits in a transmitter for a communication system comprising: an encoder for encoding the k input information bits by multiplying the k input 20 information bits with first order Reed-Muller codes based on the k input information bits and t selected linearly independent k1h order vectors to generate and output ( 2 k-2') encoded bits. According to another aspect of the present invention there is provided a 25 communication apparatus comprising: an encoder for encoding k input information bits by multiplying the k input information bits with first order Reed-Muller codes based on the k input information bits and t selected linearly independent kth order vectors to generate and output ( 2 k-2t) encoded bits; 30 a transmitter configured to transmit the ( 2 k- 2 ') encoded bits output from the encoder in a signal; 5 a receiver configured to receive the ( 2 k- 2 t) encoded bits from the transmitted signal; and a decoder configured to decode the ( 2 k- 2 t) encoded bits. 5 BRIEF DESCRIPTION OF THE DRAWINGS Objects, features and advantages of the present invention will become more apparent from the following detailed description when taken into conjunction with the accompanying drawings in which: FIG. I is a diagram illustrating a frame format in a conventional NB 10 TDD CDMA mobile communication system; FIG. 2 is a diagram illustrating a structure of a transmitter in the conventional NB-TDD CDMA mobile communication system; FIG. 3 is a diagram illustrating a structure of a receiver corresponding to the transmitter shown in FIG. 2; 15 FIG. 4 is a diagram illustrating a structure of a conventional (24,5) TFCI encoder; FIG. 5 is a flow chart illustrating a procedure for calculating optimal puncturing positions according to an embodiment of the present invention; FIG. 6 is a diagram illustrating a structure of an encoder included in a 20 transmitter according to an embodiment of the present invention; FIG. 7 is a diagram illustrating a structure of a decoder included in a receiver according to an embodiment of the present invention. FIG. 8 is a diagram illustrating a detailed structure of the encoder according to an embodiment of the present invention; and 25 FIG. 9 is a diagram illustrating a detailed structure of the encoder according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 30 A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known 6 functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Embodiments of the present invention relate to a method for encoding TFCI bits 5 so that the CDMA mobile communication system using the TFCI bits creates optimal codes. For example, the present invention applies punctured (24,5) first order Reed Muller codes obtained by puncturing 8 symbols out of the coded symbols output by first order Reed-Muller codes of length 32 to the CDMA mobile communication system. That is, the punctured (24,5) first order Reed-Muller codes are 24 coded symbols 10 obtained by puncturing 8 symbols out of the 32 coded symbols output by the punctured first order Reed-Muller codes of length 32. A change in the puncturing positions of the 8 symbols may vary a minimum distance dmin of the punctured (24,5) first order Reed-Muller codes. The minimum 15 distance refers to the minimum value out of Hamming distance values of several codewords. As the minimum distance increases more and more, the linear error correcting codes have improved error correcting capability. That is, Hamming distance distribution for codewords of the error correcting codes can serve as a measure indicating the capability of the error correcting codes. This means the number of non 20 zero symbols in the respective codewords. That is, for a certain codeword '0111', the number of l's, i.e., the Hamming distance is 3. An increase in the minimum distance corresponding to the minimum value out of such Hamming distance values improves the error correcting capability of the first order Reed-Muller codes. This indicates that it is important to calculate puncturing positions in order to create the punctured (24,5) 25 first order Reed-Muller codes having superior error correcting capability in the punctured first order Reed-Muller codes of length 32. Actually, the (24,5) first order Reed-Muller codes are obtained by puncturing 23 (=8) symbols from the (32,5) first order Reed-Muller codes. This is an 30 example generalised by applying k=5 and t=3 to ( 2 k -,k) first order Reed-Muller codes obtained by puncturing 2' bits from ( 2 k k) first order Reed-Muller codes. An encoder 7 generating the ( 2 k 2 ',k) first order Reed-Muller codes has a minimum distance of k 2 _ 1-2'-1. Therefore, embodiments of the present invention disclose a method for 5 calculating 2'puncturing positions for optimizing the (2 k- 2 ', k) first order Reed-Muller codes created by puncturing 2! bits from the (2kk) first order Reed-Muller codes. In the following description, the (2 2 ',k) first order Reed-Muller codes will be referred to as "(2k-2',k) codes" for short. Before describing the method for calculating the optimal puncturing positions, a mathematical term, which becomes a background of the invention, will be defined. A linear independent property for a vector space V having a kth order vector v (=vk, . . .,v', v 0 ) as its elements is defined by Equation (1). v ,v',..,v' linear independent property e> c 1 v t +.--+ cv' + cOv w 0, V cO,c,,..., c FIG. 5 illustrates a procedure for calculating optimal puncturing positions in a CDMA mobile communication system according to an embodiment of the present invention. Refering to FIG. 5, t linearly independent kth order vectors v0 v . ., vi- are selected by Equation (1) in step 500. After the t k' order vectors are selected, possible linear combinations c' for the selected t k order vectors v", v', . . ., v'- are calculated by Equation (2) in step 510. c' ... , ....... (2) where i indicates an index for the number of the linear combinations, and k indicates the order of the vector, or indicates the number of vector coordinates. The total number of the possible liner combinations, which can be calculated by Equation (2), becomes 2'. Thereafter, in step 520, puncturing positions pi for the calculated 2' possible linear combinations are calculated by Equation (3). 8 k- ' I = c,2 t = ,. . . .. .. .. (3) j=0 Equation (3) serves to convert the respective 2' linear combinations c' to decimal numbers. For better understanding of the above-stated procedure, a method for calculating the puncturing positions of the (24,5) codes, which are k=5, t=3 ( 2 k 2',k) codes, will be described herein below. First, in step 500, 3 linearly independent 5' order vectors v 0 =(0,0,0,0,l) v'=(0,0,0,1,0) and v 2 (0,0,1,0,0) are selected. Next, all the possible linear combinations c' for the selected three 5 (h order vectors v0, v' and V2 are calculated by Equation (2) in step 510. The possible linear combinations c' calculated by Equation (2) are given as follows: c'=(0,0,0,0,0), 20 c2=vl=(0,0, 0, 0,1), c 3 =v'=(0,0,0,1,1), c 4 =v'+v,=(0,0,0,1,1), c 5 =v 2 =(0,0, 1,0,0), c6 2 0 c 6v 2+V 0=(0, 0,1,0, 1) c 7 =v 2 +v'=(0,0, 1,1,0), c 8 =v 2 +v'+v 0 =(0,0,0,0,1) After all the possible linear combinations are calculated in step 510, the puncturing positions pi for the calculated possible 23=8 linear combinations are calculated by Equation (3) in step 520. The puncturing positions calculated by Equation (3) are given as follows: p 1 =0-2 4 +0.2 3 +0.2 2 +0.2'+0.2=O0, P2=0.2'+0-23+0-22+0-2'+1 2'=1, p3=0-2 4 +0-2 3 +0-2 2 +1 -2'+0.2'=2, P4=0-2±+0-23+0-22+1.2'+1 2'=3, p 5 =0.24+0-23+1-22+02'+0.20=4, p,=0.2+0-2 3+1.22+0.2'+1 .2=5, p7=0-2+0-23+1 .22+1 -2'+0.2'=6, p,=0- 2 +0-2 3+1.22+1 2'+ 1 .2'=7 9 Therefore, for k=5 and t=3, it is possible to obtain optimal (24,5) codes sI nd rd th 1h 1h 1 by puncturing Oh, 1s, 2 , 3 4 , 5 , 6 and 7 'h symbols of the (32,5) first order Reed-Muller codes. Actually, there exist many other puncturing positions in addition to the puncturing positions of the (32,5) first order Reed-Muller codes for calculating the optimal (24,5) codes. The other puncturing positions excepting the above stated puncturing positions can be calculated using the linear combination c'. That is, the other optimal puncturing positions can be calculated by performing step 520 of FIG. 5 on vectors c' determined by multiplying a kxk invertible k-I matrix A by the linear combination c'. The result is H 7 1

(

2 ' - 2') kxk invertible j=0 matrixes. It is possible to easily calculate the number of kxk invertible matrixes from a method for creating matrixes having inverse matrixes. In the method for calculating the kxk invertible matrixes, for a first column, kth order column vectors, which are non-zero vectors, are selected and arranged, and the number of such cases is 2 -20. For a second column, the column vectors, which are not zero vectors nor the column vectors used for the first column, are selected and arranged, and the number of such cases is 2k- 2 . For a third column, the column vectors, which are not the column vectors determined by the linear combinations of the column vectors used for the first and second columns, are selected and arranged, and the number of such cases is 2 k- 2 1. In this method, for an ith column, the column vectors which are not the column vectors determined by the linear combinations of the (i-I) column vectors used for the first to (i-1)'h columns, are selected and arranged, and the number of such cases is 2

-

2 'i-1. It is possible to easily calculate the invertible matrixes by selecting and arranging the column A-I vectors in this manner. The number of all the invertible matrixes is 1

J(

2 * - 2 j) j=0 For example, the above-stated example will be described with reference to a 5x5 invertible matrix A shown in Equation (4). 10 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ....... (4) 1 0 0 0 0 ,0 1 0 0 0 The vectors c' calculated by multiplying the kxk invertible matrix A by linear combinations ciT are given as follows: c' =A.c ITT=(00,,OO) c2=A-c 2T=( 0

,

0

,

1

,

0 0 )T, c14=A .cT=(0, 1 , 0

,

0

,

0 )T, c'4= -4T=0 ,,,), c=A-c 5T=( 1 ,0,0,0, 0 )T, C'6= -6TT c =A-c T=( 1

,,

0

,

0 0)T, c 7 =A-c 7 T=(1,1,0,OO)T c.8Ac CT(, l 100 )T In the above process, T indicates transpose, and the row vectors ciT are transposed into column vectors and then multiplied by the matrix A. After all the possible combinations stated above are calculated, the puncturing positions pi for the calculated vectors c, iT are calculated using Equation (3) in step 520. The puncturing positions calculated by Equation (3) are as follows: p,=0-2 4 +0-2 3 +0-2 2 +0.2'+0-20=0, P2= 0 -24+0-2+1 -22+0.2'+0-2'=4, p3=0.2 4 + 1.23+0-22+0.2'+0.2'=8, pa=0.2+1-23+1 22+1 -2'+0.2'=12, p5= 1-2 4 +0.2 3 +0.2 2 +0.2'+0. 2=l 6, p6=1 24+0.2+1 .22+0.2'+0-2'=20, p7=1 -2'+1 .23+0.22+0.21+0-2'=24, 11 pg=1 2 '+1-2+1.2 2+0.21+0.20=28 Therefore, for k=5 and t=3, it is possible to obtain the optimal (24,5) codes by puncturing the other optimal puncturing positions of 0th 4 h 8 th , 2 th 16 h, 2 0 th 24 th and 2 8 th from the (32,5) first order Reed-Muller codes. Next, a description of the invention will be made with reference to embodiments where the above-provided (2 k 2 ,k) codes are used and in particular, the (24,5) codes using the two types of the above-calculated puncturing positions are used. First Embodiment The first embodiment of the present invention provides an encoding apparatus and method for a transmitter based on the above-stated optimal code generation method. FIG. 6 illustrates a structure of an encoder included in a transmitter for a CDMA mobile communication system according to an embodiment of the present invention. Referring to FIG. 6, a (32,5) first order Reed-Muller encoder 600 encodes 5 input information bits of aO, al, a2, a3 and a4, and outputs a coded symbol stream comprised of 32 coded symbols. FIG. 8 illustrates a detailed structure of the first order Reed-Muller encoder 600. Referring to FIG. 8, the 5 input information bits aO, al, a2, a3 and a4 are provided to their associated multipliers 840, 841, 842, 843 and 844, respectively. At the same time, a Walsh code generator 810 generates Walsh codes W1, W2, W4, W8 and W16, and provides the generated Walsh codes WI, W2, W4, W8 and W16 to the associated multipliers 840, 841, 842, 843 and 844, respectively. More specifically, the Walsh code WI= 01010101010101010101010101010101 is provided to the first multiplier 840, and the Walsh code W2= 00110011001100110011001100110011 is provided to the second multiplier 841. Further, the Walsh code W4= 00001111000011110000 111100001111 is provided to the third multiplier 842, the 12 Walsh code W8= 00000000111111110000000011111111 is provided to the fourth multiplier 843, and the Walsh code W16= 00000000000000001111111111111111 is provided to the fifth multiplier 844. The first multiplier 840 multiplies the input information bit aO by the Walsh code WI in a bit unit and outputs 32 coded symbols. That is, the first multiplier 840 encodes the information bit a0 with the Walsh code WI of length 32 and outputs a coded symbol stream comprised of 32 coded symbols. This same process is repeated with the remaining information bits (al-a4) and Walsh Codes (W2, W4, W8 and W16) by the respective multipliers 841-844. The five coded symbol streams output from the first to fifth multipliers 840, 841, 842, 843 and 844 are provided to a summer 860. The summer 860 sums up the five coded symbol streams output from the first to fifth multipliers 840, 841, 842, 843 and 844 in a symbol unit, and outputs one coded symbol stream of length 32. In the first embodiment, the first order Reed-Muller encoder 600 encodes the 5 input information bits with different Walsh codes, sums up the encoded information bits, and outputs one coded symbol stream of length 32. However, as another example, it is also possible to embody a method for outputting a coded symbol stream of length 32, which corresponds to the 5 input information bits. That is, the first order Reed-Muller encoder 600 includes a memory table for storing different coded symbol streams of length 32 corresponding to the 5 respective input information bits, and reads out the coded symbol stream corresponding to the 5 input information symbols. The coded symbol stream output from the first order Reed-Muller encoder 600 is provided to a puncturer 610. The puncturer 610 punctures the symbols in the 8 puncturing positions determined by the proposed method out of the 32 symbols constituting the provided coded symbol stream. For example, if the optimal puncturing positions are determined as 01h, 1 st, 2 ", 3 rd, 4 t, 5 ,h and 7th symbols, the puncturer 610 punctures the 0', Is, 2 d, 3rd th , 5th ,th and 7 th symbols out of the coded symbols. Therefore, the puncturer 610 outputs a coded symbol stream comprised of 24 symbols, which do not correspond to the 13 puncturing positions. FIG. 7 illustrates a structure of an encoder included in a receiver for a CDMA mobile communication system according to an embodiment of the present invention. Referring to FIG. 7, a zero inserter 710 receives a coded symbol stream of length 24 from the transmitter, and inserts zero (0) bits in the puncturing positions used by the puncturer 610 shown in FIG. 6. That is, when the puncturer 610 has punctured the 0 th Is nd rd 4 th, 5 h 6 th and 7 th coded symbols, the zero inserter 710 inserts the zero bits in the first 8 puncturing positions of the coded symbol stream of length 24, and thus outputs a coded symbol stream of length 32. To this end, the zero inserter 710 must be acquainted with zero insertion positions, i.e., the puncturing positions used by the puncturer 610. This information is provided from the transmitter in a given process. The coded symbol stream of length 32 output from the zero inserter 710 is provided to an inverse fast Hadamard transform part (IFHT) 705. The IFHT 705 compares the provided coded symbol stream of length 32 with all the first order Reed Muller codewords of length 32, and calculates reliabilities of the respective first order Reed-Muller codewords based on the comparison results. The first order Reed-Muller codewords may be the Walsh codes used for encoding by the transmitter, and the reliabilities can be obtained by calculating correlations between the coded symbol stream and the Walsh codes. In addition, the IFHT 705 decodes the coded symbol stream of length 32 with all the first order Reed Muller codewords. The IFHT 705 outputs the calculated reliabilities and the input information bits decoded by the respective first order Reed-Muller codewords. The reliabilities and the decoded information bits make pairs, the number of which is equal to the number of the first order Reed-Muller codewords. The pairs of the reliabilities and the input information bits are provided to a comparator 700. The comparator 700 selects the highest reliability out of the provided reliabilities, and outputs the input information bit pairing with the selected reliability as a decoded bit. The embodiment has determined the 01, 1 , 2"d, 3 4 5 th, 6 th and 7 th symbols as the optimal puncturing positions, by way of example. However, as mentioned above, the O , 4 ', 8th, 12 1 th 2 0 h 2 4 th and 2 8 h symbols may also be used as the optimal puncturing positions. In this case, the zero insertion 14 positions of the zero inserter 710 are also changed according to the puncturing positions. In addition, since the puncturing positions according to the embodiment are so determined as to optimize the capability of the encoder and have simple regularity, it is possible to reduce hardware complexity of the encoder in the transmitter and the decoder in the receiver. Second Embodiment Although the first embodiment has proposed a scheme for puncturing the coded symbol stream, the second embodiment proposes a scheme for puncturing the Walsh codes used for encoding before encoding the input information bits. That is, the second embodiment provides an apparatus and method for performing the puncturing and encoding operations at the same time, without the separate puncturer. FIG. 9 illustrates a detailed structure of the encoder according to the second embodiment of the present invention. Referring to FIG. 9, five input information bits aO, al, a2, a3 and a4 are provided to first to fifth multipliers 940, 941, 942, 943 and 944, respectively. At the same time, a Walsh code generator 910 generates 8-bit-punctured Walsh codes W1, W2, W4, W8 and W16 of length 24. The Walsh codes of length 24 output from the Walsh code generator 910 correspond to the Walsh codes of length 32 used in the first embodiment, from which 8 bits corresponding to the optimal puncturing positions are punctured. That is, as stated above, the optimal puncturing positions correspond to the 0 ', 15s, 2"d, 3'd, 4 h, 5 h, 6th and 7"' bits, or 01h 41, 81h, 2 2h, 16't, 20', 24 and 28" bits. In the following description, the optimal puncturing positions will be assumed to be the 01h, 1", 2"n, 3'd 4 0, 5", 6 and 7 bits. The punctured Walsh codes W1, W2, W4, W8 and W16 output from the Walsh code generator 910 are provided to the first to fifth multipliers 940, 941, 942, 943 and 944, respectively. More specifically, the Walsh code W1= 010101010101010101010101 is provided to the first multiplier 940, and the Walsh code W2= 001100110011001100110011 is provided to the second multiplier 941. Further, the Walsh code W4= 000011110000111100001111 is 15 provided to the third multiplier 942, the Walsh code W8=1 11111110000000011111111 is provided to the fourth multiplier 943, and the Walsh code W16=0000000011111 l1 l11 11 is provided to the fifth multiplier 944. 5 The first multiplier 940 multiplies the input information bit aO by the punctured Walsh code W1 in a bit unit. That is, the first multiplier 940 encodes the information bit a0 with the punctured Walsh code wl of length 24 and outputs a coded symbol stream comprised of 24 coded symbols. This same process is repeated with the remaining information bits (al-a4) and Walsh Codes (W2, W4, W8 and W16) by the respective 10 multipliers 941-944. The five coded symbol streams output from the first to fifth multipliers 940, 941, 942, 943 and 944 are provided to a summer 960. The summer 960 sums up the five coded symbol streams output from the first to fifth multipliers 940, 941, 942, 943 and 15 944 in a symbol unit, and outputs one coded symbol stream of length 24. In FIG. 9, the Walsh code generator 910 outputs the 24-bit Walsh codes obtained by puncturing 8 bits corresponding to the optimal puncturing positions out of the 32-bit Walsh codes. However, in an alternative embodiment, it is also possible to 20 arrange a puncturer at a following stage of the Walsh code generator 910, so that the puncturer punctures the 32-Walsh codes from the Walsh code generator 910. Further, in the embodiments, the first order Reed-Muller encoder 600 encodes the 5 input information bits with the different Walsh codes, sums up the encoded information bits, and outputs one coded symbol stream of length 24. However, in an alternative 25 embodiment, it is also possible to embody a method for outputting a coded symbol stream of length 24, which corresponds to the 5 input information bits. That is, the first order Reed-Muller encoded 600 includes a memory table for storing different coded symbol streams of length 24 corresponding to the 5 respective input information bits, and reads out the coded symbol stream corresponding to the 5 input information 30 symbols. 16 As described above, the NB-TDD CDMA mobile communication system according to embodiments of the present invention optimally encodes and decodes the transport format combination indicator (TFCI) bits to obtain the optimal minimum 5 distance, thereby increasing the error correcting capability. In addition, it is possible to simplify the encoding and decoding schemes by determining the puncturing positions according to the simple regularity. While the invention has been shown and described with reference to a certain 10 preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It is to be understood that, if any prior art publication is referred to herein, such 15 reference does not constitute an admission that the publication forms a part of the common general knowledge in the art, in Australia or any other country. In the claims which follow and in the preceding description, except where the context requires otherwise due to express language or necessary implication, 20 the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. 25 17

Claims (16)

1. 2. An apparatus as claimed in claim 1, further comprising a memory for storing a plurality of first order Reed-Muller codes, and wherein the first order Reed-Muller codes used by the encoder as selected from the plurality of codes based on the k input information bits. 15
2. 3. An apparatus as claimed in claim 1, further comprising a code generator for generating first order Reed-Muller codes for use by the encoder based on the k input information bits. 20 4. An apparatus as claimed in claim 2 or 3, wherein the first order Reed-Muller codes have a length of 2k bits.
3. 5. An apparatus as claimed in claim 4, further comprising a puncturer for puncturing 2' bits from the 2 k bit length Reed Muller codes before use by the encoder to generate ( 2 k 2 t) 25 bit length first order Reed Muller codes for use by the encoder.
4. 6. An apparatus as claimed in claim 4, further comprising a puncturer for puncturing 2t bits from the 2 k encoded bits after multiplication of the k input bits by the 2 k bit length Reed Muller codes by the encoder. 30
5. 7. An apparatus as claimed in claim 2 or claim 3, wherein the first order Reed-Muller codes have a length of ( 2 k t) bits. 1740221_1 (GHMaters) 24/08/09 19
6. 8. An apparatus as claimed in claim 3, wherein the code generator generates first order Reed-Muller codes having a length of( 2 k t) bits by puncturing 2t bits from 2 k bit length first order Reed Muller codes based on the k input information bits. 5 9. An apparatus as claimed in claim 8, wherein the 2 k bit length first order Reed Muller codes are generated by the code generator.
7. 10. An apparatus as claimed in claim 8, wherein the 2 k bit length first order Reed Muller codes are selected from a memory storing a plurality of first order Reed-Muller 10 codes.
8. 11. An apparatus as claimed in any one of the preceding claims, wherein the value K is 5 and the value t is 3. 15 12. An apparatus as claimed in claim I when appended to any one of claims 5, 6 or 8, wherein the 0 th to 7 th bits are punctured.
9. 13. An apparatus as claimed in any one of claims 5, 6 or 8, wherein bits in the 0 th to ( 2 t - I) bit positions are punctured. 20
10. 14. A communication apparatus comprising: an encoder for encoding k input information bits by multiplying the k input information bits with first order Reed-Muller codes based on the k input information bits and t selected linearly independent kth order vectors to generate and output ( 2 k - 2 t) encoded 25 bits; a transmitter configured to transmit the ( 2 k-2t) encoded bits output from the encoder in a signal; a receiver configured to receive the ( 2 k -t) encoded bits from the transmitted signal; and 30 a decoder configured to decode the ( 2 k-2t) encoded bits. 1740221 _(GHMatters) 24/08/09 20
11. 15. An apparatus as claimed in claim 14, wherein the encoder includes a puncturer for puncturing 2t bits from 2 k bit length first order Reed-Muller codes or 2 k encoded bits to generate the output ( 2 k- 2 ) encoded bits. 5
12. 16. An apparatus as claimed in claim 15, wherein bits in Oth to ( 2 t- 1) bit positions are punctured.
13. 17. An apparatus as claimed in any one of claims 14 to 16, wherein the value k is 5 10 and the value t is 3.
14. 18. An apparatus as claimed in claim 17, wherein the 0 th to 7 th bits are punctured.
15. 19. An apparatus as claimed in claim 15 or 18, wherein the decoder includes an 15 inserter configured to insert 2' bits in the punctured positions to reconstruct a first order Reed-Muller code.
16. 20. An apparatus as claimed in claim 19, wherein the decoder further comprises an inverse fast Hadamard transform (IFHT) configured to decode the reconstructed first 20 order Reed-Muller code. 1740221_1 (GHMatters) 24/08/09