AU2012200530B2 - Method and apparatus for encoding and decoding channel in a communication system using low-density parity-check codes - Google Patents

Abstract

A method for a channel encoding in a communication system using a Low-Density Parity Check (LDPC) code. The method includes dividing information bits into a plurality of bit 5 groups; determining a number of information bits to be shortened; determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a predetermined order; and LDPC encoding shortened information bits. 3MO939_1 (GHMaters) P84002.AU.I READ COLUMN GROUP INFORMATION OF DVB-S2 LDPC CODE TO BE 601 SUBJECTED TO SHORTENING DETERMINE CODE LENGTH N2 AND INFORMATION LENGTH K2 603 OF SHORTENED LDPC CODE DETERMINE VALUE A60 ACCORDING TO SHORTENING STEP 1 605 SELECT INFORMATION ON (A+1) COLUMN GROUPS 607 ACCORDING TO SHORTENING STEP 2 GENERATE SHORTENED LDPC CODE USING DVB-82 LDPC CODE GENERATION METHOD 609 ACCORDING TO SHORTENING STEP 3 GENERATE FINAL LDPC CODE BY APPLYING ADDITIONAL SHORTING 611 ACCORDING TO SHORTENING STEP 4 APPLY PUNCTURING IN LDPC ENCODING 61 PROCESS WHEN PUNCTURING IS NEEDED 613

Description

AUSTRALIA Patents Act 1990 COMPLETE SPECIFICATION Standard Patent Applicant (s) SAMSUNG ELECTRONICS CO., LTD. and Postech Academy Industry Foundation Invention Title: Method and apparatus for encoding and decoding channel in a communication system using low-density parity-check codes The following statement is a full description of this invention, including the best method for performing it known to me/us: METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING LOW-DENSITY PARITY-CHECK CODES 5 This patent application is a divisional application of Australian patent application no. 2008332040. This patent application relates to the subject matter disclosed in Australian patent application no. 2008332040. Some description of the invention of Australian patent application no. 2008332040 is included herein to facilitate understanding of the present invention. If necessary, reference may be made to the disclosure of Australian patent 0 application no. 2008332040 to understand the present invention and the whole of the disclosure of Australian patent application no. 2008332040 is incorporated herein by reference. 1. Field of the Invention 5 The present invention relates generally to a communication system using Low Density Parity-Check (LDPC) codes, and in particular, to a channel encoding/decoding method and apparatus for generating LDPC codes having various codeword lengths and code rates from a given LDPC code. 0 2. Description of the Related Art In wireless communication systems, the link performance significantly decreases due to various noises in channels, a fading phenomenon, and Inter-Symbol Interference (ISI). Therefore, in order to realize high-speed digital communication systems requiring high data throughput and reliability, such as the next-generation mobile communication, digital 5 broadcasting, and portable internet, it is necessary to develop a technology for eliminating noise, fading, and ISI. Recently, an intensive study of an error-correcting code has been conducted as a method for increasing communication reliability by efficiently recovering distorted information. An LDPC code, first introduced by Gallager in 1960s, has lost favor over time due to 0 its implementation complexity which could not be resolved by the technology at that time. However, as the turbo code, which was discovered by Berrou, Glavieux, and Thitimajshima in 1993, shows the performance approximating Shannon's channel limit, research has been conducted on iterative decoding and channel encoding based on a graph along with analyses on performance and characteristic of the turbo code. Due to this research, the LDPC code was 5 restudied in the late 1990s, and proved that LDPC code has performance approximating the Shannon's channel limit if it undergoes decoding by applying iterative decoding based on a -2 3090139_1 (GHMatters) P84002.AU.1 sum-product algorithm on a Tanner graph (a special case of a factor graph) corresponding to the LDPC code. The LDPC code is typically represented using a graph representation technique, and many characteristics can be analyzed through the methods based on graph theory, algebra, 5 and probability theory. Generally, a graph model of channel codes is useful for description of codes, and by mapping information on encoded bits to vertexes in the graph and mapping relations between the bits to edges in the graph, it is possible to consider a communication network in which the vertexes exchange predetermined messages through the edges, thus making it possible to derive a natural decoding algorithm. For example, a decoding algorithm 0 derived from a trellis, which can be regarded as a kind of graph, can include the well-known Viterbi algorithm and a Bahl, Cocke, Jelinek and Raviv (BCJR) algorithm. The LDPC code is generally defined as a parity-check matrix, and can be represented using a bipartite graph, which is referred to as a Tanner graph. The bipartite graph means that vertexes constituting the graph are divided into two different types, and the LDPC code is 5 represented with the bipartite graph composed of vertexes, some of which are called variable nodes and the other of which are called check nodes. The variable nodes are one-to-one mapped to the encoded bits. With reference to FIGs. 1 and 2, a description will be made of a graph representation method for the LDPC code. 0 FIG. 1 shows an example of a parity-check matrix Hi of the LDPC code composed of 4 rows and 8 columns. Referring to FIG. 1, since the number of columns is 8, the parity check matrix H 1 means an LDPC code that generates a length-8 codeword, and the columns are mapped to 8 encoded bits. FIG. 2 is a diagram illustrating a Tanner graph corresponding to Hi of FIG. 1. 25 Referring to FIG. 2, the Tanner graph of the LDPC code is composed of 8 variable nodes x 1 (202), x 2 (204), x 3 (206), x 4 (208), x 5 (210), x 6 (212), x7 (214) and x8 (216), and 4 check nodes 218, 220, 222 and 224. An ith column and a jth row in the parity-check matrix H, of the LDPC code are mapped to a variable node xi and a jth check node, respectively. In addition, a value of 1, i.e., a non-zero value, at the point where an ith column and a jth row in 0 the parity-check matrix H, of the LDPC code cross each other, means that there is an edge between the variable node xi and the j'h check node on the Tanner graph of FIG. 2. In the Tanner graph of the LDPC code, a degree of the variable node and a check node means the number of edges connected to each respective node, and the degree is equal to the number of non-zero entries in a column or row corresponding to the associated node in 5 the parity-check matrix of the LDPC code. For example, in FIG. 2, degrees of the variable nodes xi (202), x 2 (204), x 3 (206), x 4 (208), x 5 (210), x6 (212), x7 (214) and x 8 (216) are 4, 3, -3 30901391_ (GHPatems) P84002 AU1 3, 3, 2, 2, 2 and 2, respectively, and degrees of check nodes 218, 220, 222 and 224 are 6, 5, 5 and 5, respectively. In addition, the numbers of non-zero entries in the columns of the parity check matrix Hi of FIG. 1, which correspond to the variable nodes of FIG. 2, are coincident with their degrees 4, 3, 3, 3, 2, 2, 2 and 2, and the numbers of non-zero entries in the rows of 5 the parity-check matrix Hi of FIG. 1, which correspond to the check nodes of FIG. 2, are coincident with their degrees 6, 5, 5 and 5. In order to represent degree distribution for the nodes of the LDPC code, a ratio of the number of degree-i variable nodes to the total number of variable nodes is defined as fi, and a ratio of the number of degree-j check nodes to the total number of check nodes is 0 defined as gj. For example, for the LDPC code corresponding to FIGs. 1 and 2, f 2 =4/8, f 3 =3/8, f 4 =l/8, and fi=0 for i 2, 3, 4; and gs=3/4, g6=1/4, and gj=0 for jf5, 6. When a length of the LDPC code is defined as N, i.e., the number of columns is defined as N, and when the number of rows is defined as N/2, the density of non-zero entries in the entire parity-check matrix having the above degree distribution is computed as Equation (1). 5 2f 2 N+3f 3 N+4f 4 N 5.25 N -N/2 N In Equation (1), as N increases, the density of 'l's in the parity-check matrix decreases. Generally, as for the LDPC code, since the code length N is inversely proportional 0 to the density of non-zero entries, the LDPC code with a large N has a very low density. The wording 'low-density' in the name of the LDPC code originates from the above-mentioned relationship. Next, with reference to FIG. 3, a description will be made of characteristics of a parity-check matrix of a structured LDPC code to be applied in the present invention. FIG. 3 25 schematically illustrates an LDPC code adopted as the standard technology in DVB-S2, which is one of the European digital broadcasting standards. In FIG. 3, Ni denotes a length of an LDPC codeword, K, provides a length of an information word, and (N-K 1 ) provides a parity length. Further, Mi and q are determined to satisfy q=(N-Kj)/Mi. Preferably, K 1 /Mi should be an integer. For convenience, the parity 0 check matrix of FIG. 3 is called a first parity-check matrix HI. Referring again to FIG. 3, a structure of a parity part, i.e., K 1 h column through (N 1 )1h column, in the parity-check matrix, has a dual diagonal shape. Therefore, as for degree distribution over columns corresponding to the parity part, all columns have a degree '2', except for the last column having a degree '1'. 5 In the parity-check matrix, a structure of an information part, i.e., 0 1h column through -4 3090139_1 (GHMaeOrs) P84002.AU.I (Ki-l)1h column, is made using the following rules. Rule 1: It generates a total of K 1 /Mi column groups by grouping Ki columns corresponding to the information word in the parity-check matrix into multiple groups of Mi columns.. A method for forming columns belonging to each column group follows Rule 2 5 below. Rule 2: It first determines positions of 'l's in each 0 1h column in ith column groups (where i=l,...,K 1 /Mj). When a degree of a 0 th column in each ith column group is denoted by Rm - R 2 ) R(D) D,, if positions of rows with 1 are assumed to be '-0 0 ' 1, , positions R,(")(k=1, 2,.D.) Q ''' i) of rows with 1 are defined as Equation (2), in a jh column (where 0 j=l,2,...,Mj-l) in an ith column group. ,R = {R,() 1 ) + q} mod(N - K 1 ), k=1,2,..., D, i=1,...,Ki 1

/M

1 , j=1,...,M 1 -1.........(2) According to the above rules, it is can be appreciated that degrees of columns 5 belonging to an ith column group are all equal to Di. For a better understanding of a structure of a DVB-S2 LDPC code that stores information on the parity-check matrix according to the above rules, the following detailed example will be described. As a detailed example, for N 1 =30, K 1 =15, M 1 =5 and q=3, three sequences for the information on the position of rows with I (hereafter, these sequences are called "Weight-I 0 Position Sequences" for convenience' sake) for 0 th columns in 3 column groups can be expressed as; R -0, R - 1, R =2, R ' =0, 'R =21 11, R =13, 2,0 2,02,0 R('=0, R =10, R =14. 25 Regarding the weight-I position sequence for 01h columns in each column group, only the corresponding position sequences can be expressed as follows for each column group, for convenience' sake. For example: 0 12 0 0 11 13 0 10 14. -5 3090139_1 (GHMatters) P84002.AU 1 In other words, the ith weight-I position sequence in the ith line sequentially represents the information on the position of rows with 1 for the ith column group. It is possible to generate an LDPC code having the same concept as that of a DVB 5 S2 LDPC code of FIG. 4, by forming a parity-check matrix using the information corresponding to the detailed example, and Rule 1 and Rule 2. It is known that the DVB-S2 LDPC code designed in accordance with Rule I and Rule 2 can be efficiently encoded using the structural shape. A process of performing LDPC encoding using the DVB-S2 based parity-check matrix will be described below by way of 0 example. In the following exemplary description, as a detailed example, a DVB-S2 LDPC code with N 1 =16200, K 1 =10800, M 1 =360 and q=15 undergoes an encoding process. For convenience, information bits having a length Ki are represented as an' parity bits having a length (Ni-Ki) are expressed as (pO,pI,...,PN-K-1). 5 Step 1: An encoder initializes parity bits as follows: Po = PI = ... = PN,-K,-1 = 0 Step 2: The encoder reads information on a row where 1 is located within the first 0 column group of an information word, from the 0 th weight-i position sequence of the stored sequences indicating the parity-check matrix. 02084 1613 1548 1286 1460319642972481 3369345146202622 R =0, R 2 ' =2048, R" =1613, R(4 =1548, R"' =1286, 5 R( =1460, R") = 3196, R") =4297, R(" =2481, R"')=3369, R = 3451, R(' = 4620, R"' 3 = 2622. ,05 1'0 __1' The encoder updates particular parity bits px in accordance with Equation (3) using the read information and the first information bit io. Herein, x means a value of R0k for k = 1,2,...,13. -6 3090139_1 (GHMatters) P84002.AU.1

P

0 o=P A 0, P 2 064 -- P 2064 '50, P 1 3

P

6 ( io, P15 4 8 P 548 o, P 1 286

AP

286

G

0 , P 1 46 0 1460 (0

P

3 1 9 6 P31 96 e o P 4297 - P 4297 ( 'o P 2481 - P 2481 0, -... -......... (3) P3369 P3369 e 10, P3451 = P3451 E o, P4620 P 46 20 (10,

P

2 62 2 - P 262 2 D i0 In Equation (3), p, = p, E 1o can also be expressed as p,<- p, @ i, and E means binary addition. 5 Step 3: The encoder first finds out a value of Equation (4) for the next 359 information bits im, (where m=1, 2, ..., 359) after io. {x +(m mod M 1 )x q}mod(NI - K,), M, = 360, m = 1,2,...,359 ........ (4) 0 In Equation (4), x means a value of R( for k =1,2,...,13. It should be noted that Equation (4) has the same concept as Equation (2). Next, the encoder performs an operation similar to Equation (3) using the value found in Equation (4). That is, the encoder updates P4+(mmodM,)xq)mod(Ni-KI) for im. For example, for m=1, i.e., for ii, the encoder updates parity bits P(x+q)mod(Ni-K,) as defined in 5 Equation (5). PIS = PI 5 )is , P20 99 - P 20 99 ( lI, P 162 8 = P 16 28 (1'1 Pi563 = P 1 5 48 D l, PI301 = P 1 301 ej 1 , P475 = P1475 D i 1 , P3211= P 3 1 9 6 9 li, P 4 3 12 = P 4 3 1 2 e1 1 , P 2496 = P 2 496 e3), . ....... (5) P3384 - P3384 G il, P 3 46 6 = P 3 466 @ l, P4635 = P 46 35 E li, P2637 - P 2637 D il It should be noted that q=1 5 in Equation (5). The encoder performs the above process .0 for m=1, 2, ..., 359, in the same manner as shown above. Step 4: As in Step 2, the encoder reads information of R(K) (k =1 ,2,...,13), the 1s weight-I position sequence, for a 361s information bit 360, and updates particular Px, where x masR(k). h encoder updates P (ioM)q~o( 1 K) by similarly applying means 20. The ed( )xq) mod(NI-K,), m=361,362,...,719 Equation (4) to the next 359 information bits /361, 362, ... , 1719 after i360. 5 Step 5: The encoder repeats Steps 2, 3 and 4 for all groups each having 360 information bits. Step 6: The encoder finally determines parity bits using Equation (6). p, = p @ p,_, i = 1,2,..., N - K, - . ........ (6) -7 30901391 (GHMatten) Pa4002.AU I The parity bits pi of Equation (6) are parity bits that underwent LDPC encoding. As described above, DVB-S2 performs encoding through the process of Step I through Step 6. 5 In order to apply the LDPC code to the actual communication system, the LDPC code should be designed to be suitable for the data rate required in the communication system. Particularly, not only in an adaptive communication system employing a Hybrid Automatic Retransmission Request (HARQ) scheme and an Adaptive Modulation and Coding (AMC) scheme, but also in a communication system supporting various broadcast services, LDPC L0 codes having various codeword lengths are needed to support various data rates according to the system requirements. However, as described above, the LDPC code used in the DVB-S2 system has only two types of codeword lengths due to its limited use, and each type of the LDPC code needs an independent parity-check matrix. For these reasons, there is a long-felt need in the art for a 5 method for supporting various codeword lengths to increase extendibility and flexibility of the system. Particularly, in the DVB-S2 system, transmission of data comprising several hundreds to thousands of bits is needed for transmission of signaling information. However, since only 16200 and 64800 are available for a length of the DVB-S2 LDPC code, it is necessary to support various codeword lengths. .0 In addition, since storing independent parity-check matrix separately for each codeword length of the LDPC code reduces the overall memory efficiency, there is a demand for a scheme capable of efficiently supporting various codeword lengths from the given existing parity-check matrix, without designing a new parity-check matrix. 25 SUMMARY OF THE INVENTION According to an exemplary aspect of the present invention, there is provided a method for a channel encoding in a system using a Low-Density Parity-Check (LDPC) code, the method comprising: dividing information bits into a plurality of bit groups; W0 determining a number of information bits to be shortened; determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a predetermined order; and 5 LDPC encoding shortened information bits. According to another exemplary aspect of the present invention, there is provided an -8 3090139_1 (GHMatters) P84002AUA apparatus for a channel encoding in a system using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: a shortening pattern applier for dividing information bits into a plurality of bit groups, for determining a number of information bits to be shortened, for determining a 5 number of bit groups to be shortened based on the determined number of information bits to be shortened, and for shortening information bits in the determined number of bit groups according to a predetermined order; and an encoder for LDPC encoding shortened information bits. According to still another exemplary aspect of the present invention, there is 10 provided a method for a channel decoding in a system using a Low-Density Parity-Check (LDPC) code, the method comprising: demodulating a received signal; determining position of shortened information bits; and decoding the demodulated signal in consideration of the determined position of 15 shortened information bits, wherein determining position of shortened information bits comprises, dividing information bits into a plurality of bit groups; determining a number of shortened information bits; determining a number of shortened bit groups based on the determined number of !0 information bits to be shortened; and determining the shortened bit groups based on a predetermined order. According to yet another exemplary aspect of the present invention, there is provided an apparatus for a channel decoding in a system using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: 25 a demodulator for demodulating a received signal; a shortening pattern determiner for determining position of shortened information bits; and a decoder for decoding the demodulated signal in consideration of the determined position of shortened information bits, 30 wherein determining position of shortened information bits comprises, dividing information bits into a plurality of bit groups; determining a number of shortened information bits; determining a number of shortened bit groups based on the determined number of information bits to be shortened; and '5 determining the shortened bit groups based on a predetermined order. -9 3090139_1 (GHlMattems) Pa94002.AU. I BRIEF DESCRIPTION OF THE DRAWINGS The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction 5 with the accompanying drawings in which: FIG. I is a diagram illustrating an exemplary parity-check matrix of a length-8 LDPC code; FIG. 2 is a diagram illustrating a Tanner graph for an exemplary parity-check matrix of a length-8 LDPC code; 0 FIG. 3 is a diagram illustrating a schematic structure of a DVB-S2 LDPC code; FIG. 4 is a diagram illustrating an exemplary parity-check matrix of a DVB-S2 LDPC code; FIG. 5 is a block diagram illustrating a structure of a transceiver in a communication system using LDPC codes; 5 FIG. 6 is a flowchart illustrating a process of generating an LDPC code having a different codeword length from a parity-check matrix of a stored LDPC code according to an exemplary embodiment of the present invention; FIG. 7 is a block diagram illustrating a structure of a transmission apparatus using shortened LDPC codes according to an embodiment of the present invention; 0 FIG. 8 is a block diagram illustrating a structure of a transmission apparatus using shortened/punctured LDPC codes according to an exemplary embodiment of the present invention; FIG. 9 is a block diagram illustrating a structure of a reception apparatus using LDPC codes to which shortening is applied, according to an exemplary embodiment of the present 5 invention; FIG. 10 is a block diagram illustrating a structure of a reception apparatus using LDPC codes to which shortening and puncturing are both applied, according to an exemplary embodiment of the present invention; and FIG. I I is a flowchart illustrating a reception operation in a reception apparatus 0 according to an exemplary embodiment of the present invention. Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features and structures. DETAILED DESCRIPTION 5 Preferred exemplary embodiments of the present invention will now be described in detail with reference to the annexed drawings. In the following description, a detailed - 10 3090139.1 (GHMaters) P84002.AU.1 description of known functions and exemplary configurations incorporated herein may have been omitted for clarity and conciseness when their inclusion might obscure appreciation of the invention by a person of ordinary skill in the art. The present invention provides a method for supporting LDPC codes having various 5 codeword lengths using a parity-check matrix of a structured LDPC code of a particular type. In addition, the present invention provides an apparatus for supporting various codeword lengths in a communication system using LDPC codes of a particular type, and a method for controlling the same. Particularly, the present invention provides a method and apparatus for generating an LDPC code using a parity-check matrix of a given LDPC code, the generated 0 LDPC code being shorter in length than the given LDPC code. FIG. 5 is a block diagram illustrating a structure of a transceiver in a communication system using LDPC codes. Referring to FIG. 5, a message u is input to an LDPC encoder 511 in a transmitter 510 before being transmitted to a receiver 530. Then the LDPC encoder 511 encodes the 5 input message u, and outputs the encoded signal to a modulator 513. The modulator 513 modulates the encoded signal, and transmits the modulated signal to the receiver 530 over a wireless channel 520. Then a demodulator 531 in the receiver 530 demodulates the signal transmitted by the transmitter 510, and outputs the demodulated signal to an LDPC decoder 533. Then the LDPC decoder 533 estimates an estimation value u of the message based on 0 the data received through the wireless channel 520. The LDPC encoder 511 generates a parity-check matrix according to a codeword length required by a communication system, using a preset scheme. Particularly, according to the present invention, the LDPC encoder 511 can support various codeword lengths using the LDPC code without the separate need for additional storage information. A detailed operation 5 of the LDPC encoder for supporting various codeword lengths will be described in detail below with reference to FIG. 6. FIG. 6 is a flowchart illustrating an encoding operation of an LDPC encoder according to an exemplary embodiment of the present invention. To be specific, FIG. 6 illustrates a method for generating LDPC codes having different codeword lengths from a 0 parity-check matrix of a previously stored LDPC code. Herein, the method of supporting various codeword lengths uses a shortening technique and a puncturing technique. The term 'shortening technique' as used herein means a method that does not substantially use a specified part of a given particular parity-check matrix. For a better 5 understanding of the shortening technique, a parity-check matrix of the DVB-S2 LDPC code shown in FIG. 3 will be described in detail. - 11 309013_1 (GHMatters) P84002.AU.1 Referring now to the parity-check matrix of the DVB-S2 LDPC code shown in FIG. 3, its total length is N 1 , the leading part corresponds to length-Ki information bits and the rear part corresponds to length-(NI-Ki) parity bits (Po IPi ... , -K, -1). Commonly, the information bits freely have a value of 0 or 1, and the 5 shortening technique limits values of information bits of a particular part which is to be subjected to shortening. For example, shortening N, information bits io through iN, commonly means that io = i =...= iN,-l. In other words, by limiting values for N, information bits io through iN-1, to 0, the shortening technique can obtain the same effect as substantially not using N, leading columns in the parity-check matrix of the DVB-S2 LDPC 0 code shown in FIG. 3. The term 'shortening technique' originates from the above-stated limitation operation. Therefore, applying the shortening herein means considering values of the shortened information bits, as 0. With respect to the shortening technique, when the system is set up, a transmitter and a receiver can share or generate the same position information for the shortened information 5 bits. Therefore, though the transmitter has not transmitted the shortened bits, the receiver performs decoding, knowing that information bits in the positions corresponding to the shortened bits have a value of 0. In the shortening technique, since a length of a codeword that the transmitter actually transmits is NI-N, and a length of an information word is also KI-Ns, the code rate becomes 0 (K - N,) / N, - N,), which is always less than the first given code rate KI/NI. Next, the puncturing technique will be described in detail. Generally, the puncturing technique can be applied to both the information bits and parity bits. Although the puncturing technique and the shortening technique are in common in reducing codeword lengths of codes, the puncturing technique, unlike the shortening technique, described herein above, 25 does not have the concept that limits values of particular bits. The puncturing technique is a method for simply not transmitting particular information bits or a particular part of generated parity bits, so that a receiver can perform erasure processing on the corresponding bits. In other words, by simply not transmitting bits in Np predefined positions in a generated length-Ni LDPC codeword, the puncturing technique can obtain the same effect as 0 transmitting a length-(Ni-Np) LDPC codeword. Since columns corresponding to the bits punctured in the parity-check matrix are all used intact in a decoding process, the puncturing technique is different from the shortening technique. Since, according to the invention position information for the punctured bits can be equally shared or estimated by the transmitter and the receiver when the system is set up, the 5 receiver performs erasure processing on the corresponding punctured bits, before performing - 12 309039_1 (GHMaIters) P84002.AU.1 decoding. In the puncturing technique, since a length of a codeword that the transmitter actually transmits is Ni-N, and a length of an information word is K, constantly, the code rate becomes Ki/(Ni-N.), which is always greater than the first given code rate Ki/NI. 5 A description will now be made of the exemplary shortening technique and the exemplary puncturing technique suitable for the DVB-S2 LDPC code. The DVB-S2 LDPC code, as mentioned above, is a kind of an LDPC code having a particular structure. Therefore, compared with the normal LDPC code, the DVB-S2 LDPC code can undergo more efficient shortening and puncturing. 0 For convenience of this example, assume that a codeword length and an information length of an LDPC code are N 2 and K 2 , respectively that the invention desires to finally obtain from the DVB-S2 LDPC code whose codeword length and information length are Ni and K 1 , respectively, using the shortening technique and the puncturing technique. If Ni-N 2 =

N

4 and K 1 - K2= Kd, it is possible to generate the LDPC code whose codeword length and 5 information length are N 2 and K 2 , respectively, by shortening K 4 bits and puncturing (N 4 -Kd) bits from the parity-check matrix of the DVB-S2 LDPC code. For the generated LDPC code with N 4 >0 or Kd>O, since its code rate K 1

-K/N

1 -Nj is generally different from the code rate Ki/NI of the DVB-S2 LDPC code, its algebraic characteristic changes. For Nd = K 4 ', the LDPC code is generated by applying none of shortening and puncturing or performing only 0 shortening. However, regarding the DVB-S2 LDPC code, as described in Rule 1 and Rule 2, as one R 'k(k = 1,2,..., D,, i =1,..., K, / M, i = 0,...,M, -1) value corresponds to M, columns, a total of KI/Ni column groups each have a structural shape. Therefore, the DVB-S2 LDPC code is equal to an LDPC code that does not use M, columns, if it does not use one Z5 R(k value. The following shortening process is proposed considering such characteristics. In step 601, the LDPC encoder 511 reads column group information of a DVB-S2 LDPC code to be subjected to shortening. That is, the LDPC encoder 511 reads the stored parity-check matrix information. Thereafter, in step 603, the LDPC encoder 511 determines a codeword length N 2 and an information length K2 for a shortened LDPC codeword to transmit 0 actually after shortening. Thereafter, the LDPC encoder 511 performs a shortening process of steps 605 to 611, in which the LDPC encoder 511 performs shortening corresponding to a required information length of an LDPC code, based on the read information of the stored parity-check matrix. Shortening Step 1: The LDPC encoder 511 determines A- 2 in step 605, where Mi - 13 3090139_1 (GHMatters) P84002.AU.1 Lx] means the maximum integer which is less than or equal to x. Shortening Step 2: The LDPC encoder 511 selects a sequence for (A+1) column groups among Rfk(ij, =,...,K, /M,) in step 607, and the selected sequence is defined as S(f (i, =1,..., A +1). The LDPC encoder 511 considers that there is no sequence Rf() for the 5 remaining K;/M-A-1 column groups. Shortening Step 3: The LDPC encoder 511 generates a shortened DVB-S2 LDPC code from the A+1 Sf(k values selected in Shortening Step 2, using Rule 1 and Rule 2 in step 609. It should be noted that the shortened LDPC code has an information length of (A+1)/M1, which is always greater than or equal to K 2 . [0 Shortening Step 4: The LDPC encoder 511 additionally shortens (A+1)/MI-K 2 columns from the shortened LDPC code generated in Shortening Step 3 in step 611. For a description of detailed examples, a detailed description will now be made of a process of generating a new LDPC code whose codeword length is N 2 =4050 and whose information length is K2=1170, by shortening 12150 bits among the information bits using a 5 DVB-S2 LDPC code that has a characteristic of N 1 =16200, K 1 =13320, M 1 =360 and q=9. Example of Shortening Step 1: The LDPC encoder 511 determines A= -1170 = 3. 1360_ Example of Shortening Step 2: The LDPC encoder 511 selects a sequence for 4 column groups among a total of 37 R(' values. In this particular example, the LDPC encoder 511 selects the following sequence. S") = 3, S(2 = 2409, S 1 3 = 499, S( 1 f = 1481, S 1 f 908, S6 559 S(' = 716, S'8 = 1270,S( 9 1 -333, S(0) = 2508 10 1,0 76S 8 127 1, - ' 0 S = 2264, S '12 = 1702, S(" = 2805, S(')=6, S = 2114, S") =842, S3=0, S, =1885, S") =2369, S 7, S -2326, S = 1579. Example of Shortening Step 3: The LDPC encoder 511 generates a shortened DVB S2 LDPC code from the 4 Sffk values selected in Example of Shortening Step 2, using Rule I and Rule 2. For the shortened LDPC code, a length of its information word is 4x360=1440. 25 Example of Shortening Step 4: The LDPC encoder 511 additionally shortens 1440 1170=270 columns from the shortened LDPC code generated in Example of Shortening Step 3. The LDPC encoder 511 performs encoding based on the shortened LDPC code. According to the exemplary embodiment, since sequence information for K1/My-A-1 = 13320/360-4=33 column groups among RQ (i = ],...,K] /M,) values are not used, which -14 3090139_1 (GHMallers) P84002.AU I is equivalent to shortening a total of 33x360=1 1880 bits in the Example of Shortening Step 2. In addition, since the LDPC encoder 511 has additionally shortened 270 information bits through the Example of Shortening Step 3 and the Example of Shortening Step 4, it is finally equivalent to shortening 12150 information bits. Therefore, the result of the embodiment 5 provides a shortened LDPC code with a codeword length N 2 =4050 and an information length

K

2 =1 170. As described above, the present invention can apply an efficient shortening technique that, compared with a bit-by-bit shortening technique which is commonly used for shortening of the DVB-S2 LDPC code, employs a method of not using information on column groups of 0 the DVB-S2 LDPC code depending on the structural features of the DVB-S2 LDPC code. Selection criteria of a sequence for a column group can be summarized as follows in Step 2 in the shortening process of the DVB-S2 LDPC code. Criterion 1: The LDPC encoder 511 selects a shortened LDPC code with a codeword length N 2 and an information length K2, obtained by performing shortening on a DVB-S2 5 LDPC code with a codeword length N, and an information length KI, degree distribution of the selected shortened LDPC code being almost similar to the optimal degree distribution of the normal LDPC code with a codeword length N2 and an information length K 2 . Criterion 2: The LDPC encoder 511 selects a code having the good cycle characteristic on the Tanner graph among the shortened codes selected in Criterion 1. In the 0 present invention, regarding a criterion for a cycle characteristic, the LDPC encoder 511 selects a case where the minimum-length cycles in the Tanner graph is as large as possible and the number of the minimum-length cycles is as small possible. Although the optimal degree distribution of the normal LDPC code can be found out in Criterion 1 using a density evolution analysis method, a detailed description thereof will be !5 omitted since it is irrelevant to the understanding of the present invention. If the number of selections of a weight-i position sequence for the column group is not great, the LDPC encoder 511 may select a weight-I position sequence for the column group having the best performance by fully searching all the cases regardless of Criterion 1 and Criterion 2. However, the selection criteria for column groups, applied in Shortening Step 0 2 of the DVB-S2 LDPC code, can increase its efficiency by selecting an LDPC code satisfying the both conditions when the number of selections of the weight-1 position sequence for the column group is too large. To describe an example of a good sequence obtained by applying the selection criteria of a weight-i position sequence for the column group, a DVB-S2 code with 5 N 1 =16200, K 1 =3240, M 1 =360 and q=36 will be considered. The DVB-S2 LDPC code has the following weight-I position sequence on column groups. -15 3090139_1 (GHMatters) P84002AU I 6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 12557 10691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 11090 10774 3613 5208 111777676354987466583 7239 12265 2674 4292 5 11869 3708 5981 8718 4908 10650 6805 3334 2627 10461 9285 11120 7844 3079 10773 3385 10854 5747 1360 12010 12202 6189 4241 2343 .0 9840 12726 4977 The jth weight-I position sequence in the i1h line sequentially represents the information on the position of rows with I for the ith column group. Therefore, it can be appreciated that the DVB-S2 LDPC code is composed of 9 column groups and its 5 information length is 90360 = 3240. If a codeword length and an information length desired to be obtained by performing shortening are N 2 and K 2 , respectively, it is possible to find out the optimized shortening pattern using Shortening Step 1 through Shortening Step 4. However, when values of N 2 and K 2 required by the system are highly variable, the optimized shortening pattern may have no correlation according to the value of JV 2 . For 0 example, assuming that the optimal selection for a case necessary for shortening 2 column groups from the DVB-S2 LDPC code is not using information on rows with I in 4 th and 8 th column groups, since selecting and shortening 1 ", 5 th and 6 th column groups can also be optimal when selecting 3 column groups, they have no correlation with each other. Therefore, when values of N 2 and K 2 required by the system are highly variable, it is undesirably 25 necessary to store all shortening patterns optimized according to a value of K 2 , for the optimized performance. Thus, if values of N 2 and K 2 required by the system are highly variable, suboptimal shortening patterns can be found using the following method, for system efficiency. First, assume that selection of I column group is needed for shortening. In this case, 0 since the number of selectable column groups is only I in an optimal sense, it is possible to select the highest-performance column group. Next, when there is a need for selection of 2 column groups for shortening, the LDPC encoder 511 selects a column group showing the best performance among the remaining column groups, including the selected 1 column group. In the same manner, when there is a need for selection of i column groups for 5 shortening, the LDPC encoder 511 selects one highest-performance column group among the remaining column groups, including (i-1) column groups selected in the previous step for - 16 3090139.1 (GHMatters) P84002 AU-1 shortening. This method of shortening, though it cannot guarantee the optimal selection, can have stabilized performance from one shortening pattern regardless of a change in the value of K 2 . 5 For a detailed example, when values of N 2 and K 2 required by the system are highly variable, it is possible to find out suboptimal shortening patterns according to N 2 and K 2 , for 9 cases shown in Table 1. Herein, N 2 =Ni-K 2 , since the puncturing technique is not considered. Table 1 Range of K 2 Shortening Method 1) 2880 K 2 < 3240 Shortens 3240-K 2 bits from an information word corresponding to the 8 th sequence 6189 4241 2343 for the 8th column group among the weight-I position sequences. 2) 2520 s K 2 < 2880 Shortens all columns included in the column group, which correspond to the 8 th sequence among the weight-1 position sequences, and additionally shortens 2880-K 2 bits from an information word corresponding to the 4 th sequence 118693708 5981 8718 4908 10650 6805 3334 2627 10461 9285 11120 for the 4th column group. 3) 2160 s K 2 < 2520 Shortens all columns included in the column group, which correspond to the 8th and 4 th sequences among the weight-I position sequences, and additionally shortens 2520-K 2 bits from an information word corresponding to the 7 h sequence 1360 12010 12202 for the 7 h column group. 4) 1800 K 2 < 2160 Shortens all columns included in the column group, which correspond to the 8 th 4 th and 7 th sequences among the weight-1 position sequences, and additionally shortens 2160-K 2 bits from an information word corresponding to the 6 th sequence - 17 30901391 (GHMaters) P84002.AU.1 3385 10854 5747 for the 6th column group. 5) 1440 5 K 2 < 1800 Shortens all columns included in the column group, which correspond to the 8 th ,th 7 th and 6 th sequences among the weight-I position sequences, and additionally shortens 1880-K 2 bits from an information word corresponding to the 3 rd sequence 10774 3613 5208 11177 7676 3549 8746 6583 7239 12265 26744292 for the 3rd column group. 6) 1080 s K 2 < 1440 Shortens all columns included in the column group, which correspond to the 8 th, 41 7th 6t and 3 rd sequences among the weight-i position sequences, and additionally shortens 1440-K 2 bits from an information word corresponding to the 5 th sequence 7844 3079 10773 for the 5th column group. 7) 720 K 2 < 1080 Shortens all columns included in the column group, which correspond to the 8h ,th 7t 6h 3 rd and 5 th sequences among the weight-I position sequences, and additionally shortens 1080-K 2 bits from an information word corresponding to the 2 nd sequence 10691 4988 3859 3734 3071 3494 7687 10313 5964 8069 8296 11090 for the 2 "d column group. 8) 528 s K 2 < 720 Shortens all columns included in the column group, which correspond to the 8 th 4th 7th 6 th 3 rd, 5 th and 2 nd sequences among the weight-l position sequences, and additionally shortens 720-K 2 bits from an information word corresponding to the 9 th sequence 9840 12726 4977 for the 9th column group. However, since 168 BCH parity bits are mapped to a part of the column group, which corresponds to the 9 th sequence, by a DVB-S2 encoding scheme, columns in the positions corresponding to the - 18 30901391 (GHMatters) P84002.AU.1 BCH parity do not undergo shortening. 9) 168 K 2 < 528 Shortens all columns included in the column group, which correspond to the 8 th 4 th 7 th , th 3 rd, 5 th, 2 nd and 9 th sequences among the weight-] position sequences, and additionally shortens 528-K 2 bits from an information word corresponding to the 1S sequence 6295 9626 304 7695 4839 4936 1660 144 11203 5567 6347 12557 for the Ist column group. Herein, K2=168 means the case where only the columns corresponding to the BCH parity remain in the DVB-S2 LDPC code. In other words, there , are no pure information word bits. This is not considered. The shortening order in Table I is determined by, for example, dividing the information word into 9 intervals, and then applying Criterion I and Criterion 2 thereto. Referring to Table 1, it can be appreciated that all columns corresponding to the 8 th 5 4 th 7 th 6 th, 3 rd 5 th 2 nd 9 th and Ist sequences included in the column group sequentially undergo shortening according to the required information length for the LDPC code. That is, a value of 0 is mapped to the information bits that will undergo shortening in order of the columns corresponding to the 8 th 4 h 7 th 6 th 3 rd, 5 th 2 nd, 9 th and Ist rows according to the required information length. Alternatively, it can also be considered that the meaningful 0 information bits, which are not fixed to 0, are sequentially mapped to the columns corresponding to the lSt, 9 th 2 nd, 5 th, 3 rd 6 th 7 th 4 th and 8th sequences according to the information length. The order '8, 4, 7, 6, 3, 5, 2, 9, ' of the columns can also be expressed as '7, 3, 6, 5, 2, 4, 1, 8, 0', by representing the 1 " column as a 0 th block. In Step 8) and Step 9) in Table 1, since the last 168 bits of the 9 th column group, or 15 the last column group, in the part corresponding to information bits of the DVB-S2 LDPC code with N 1 =16200, K 1 =3240, M 1 =360 and q=36 are mapped to Bose-Chaudhuri Hocquenghem (BCH) parity bits, they cannot undergo shortening. Actually, when a DVB-S2 LDPC code with N,=16200 is designed such that 168 BCH parity bits are always included in LDPC information bits having the lengths Ki and K 2 . .0 The shortening order information shown in Table I can also be expressed as Table 2, in brief. Table 2 - 19 30901391 (GHMatters) P84002.AU 1 Major variables of DVB S2jo LDPC code Ni=16200, KI=3240, Mi=360, q=36 S2 LDPC code Range of K 2 Shortening Method 1) 528 ! K 2 < 3240 For an integer m = 3240-K 2 shortens all of m column _ 360 _ groups corresponding to 7E(0)th, 7( 1)h, ..., and cn(m- l)th column groups, and additionally shortens 3240-K 2 -360m information bits from a t(m)th column group. Herein, iT denotes a permutation function meaning a shortening pattern, and a relationship therebetween is shown at the bottom of the table. However, when a part of a nE(7)=8'h column group is shortened, the columns in the positions corresponding to the 168 BCH parity bits are not subjected to shortening. 2) 168 K 2 < 528 Shortens all of n(O)th n(l)th, ..., and nT( 6 )th column groups, and shortens all columns except for the columns in the positions corresponding to 168 BCH parity bits from the 7T( 7 )=8th column group. Further, additionally shortens 528 K2 information bits from a n( 8 )=Oth Column group. I() T(1 7r(2) 7r(3) 7r(4) n() nt(6) 1n(7) n(8) 7 3 6 5 2 4 1 8 0 For a description of another exemplary embodiment, a DVB-S2 code with NI=16200, Ki=7200, Mi=360 and q=25 will be described. The DVB-S2 LDPC code has the following weight-i position sequences. 5 20712238663544061 106250455158 21 2543 5748 4822 2348 3089 6328 5876 22 926 5701 269 3693 2438 3190 3507 23 2802 4520 3577 5324 1091 4667 4449 0 2451402003 1263 4742 6497 11856202 0 4046 6934 1 2855 66 26694212 3 3439 1158 - 20 30901391 (GHMatters) P84002.AU.I 438504422 55924290 6 14674049 7 7820 2242 5 846063080 9 4633 7877 1038846868 1189354996 123028 764 0 13 5988 1057 147411 3450 The ith sequence sequentially represents the information on the position of rows with I for an i'h column group. Therefore, it can be appreciated that the DVB-S2 LDPC code is 5 composed of 20 column groups, and the information length is 20x360=7200. When the codeword length and the information length desired to be obtained by performing shortening are N 2 and K 2 , respectively, it is possible to find out suboptimal shortening patterns as defined in Table 3. 0 Table 3 Major variables of DVB-S2 vablDP co Ni=16200, Ki=7200, Mi=360, q=25 DVB-S2 LDPC code Range of K 2 Shortening Method 1)528 K 2 <7200 For an integer m= 7200-K 2 ], shortens all of m column 360 _' groups corresponding to n( 0 )th 7 t(I)th ..., and nl(m-I)th column groups, and additionally shortens 7200-K 2 -360m information bits from a n(m)th column group. Herein, 71 denotes a permutation function meaning a shortening pattern, and a relationship therebetween is shown at the bottom of the table. However, when a part of a ni(18)=19th column group is shortened, the columns in the positions corresponding to the 168 BCH parity bits are not subjected to shortening. 2) 168 s K 2 < 528 Shortens all of 7E(0) t h, 7t()lh, ..., and n( 1 7 )h column groups, and shortens all columns except for the columns in the positions corresponding to 168 BCH parity bits from the -21 30901391 (GHMatters) P84002 AU.1 7 r(1 8 )=19'h column group. Further, additionally shortens 528

K

2 information bits from a 7T( 19

)=

0 th column group. _ n(0) nr(l) n(2) n(3) 7r(4) n(5) 7c(6) nc(7) n(8) 7r(9) 18 17 16 15 14 13 12 11 4 10 7E(10) n(11) 7T(12) 7t(13) 7E(14) n7(15) 7r(16) (17) nr(18) n(19) 9 8 3 2 7 6 5 1 19 0 In the shortening process, the additional shortening can be more easily implemented if the process is sequentially performed from the rear or the front of the column group where the additional shortening is achieved. 5 After step 611 in FIG. 6, when puncturing is needed, the LDPC encoder 511 applies puncturing in an LDPC encoding process in step 613. The puncturing method will be described below in brief. If a codeword length and an information length of an LDPC code are defined as N2 and K 2 , respectively, then the invention intends to obtain eventually from the DVB-S2 LDPC D code with a codeword length N, and a information length K, using the shortening technique and the puncturing technique, and it is given that NI-N2=N and Ki-K 2 =KA, it is possible to get the LDPC code with a codeword length N 2 and an information length K 2 by shortening KA bits and puncturing (NA-KA) bits from a parity-check matrix of the DVB-S2 LDPC code. Assuming that for convenience' sake, only the parity part is subjected to puncturing, since the 5 parity length is Ni-Ki, there is a method of puncturing 1 bit from the parity part at every (Ni KI)I(NA-KA) bits. However, various other methods can also be applied as the puncturing technique. For NA-KA=0, there is no need to apply the puncturing technique. In this particular case, it is possible to get a high-efficiency shortened DVB-S2 LDPC code by applying a 0 similar generation method for the DVB-S2 LDPC code using the shortening pattern shown in Table 1. Shown in FIG. 7 is a detailed example of a transmission apparatus for implementing a shortening process for the DVB-S2 LDPC code. FIG. 7 is a block diagram illustrating an exemplary structure of a transmission apparatus using shortened LDPC codes according to an 5 embodiment of the present invention. The transmission apparatus includes, for example, a controller 710, a shortening pattern applier 720, an LDPC code's parity-check matrix extractor 740, and an LDPC encoder 760. The LDPC code's parity-check matrix extractor 740 extracts a shortened LDPC code - 22 3090139.1 (GHMatters) P64002.AU.1 parity-check matrix. The LDPC code parity-check matrix can be extracted from a memory, or can be given in the transmission apparatus, or can be generated by the transmission apparatus. The controller 710 controls the shortening pattern applier 720 so that it can determine a shortening pattern according to an information length. The shortening pattern applier 720 5 inserts zero (0)-bits at the positions of shortened bits, or removes columns corresponding to the shortened bits from the parity-check matrix of a given LDPC code. A method of determining the shortening pattern can use a shortening pattern stored in a memory, generate a shortening pattern using a sequence generator (not shown), or use a density evolution analysis algorithm for a parity-check matrix and its given information length. 0 The controller 710 controls the shortening pattern applier 720 so that it can shorten a part of the information bits of the LDPC code in the patterns shown in Table 1 through Table 3. The LDPC encoder 760 performs encoding based on the LDPC code shortened by the controller 710 and the shortening pattern applier 720. 5 FIGs. 8 and 9 are block diagrams illustrating structures of a transmission apparatus and a reception apparatus for a DVB-S2 LDPC code to which shortening and puncturing are both applied, respectively. FIG. 8 is a block diagram illustrating an exemplary structure of a transmission apparatus using shortened/punctured LDPC codes according to an embodiment of the present 0 invention. The transmission apparatus of FIG. 8 further comprises a puncturing pattern applier 880 added to the transmission apparatus of FIG. 7. Referring to FIG. 8, it can be appreciated that shortening is carried out in the front stage of the LDPC encoder 760 and puncturing is performed in the output stage of the LDPC encoder 760. 25 The puncturing pattern applier 880 applies puncturing to the output of the LDPC encoder 760. The method of applying puncturing has been described in detail in step 613 of FIG. 6. FIG. 9 is a block diagram illustrating an exemplary structure of a reception apparatus using LDPC codes to which shortening is applied, according to an embodiment of the present 0 invention. Shown in FIG. 9 is an example of a reception apparatus that receives a signal transmitted from a communication system using the shortened DVB-S2 LDPC code, and restores the data desired by a user from the received signal when a length of the shortened DVB-S2 LDPC code is determined from the received signal. 5 The reception apparatus includes, for example, a controller 910, a shortening pattern decision/estimation unit 920, a demodulator 930, and a LDPC decoder 940. - 23 30901391 (GHMalters) P84002.AU.I The demodulator 930 receives and demodulates a shortened LDPC code, and provides the demodulated signal to the shortening pattern decision/estimation unit 920 and the LDPC decoder 940. The shortening pattern decision/estimation unit 920, under the control of the 5 controller 910, estimates or decides information on a shortening pattern of an LDPC code from the demodulated signal, and provides position information of the shortened bits to the LDPC decoder 940. A method of deciding or estimating a shortening pattern in the shortening pattern decision/estimation unit 920 can use a shortening pattern stored in a memory, or generate a shortening pattern using sequence generator (not shown), or use a 0 density evolution analysis algorithm for a parity-check matrix and its given information length. Since a probability that values of shortened bits will be zero (0) in the LDPC decoder 940 is 1 (or 100%), the controller 910 decides whether it will decode the shortened bits by means of the LDPC decoder 940, using the probability value of 1. 5 The LDPC decoder 940 restores data desired by the user from the received signal when it finds a length of the shortened DVB-S2 LDPC code by means of the shortening pattern decision/estimation unit 920. FIG. 10 is a block diagram illustrating an exemplary structure of a reception apparatus using LDPC codes to which shortening and puncturing are both applied, according 0 to an embodiment of the present invention. In the reception apparatus of FIG. 10, a shortening and puncturing pattern decision/estimation unit 1020 replaces the shortening pattern decision/estimation unit 920 of FIG. 9. When the transmission apparatus applies both shortening and puncturing, the 5 shortening and puncturing pattern decision/estimation unit 1020 in the reception apparatus can first perform pattern decision/estimation on shortening, or can first perform pattern decision/estimation on puncturing, or can simultaneously perform pattern decision/estimation on shortening and pattern decision/estimation on puncturing. The LDPC decoder 940 preferably has information on both shortening and 0 puncturing in order to perform decoding. FIG. I1 is a flowchart illustrating an exemplary reception operation in a reception apparatus according to an embodiment of the present invention. A demodulator 930 receives and demodulates a shortened LDPC code in step 1101. Thereafter, a shortening pattern decision/estimation unit 920 decides or estimates a 5 shortening/puncturing pattern(s) from the demodulated signal in step 1103. The shortening pattern decision/estimation unit 920 determines in step 1105 whether - 24 30901391 (GHMatters) P84002.AU.I there is any shortened/punctured bit. If there is no shortened/punctured bit, a LDPC decoder 940 performs decoding in step 1111. However, if there is shortened/punctured bit(s), a shortening and puncturing pattern decision/estimation unit 1020 provides the position information of the shortened/punctured bits to the LDPC decoder 940 in step 1107. 5 In step 1109, based on the position information of the shortened/punctured bits, the LDPC decoder 940 determines that the probability that values of the shortened bits will be 0 is 1, and determines that the punctured bits are erased bits. Thereafter, the LDPC decoder 940 proceeds to step 1111 where it performs LDPC decoding. As is apparent from the foregoing description, the present invention provides 0 shortening patterns, thus making it possible not to substantially use some columns. In addition, the present invention can generate separate LDPC codes having different codeword lengths using information on a given parity-check matrix in a communication system using LDPC codes. The above-described methods according to the present invention can be realized in 5 hardware or as software or computer code that can be stored in a recording medium such as a CD ROM, an RAM, a floppy disk, a hard disk, or a magneto-optical disk or downloaded over a network, so that the methods described herein can be executed by such software using a general purpose computer, or a special processor or in programmable or dedicated hardware, such as an ASIC or FPGA. As would be understood in the art, the computer, the processor 0 or the programmable hardware include memory components, e.g., RAM, ROM, Flash, etc. that may store or receive software or computer code that when accessed and executed by the computer, processor or hardware implement the processing methods described herein. While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various 5 changes in form and details may be made therein without departing from the spirit and range of the invention as defined by the appended claims. In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive 0 sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. - 25 30901391 (GHMaIters) P84002 AU I

Claims (24)

1. A method for a channel encoding in a system using a Low-Density Parity-Check (LDPC) code, the method comprising: dividing information bits into a plurality of bit groups; determining a number of information bits to be shortened; determining a number of bit groups to be shortened based on the determined number of information bits to be shortened; shortening information bits in the determined number of bit groups according to a predetermined order; and LDPC encoding shortened information bits.

2. The method of claim 1, further comprising: determining a number of information bits to be obtained by shortening for determining the number of information bits to be shortened.

3. The method of claim 1, wherein the predetermined order is 7 th bit group, 3 rd bit group, 6 th bit group, 5 th bit group, 2 nd bit group, 4 th bit group, 1 st bit group, 8 th bit group, Oth bit group, when a codeword length is 16200, and the information bits is 3240.

4. The method of claim 1, wherein the predetermined order is 18 h bit group, 17 h bit group, 16 th bit group, 15th bit group, 14 th bit group, 13th bit group, 12 th bit group, 1 lth bit group, 4 th bit group, 10 th bit group, 9 th bit group, 8 th bit group, 3 rd bit group, 2 nd bit group, 7 th bit group, 6 th bit group, 5 th bit group, 1 st bit group, 19 th bit group, Oth bit group, when a codeword length is 16200, and the information bits is 7200. 5

5. The method of claim 1, comprising: wherein when a number of bits of each bit group is 360 and the information bits is 3240, shortening all information bits in bit groups from 0 th bit group to (m-I1th bit group in 0 the predetermined order; and shortening (3240-K 2 -360m) information bits in mth bit group in the predetermined order, wherein, K 2 is a number of information bits to be obtained by shortening, (3240-K 2 ) 3240 - K2 is the number of information bits to be shortened, and - 360 _ - 26 4075386_2 (GHMatters) P84002.AU.1

6. The method of claim 1, comprising: wherein when a number of bits of each bit group is 360 and the information bits is 7200, shortening all information bits in bit groups from 0 th bit group to (m-1)th bit group in the predetermined order; and shortening (7200-K 2 -360m) information bits in mth bit group in the predetermined order, wherein, K2 is a number of information bits to be obtained by shortening, (7200-K 2 ) 7200 -K2 is the number of information bits to be shortened, and m 3 60 2

7. An apparatus for a channel encoding in a system using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: a shortening pattern applier for dividing information bits into a plurality of bit groups, for determining a number of information bits to be shortened, for determining a number of bit groups to be shortened based on the determined number of information bits to be shortened, and for shortening information bits in the determined number of bit groups according to a predetermined order; and an encoder for LDPC encoding shortened information bits.

8. The apparatus of claim 7, wherein the shortening pattern applier is configured to determine a number of information bits to be obtained by shortening for determining the number of information bits to be shortened. 5

9. The apparatus of claim 7, wherein the predetermined order is 7 th bit group, 3 rd bit group, 6 th bit group, 5 th bit group, d bit group, 4 th bit group, 1st bit group, 8 bit group,th bit group, when a codeword length is 16200, and the information bits is 3240.

10. The apparatus of claim 7, wherein the predetermined order is 18 th bit group, 17 h bit 0 group, 16 th bit group, 15 th bit group, 14 th bit group, 13 th bit group, 12 th bit group, 1 Ith bit group, 4th bit group, 10th bit group, 9th bit group, 8th bit group, 3rd bit group, 2nd bit group, 7th bit group, 6 0 th bit group, 5th bit group, st bit group, 39th bit group, 2 h bit group, when a codeword length is 16200, and the information bits is 7200. 5

11. The apparatus of claim 7, wherein when a number of bits of each bit group is 360 and - 27 4975386.2 (GHMatters) P84002 AU.1 the information bits is 3240, the shortening pattern applier shortens all information bits in bit groups from 0th bit group to (m-i)th bit group in the predetermined order, and shortens (3240 K 2 -360m) information bits in mth bit group in the predetermined order, wherein, K2 is a number of information bits to be obtained by shortening, (3240-K 2 ) 3240 - K2 is the number of information bits to be shortened, and L 360

12. The apparatus of claim 7, wherein when a number of bits of each bit group is 360 and the information bits is 7200, the shortening pattern applier shortens all information bits in bit groups from 0 th bit group to (M-i)th bit group in the predetermined order, and shortens (7200 K 2 -360m) information bits in mth bit group in the predetermined order, wherein, K2 is a number of information bits to be obtained by shortening, (7200-K 2 ) 7200 - K2 is the number of information bits to be shortened, and m = 1 K 2 ]

13. A method for a channel decoding in a system using a Low-Density Parity-Check (LDPC) code, the method comprising: demodulating a received signal; determining position of shortened information bits; and decoding the demodulated signal in consideration of the determined position of shortened information bits, wherein determining position of shortened information bits comprises, dividing information bits into a plurality of bit groups; determining a number of shortened information bits; determining a number of shortened bit groups based on the determined number of information bits to be shortened; and 5 determining the shortened bit groups based on a predetermined order.

14. The method of claim 13, wherein determining position of shortened information bits further comprising: determining a number of information bits to be obtained by shortening for 0 determining the number of information bits to be shortened.

15. The method of claim 13, wherein the predetermined order is 7 th bit group, 3 rd bit group, 6 th bit group, 5 th bit group, 2 nd bit group, 4 th bit group, Ist bit group, 8 th bit group, 0th bit group, when a codeword length is 16200, and the information bits is 3240. -28 497538_2 (GHMatters) P84002.AU.1

16. The method of claim 13, wherein the predetermined order is 18 th bit group, 17 h bit group, 16'h bit group, 15 th bit group, 14 th bit group, 13 th bit group, 12 th bit group, I Ph bit group, 4 th bit group, 10 th bit group, 9 th bit group, 8 th bit group, 3 rd bit group, 2 nd bit group, 7 th bit group, 6 'h bit group, 5 th bit group, Is bit group, 19 th bit group, Oth bit group, when a codeword length is 16200, and the information bits is 7200.

17. The method of claim 13, comprising: wherein when a number of bits of each bit group is 360 and the information bits is 3240, determining that all information bits in bit groups from 0 th bit group to (m-l)th bit group in the predetermined order are shortened; and determining that (3240-K 2 -360m) information bits in mth bit group in the predetermined order are shortened, wherein, K2 is a number of information bits to be obtained by shortening, (3240-K 2 ) m_3240 - K2] is the number of information bits to be shortened, and L 360K_

18. The method of claim 13, comprising: wherein when a number of bits of each bit group is 360 and the information bits is 7200, determining that all information bits in bit groups from 0 th bit group to (m-]lh bit group in the predetermined order are shortened; and determining that (7200-K 2 -360m) information bits in mth bit group in the predetermined order are shortened, 5 wherein, K2 is a number of information bits to be obtained by shortening, (7200-K 2 ) 7200 - K2 is the number of information bits to be shortened, and m = [ 360 K

19. An apparatus for a channel decoding in a system using a Low-Density Parity-Check (LDPC) code, the apparatus comprising: 0 a demodulator for demodulating a received signal; a shortening pattern determiner for determining position of shortened information bits; and a decoder for decoding the demodulated signal in consideration of the determined position of shortened information bits, - 29 4975386_2 (GHMatters) P84002.AU.1 wherein determining position of shortened information bits comprises, dividing information bits into a plurality of bit groups; determining a number of shortened information bits; determining a number of shortened bit groups based on the determined number of information bits to be shortened; and determining the shortened bit groups based on a predetermined order.

20. The apparatus of claim 19, wherein the shortening pattern determiner is configured to determine a number of information bits to be obtained by shortening for determining the number of information bits to be shortened.

21. The apparatus of claim 19, wherein the predetermined order is 7 th bit group, 3 rd bit group, 6 th bit group, 5 th bit group, 2 nd bit group, 4 th bit group, 1 st bit group, 8 th bit group, 0 th bit group, when a codeword length is 16200, and the information bits is 3240.

22. The apparatus of claim 19, wherein the predetermined order is 18 th bit group, 17 th bit group, 16 th bit group, 1 5 th bit group, 14 th bit group, 13 th bit group, 12 th bit group, I Ith bit group, 4 th bit group, 10th bit group, 9th bit group, 8th bit group, 3rd bit group, 2nd bit group, 7th bit group, 6 th bit group, 5 th bit group, 1 st bit group, 19th bit group, 0 th bit group, when a codeword length is 16200, and the information bits is 7200.

23. The apparatus of claim 19, wherein when a number of bits of each bit group is 360 and the information bits is 3240, the shortening pattern determiner determines that all information bits in bit groups from 0 bit group to (MnJ)th bit group in the predetermined 5 order are shortened; and (3240-K 2 -360m) information bits in mth bit group in the predetermined order are shortened, wherein, K 2 is a number of information bits to be obtained by shortening, (3240-K 2 )

3240-K2 is the number of information bits to be shortened, and - 360 _ 0

24. The apparatus of claim 19, wherein when a number of bits of each bit group is 360 and the information bits is 7200, the shortening pattern determiner determines that all information bits in bit groups from 0 th bit group to (M-i)th bit group in the predetermined order are shortened; and 5 (7200-K 2 -360m) information bits in mth bit group in the predetermined order are -30 49753862 (GHMatters) P84002.AU.1 shortened, wherein, K 2 is a number of information bits to be obtained by shortening, (7200-K 2 ) 7200 - K2 is the number of information bits to be shortened, and m 0 2 -31

4975386.2 (GHMatters) P84002.AU.1