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AU518064B2 - Memory control system - Google Patents
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AU518064B2 - Memory control system - Google Patents

Memory control system

Info

Publication number
AU518064B2
AU518064B2 AU42408/78A AU4240878A AU518064B2 AU 518064 B2 AU518064 B2 AU 518064B2 AU 42408/78 A AU42408/78 A AU 42408/78A AU 4240878 A AU4240878 A AU 4240878A AU 518064 B2 AU518064 B2 AU 518064B2
Authority
AU
Australia
Prior art keywords
control system
memory control
memory
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU42408/78A
Other versions
AU4240878A (en
Inventor
R. H. and McAndrew R. T Gruner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EMC Corp
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Priority to AU42408/78A priority Critical patent/AU518064B2/en
Publication of AU4240878A publication Critical patent/AU4240878A/en
Application granted granted Critical
Publication of AU518064B2 publication Critical patent/AU518064B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
AU42408/78A 1978-12-11 1978-12-11 Memory control system Expired AU518064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU42408/78A AU518064B2 (en) 1978-12-11 1978-12-11 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU42408/78A AU518064B2 (en) 1978-12-11 1978-12-11 Memory control system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
AU85118/75A Division AU495342B2 (en) 1975-09-23 Data processing system

Publications (2)

Publication Number Publication Date
AU4240878A AU4240878A (en) 1979-04-05
AU518064B2 true AU518064B2 (en) 1981-09-10

Family

ID=3729628

Family Applications (1)

Application Number Title Priority Date Filing Date
AU42408/78A Expired AU518064B2 (en) 1978-12-11 1978-12-11 Memory control system

Country Status (1)

Country Link
AU (1) AU518064B2 (en)

Also Published As

Publication number Publication date
AU4240878A (en) 1979-04-05

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