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AU585955B2 - Process to obtain thin film lines - Google Patents
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AU585955B2 - Process to obtain thin film lines - Google Patents

Process to obtain thin film lines

Info

Publication number
AU585955B2
AU585955B2 AU54852/86A AU5485286A AU585955B2 AU 585955 B2 AU585955 B2 AU 585955B2 AU 54852/86 A AU54852/86 A AU 54852/86A AU 5485286 A AU5485286 A AU 5485286A AU 585955 B2 AU585955 B2 AU 585955B2
Authority
AU
Australia
Prior art keywords
thin film
obtain thin
film lines
lines
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU54852/86A
Other versions
AU5485286A (en
Inventor
Giampiero Ferraris
Antonio Tersalvi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Telecomunicazioni SpA
Original Assignee
Siemens Telecomunicazioni SpA
Societa Italiana Telecomunicazioni Siemens SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Telecomunicazioni SpA, Societa Italiana Telecomunicazioni Siemens SpA filed Critical Siemens Telecomunicazioni SpA
Publication of AU5485286A publication Critical patent/AU5485286A/en
Application granted granted Critical
Publication of AU585955B2 publication Critical patent/AU585955B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/022—Quinonediazides
    • G03F7/023—Macromolecular quinonediazides; Macromolecular additives, e.g. binders
    • G03F7/0233—Macromolecular quinonediazides; Macromolecular additives, e.g. binders characterised by the polymeric binders or the macromolecular additives other than the macromolecular quinonediazides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0577—Double layer of resist having the same pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0585—Second resist used as mask for selective stripping of first resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Laminated Bodies (AREA)
  • Inorganic Insulating Materials (AREA)
AU54852/86A 1985-05-03 1986-03-14 Process to obtain thin film lines Ceased AU585955B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT20567/85A IT1184535B (en) 1985-05-03 1985-05-03 THIN FILM LINES RECOVERY PROCESS
IT20567-85 1985-05-03

Publications (2)

Publication Number Publication Date
AU5485286A AU5485286A (en) 1986-11-06
AU585955B2 true AU585955B2 (en) 1989-06-29

Family

ID=11168906

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54852/86A Ceased AU585955B2 (en) 1985-05-03 1986-03-14 Process to obtain thin film lines

Country Status (8)

Country Link
US (1) US4812388A (en)
EP (1) EP0200237A3 (en)
JP (1) JPS61255029A (en)
CN (1) CN1006597B (en)
AU (1) AU585955B2 (en)
IT (1) IT1184535B (en)
NO (1) NO861090L (en)
ZA (1) ZA862336B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11501457A (en) * 1995-08-09 1999-02-02 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ Method of manufacturing an apparatus having a base having a conductor pattern of a conductor
NZ555495A (en) * 2002-03-21 2008-07-31 Basf Ag Fungicidal mixtures containing prothioconazole and metrafenone
CN110028670A (en) * 2019-04-11 2019-07-19 明士新材料有限公司 Low-dielectric loss negative light-sensitive poly amic acid ester resin, resin combination, preparation method and application
CN115568118A (en) * 2022-10-20 2023-01-03 Oppo广东移动通信有限公司 Manufacturing method, circuit board, anti-shake assembly and camera module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122619A2 (en) * 1983-04-15 1984-10-24 Polyonics Corporation Composite product having patterned metal layer and process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2428373C2 (en) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Method for the production of solderable connection contacts on a semiconductor arrangement
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4451971A (en) * 1982-08-02 1984-06-05 Fairchild Camera And Instrument Corporation Lift-off wafer processing
JPS59202636A (en) * 1983-05-04 1984-11-16 Hitachi Ltd Formation of fine pattern
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
JPS61242044A (en) * 1985-04-19 1986-10-28 Matsushita Electronics Corp Manufacture of semiconductor device
US4606998A (en) * 1985-04-30 1986-08-19 International Business Machines Corporation Barrierless high-temperature lift-off process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0122619A2 (en) * 1983-04-15 1984-10-24 Polyonics Corporation Composite product having patterned metal layer and process

Also Published As

Publication number Publication date
CN1006597B (en) 1990-01-24
ZA862336B (en) 1986-11-26
CN86102448A (en) 1986-10-29
JPS61255029A (en) 1986-11-12
NO861090L (en) 1986-11-04
EP0200237A3 (en) 1988-09-07
IT1184535B (en) 1987-10-28
EP0200237A2 (en) 1986-11-05
IT8520567A0 (en) 1985-05-03
US4812388A (en) 1989-03-14
AU5485286A (en) 1986-11-06

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