AU610283B2 - An arrangement for deactivating integrated circuits electrically - Google Patents

Description

I~ II i 4 'i -I A6 OPI DATE 02/05/89 AOJP DATE 15/06/89

WORLD

APPLN. ID 25564 88 PCT Nu ,ER PCT/SE88/00493

PCT

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 (11) International Publication Number: WO 89/ 03634 3/32 Al (43) International Publication Date: 20 April 1989 (20.04.89) (21) International Application Number: PCT/SE88/00493 (81) De t tat.T op ]at AU, BE (Eur-n ten uro patent), DE (22) International Filing Date. 23 September 1988 (23.09.88) peal palf, FI ean patent), GB (European patent ,HU (Erpean patent), JP, KP, KR, LU (European patent), NL (European (31) Priority Application Number: 8703913-7 patent), NO, SE (European patent), SU, US.

(32) Priority Date: 9 October 1987 (09.10.87) Published (33) Priority Country: SE With international search report.

(71) Applicant (for all designated States except US): CAR- MIS ENTERPRISES S.A. [CH/CH]; Torello Torello, 1, rue Monnier, CH-1206 Geneve (CH).

(72) Inventor; and Inventor/Applicant (for US only) RIMAN, Alf [SE/ SE]; Akervagen 21, S-352 49 Vaxj (SE).

(74) Agent: OMMING, Allan; A Omming Co AB, Sveavagen 28-30, S-1ll 34 Sto-kholm (SE).

(54) Title: AN ARRANGEMENT FOR DEACTIVATING INTEGRATED CIRCUITS ELECTRICALLY 8 "4 +2 7 L 4 3 (57) Abstract The invention relates to an arrangement for electrically deactivating IC-circiits by means of deactivating capacitors.

A particularly simple and effective electrical deactivation of such circuits is achieved in accordance with the invention by mounting, e.g. gluing, a metal foil on the circuit. The earth connection of the circuit is connected to the edge of the foil through a short conductor and each of the signal output and supply conductor is connected directly to the foil edge through a respective soldered chip capacitor 8).

CARMIS ENTERP I ES S A S. i SFP4 To: The Commissioner of Patents nature of Declarant( 11/81 Mario D Torello WO 89/03634 PCT/SE88/00493 1 An arrangement for deactivating integrated circuits electrically.

The present invention relates to an arrangement for deactivating integrated circuits electrically with the aid of deactivating capacitors connected between earth/signal outputs and/or earth/supply lines.

Troublesome interference occurs when a large number of fast acting integrated circuits, so-called IC-circuits, are connected together to a unit, e.g. a computer or data processor. For example, functioning of the equipment is on the one hand disturbed by surrounding influences, such as other computers, radio receivers, TV-apparatus and, on the other hand, the equipment itself has a disturbing influence on such peripheral apparatus and equipment, thereby producing erroneous results or no result at all. The interference referred to here is an electromagnetic interference (EMI), which may be radiating or conductorbound.

In addition to the problems which are manifested solely as interference, there is also a danger that the equipment will emit signals which can be captured at locations distansed from the equipment itself and utilized to obtain unauthorized or classified information, so-called revealing signals.

All of these problems are well known in the art. Thus, the surroundings can be shielded from these signals, by metalencapsulation of the equipment involved and by filtering the input and output signals. Such metal encapsulation becomes verv exoensive and difficult to effect, however, when the equipment concerned includes displays, visual display screens, keyboards, etc.. Furthermore, encapsula- WO 89/03634 PCT/SE88/00493, 2 tion does not assist against interference internally of the equipment. In order to safeguard against internal interference, it is standard practice to include a capacitor 4btween the supply voltage and earth on a circuit board or card in the case of IC-circuits.

This solution is also encumbered with a number of drawbacks, however. For example, the solution is not particularly effective and does not assist against signals of a revealing nature or EMI. Furthermore, the devices required herefor require too much space in compact equipment.

Other solutions, exhaustively described in the literature, include the use of ferrite filters, ferrite plates, multilayer circuit board and flat caoacitors for fitting above or beneath IC-circuits. A further possibility is that of mounting one or more capacitors in a dense array above an IC-circuit. This solution is also inefficient, however.

None of the known solutions is sufficiently effective or simple enough for efficient application, particularly not to existing equipment.

Consequently, an object of the present invention is to provide a simple, inexpensive and effective solution to the problem of deactivating IC-circuits electrically.

This object is achieved in accordance with the invention by covering at least the major part of the under-surface or over-surface of such an IC-circuit with a metal foil which is connected to the earth connection of the circuit by means of a short conductor extending to the edge of the foil and with the signal outputs and/or the supply conductor of the circuit also connected to the edges of the foil, via the deactivating capacitors. A deactivator of this kind can be easily constructed. The metal foil may, WO 89/03634 PCT/SE88/00493 3 advantageously, be glued to one side of the IC-circuit, level with the edge surfaces thereof, and to this end may be self-adhesive. Connection of the deactivating capacitors then becomes highly practicable and easy to carry out, particularly when one or more of these capacitors consist of chip capacitors soldered between on one hand respective signal outputs or the supply conductor and on the other hand adjacent points on the foil edge.

Deactivation of an integrated circuit in accordance with the invention fulfills all of the criteria upon which effective deactivation depends, such as the presence of short and broad supply conductors so as to obtain a low series inductance, supply-voltage and signal-voltage application surfaces of small dimensions (small areas, short lengths), smallest possible loop area, low capacitor losses and low impeJance of the earthing surface. The effect produced by the present invention can be confirmed in practice, suitably by carrying out comparison tests, as recited in the following description.

The invention will now be described in more detail with reference to the accompanying drawing, which illustrates schematically an exemplifying embodiment of the inventive arrangement and test apparatus with associated result curves. More specifically: Figure 1 is a perspective view of an IC-circuit according to the invention; Figure 2 is a diagrammatic illustration of test apparatus; Figure 3 is a circuit diagram of the tested IC-circuit with connections; and Figures h, 5, 6 and 7 illustrate curves obtained in the tests.

I

WO 89/03634 PCT/SE88/00493 4 In the embodiment illustrated in Figure 1, an IC-circuit in the form of a conventional elongated capsule 1 which has a sheet of copper foil 2 firmly glued to the upper surface thereof. The connecting legs of the capsule are arranged along the two long sides of the capsule, wherewith the leg 3 is earthed and the leg 4 is an output. A voltage supply leg 5 is arranged on the hidden side of the caosule. The earthed leg 3 is connected to the edge of the foil 2 by means of a very short firmly soldered conductor 6, and the output leg 4 is connected to the edge of said foil through a firmly welded clip capacitor 7. The voltage supply leg 5 is connected to the edge of the foil through a further chip capacitor 8.

In the diagrammatic Figure 2 illustration an IC-capsule 1 is located in a screened room 10. The capsule 1 is connected to a signal generator 11. Also located in the screened room is a biconcave-antenna 12, which is connected to an antenna amplifier 13, a spectrum analyser 14 and a printer The IC-circuit 1 illustrated in Figure 3 has marked thereon three points A-E, of which points A and E represent points on a circuit board adjacent the capsule 1 and the points B, C, D are points located directly on the capsule legs.

The following measurements were made with a capacitor of 150 nF coupled between A and E.

1. No additional measures taken, corresponding to the normal situation in a computer e.g. max EMI-level 56 dB (Figure 4) ,1 -;1 WO 89/03634 PCT/SE88/00493 2. 100 nF 4, 7 nF between BoD: max EMI-level 34 dB 47 nF 4, 7 nF between CoD (Figure 3. As 2+ferrite plate (Figure 6) max EMI-level 28 dB 4. Chip capacitor 100 nF between BoD max EMI-level 13 dB Chip capacitor U7 nF between CoD.

and copper foil mounted in accordance with the description (Figure 7).

As will be seen from Figures 4-6 and Figure 7, there is a considerable difference between the conventional arrangements according to 1-3 above and the inventive arrangement represented by 4.

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Claims (3)

1. An arrangement for electrically deactivating integrated circuits by means of deactivating capacitors located between earth/signal outputs and/or earth/supply conduc- tors, characterized in that at least the major part of the upper surface or the bottom surface of such an integrated circuit is covered with metal foil which is con- nected to the earth connection of the circuit by means of a short conductor to the edge of the foil and to the circuit signal outputs and/or supply conductor via the deactivating capacitors 8) which are also connected to the foil edges.

2. An arrangement according to Claim 1, characterized in that one or more of the deactivating capacitors is/are chip capacitors 8) soldered between on the one hand respective signal outputs or supply conductor and on the other hand adjacent points on the foil edge.

3. An arrangement according to Claim 1 or 2, characterized in that the metal foil is glued to one side of the integrated circuit flush with the edges of said side. J