AU615556B2 - Controller and a network controller system - Google Patents

Description

TO: THE COMMISSIONER OF PATENTS

AUSTRALIA,

$f OPI DATE 05/01/90 APPLN. ID 37679 89 pC AOJP D E T/ 9 T MBER PCT/AU89/00239 INTERNATIONAL APPLICA PUJLIJ DU D t"H ENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 (11) International Publication Number: WO 89/12345 HO02J 13/00, G08B 29/00 Al G08C 25/02, H02H 7/22 (43) International Publication Date: 14 December 1989 (14.12.89) (21) International Application Number: PCT/AU89/00239 (74)Agent: EICHBERGER, Helmut; G.R. Cullen Co., 79 Eagle Street, Brisbane, QLD 4000 (AU).

(22) International Filing Date: 1 June 1989 (01.06.89) (81) Designated States: AT, AT (European patent), AU, BB, BE Priority data: (European patent), BF (OAPI patent), BG, BJ (OAPI PI 8697 8 June 1988 (08.06.88) AU patent), BR, CF (OAPI patent), CG (OAPI patent), CH, CH (European patent), CM (OAPI patent), DE, DE (European patent), DK, FI, FR (European patent), GA (71) Applicant (for all designated States except US): THE SOUTH (OAPI patent), GB, GB (European patent), HU, IT (Eu- EAST QUEENSLAND ELECTRICITY BOARD [AU/ ropean patent), JP, KP, KR, LK, LU, LU (European pa- AU]; 150 Charlotte Street, Brisbane, QLD 4000 tent), MC, MG, ML (OAPI patent), MR (OAPI patent), MW, NL, NL (European patent), NO, RO, SD, SE, SE (72) Inventors; and (European patent), SN (OAPI patent), SU, TD (OAPI Inventors/Applicants (for US only) COOMER, Ronald, patent), TG (OAPI patent), US.

James [AU/AU]; 8 Jude Street, Brackenridge, QLD 4017 O'NEILL, Alan, Martin [AU/AU]; 7 Johnstone Street, Sherwood, QLD 4075 DI MARCO, Ray- Published mond, Raffael [AU/AU]; 24 Raglass Street, Everton With international search report.

Park, QLD 4053 ROE, Anthony, Morris [AU/ AU]; 3 Kernow Street, Robertson, QLD 4019 (AU).

(54) Title: CONTROLLER AND A NETWORK CONTROLLER SYSTEM (57) Abstract A controller for protection and monitoring of devices networked in a distribution system. The controller includes an input or pilot bus enabling communication from and to the controller, a plurality of analog signal inputs (5-18) for receiving signals representative of conditions of the device being monitored and diagnostic circuitry (63) for periodically simulating desired conditions of the device, a plurality of programmable outputs (26-36) for providing control signals for controlling the device output diagnostic circuitry (67) for enabling one programmable output to control the device, a plurality of monitoring inputs (37-41) for receiving signals indicative of the state of the device, a plurality of alarm inputs (42-50), alarm diagnostic circuitry a modulator/demodulator (64) and a computer (50) for controlling the controller.

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i iii i: 'I WO 89/12345 PCT/AU89/00239 1 "CONTROLLER AND A NETWORK CONTROLLER SYSTEM" THE INVENTION relates to a controller for protection and monitoring of circuit breakers, transformers capacitor banks and other devices of a power distribution system and to a network controller system including a plurality of controllers.

The invention will be described by way of example with reference to its application and use with circuit breakers but it should be appreciated that it is applicable to other devices normally part of a power distribution network.

Distribution systems currently employ a variety of protection devices and systems.

One earlier proposal consisted of a protective relay distribution protection relay designed for use in distribution substations for the protection of a radial feeder. The relay operated from secondary current transformers and ,ircuit breaker auxiliary contacts and included a microprocessor for providing overcurrent protection, ground overcurrent protection, multi-shot reclosing demand and peak recording ammeters, accumulation of breaker interrupting duty, self-checking and facilities for communications for remote terminal connection.

This proposal had a display and various data could be called up for observation by means of a keypad. Access could also be gained via a communication port. The proposal was marketed by Brown Boveri and is typical of similar i WO 89/12345 PCT/AU89/00239 2 controllers marketed by other companies. These controllers i i were essentially dedicated in situ controllers and were unsuitable for networking in a controller system where a f

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plurality of devices at various substations or locations needed to be monitored or controlled from a remote location.

It is an object of the present invention to provide a controller for protection and monitoring of devices capable of being networked and a controller system including a plurality of networked controllers. f According to one aspect of the invention there is provided a controller for protection and monitoring of devices capable of being networked in a distribution system, said controller including an input data or pilot bus enabling communication from and to the controller, a plurality of analog signal inputs for receiving signals representative of conditions of the device being monitored and diagnostic circuitry associated with said analog signal inputs for L: periodically simulating desired conditions of the device for I checking the function of said analog inputs, a plurality of i programmable outputs for providing control signals for controlling operation of the device, output diagnostic circuitry for testing and enabling said programmable outputs Ij I to control the device, a plurality of monitoring inputs for i receiving signals indicative of the state of the device, a plurality of digital alarm inputs and alarm input diagnostic circuitry for checking the integrity of the signals supplied V 3 to the alarm inputs, a modulator and demodulator for transmitting signals onto the pilot bus at a low impedance and for receiving signals from the pilot bus terminals at a high impedance and a computer programmed to control the function of the controller including control of reception by and transmission of signals by the demodulator and modulator respectively, said computer including memory, memory address and decoders and input/output ports.

According to another aspect of the invention there 10 is provided a network controller system including one or more controllers like that described above located at substations of the system, each said controller being associated with a device the operation of which is controlled and monitored by .0: the associated said controller, each said controller being coupled to a common pilot bus, a group controller coupled to the pilot bus and having a computer for controlling the operation of the controllers at the substations.

The modulator/demodulator may form part of a local i area network (LAN) and comprise a hybrid circuit including isolation between the modulator/demodulator and the pilot bus terminals. The isolation may be provided by a transformer.

The hybrid circuit may include an amplifier and a winding of 1 *i-ha na fn-rm cp m w An +-HaI f 1rmra i Ir -F 4 -P4 WO 89/12345 PCT/AU89/00239 4 diode bridge for. each input whereby a bias can be impressed on the bridge to simulate the presence of an analog signal at the input.

The alarm or binary input diagnostics includes comparison means for comparing the alarm or digital inputs with the actual outputs supplied by the programmable outputs.

The comparison may be made by registers such as shift registers.

The programmable output enabling diagnostics may include circuitry controlled by the computer for enabling or checking the programmable output signals at a desired time.

The outputs may be provided by controllable relays which are rendered operable in response to a control signal from the computer.

The analog inputs are coupled to an ADC converter which provides a data stream representative of each of the signals at the analog inputs. Filtering or other processing of the analog signals may be carried out prior to the ADC conversion. This filtering may be part of the diagnostics for these inputs.

The alarm inputs may include debounce circuitry.

Similarly the monitoring inputs may also have debounce or I signal conditioning circuits associated with them.

The invention will now be described by way of example with reference to the drawings in which:- Figure 1 is a block diagram of a system hierarchyi

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1l~a fI WO 89/12345 PCT/AU89/00239 according to an embodiment of the invention; Figure 2 is a block diagram of a controller employed in the system of Figure 1; Figure 3 is a detailed circuit diagram of part of the controller of Figure 2; and Figure 4 is a detailed circuit diagram of a further part of the controller of Figure 2.

An explanation is necessary in relation to the reference numerals and notations used in Figures 3 and 4.

For the sake of simplicity there has been repetition of numerals and notations in these Figures although the devices and parts do not correspond. For example notation ul is employed in Figure 3 and in one other Figure. Device ul in 7 Figure 3 does not correspond with device ul in the other Figures. These comments need to be taken into account when studying the Figures.

Also, Figure 3 has been drawn on two sheets for the sake of clarity. Part of connector J1 is shown in each of the two sheets which together comprise Figure 3. Figure 4 also appears on two sheets.

In Figure 4 the connector J3 enables coupling of the circuit of that Figure to the circuit of Figure 3 via connector J1 in Figure 3.

Figure 4 (cont.) illustrates a display circuit coupled via connector J1 to the circuit of Figure 4.

Connector J1 is not connector J1 of Figure 3 rather the Ia 6 notation has simply been repeated as previously discussed.

In Figure 4 reset line from J3 is coupled to pin 43 of Jl in Figure 4 (cont.). Various data buses from the circuit of Figure 4 are coupled to the connector Jl in Figure 4 (cont.).

A typical system hierarchy is shown in Figure 1.

The system 10 has a plurality of distribution substations 11, 12 and a zone substation 13 all of which are associated with a pilot or data bus 14 onto which and from which information may be supplied or obtained.

Each substation 11, 12, 13 has associated with it devices such as circuit breakers, transformers, capacitor banks or the like the function and control of which need to be maintained or monitored. Substation 11 is shown having a circuit breaker 15, substation 12 has circuit breakers 16 and 17 whilst substation 13 is shown having a circuit breaker 18, a transformer 19 and a capacitor bank The devices present at each substation 11, 12, 13 are coupled to respective controllers 25 to 30 as shown. The controllers 25 to 30 are all coupled to the pilot bus 14 which in this case is a two wire bus.

Substation 13 has a group controller 31 similar in cnnnt-"iin(i-nn r' r a 1 R 4s r i i i 1 i v WO89/12345 PCT/AU89/00239 7 enables the computer to be either caused to operate remotely or to convey information to a remote location. The function of controller 31 may also be implemented by having a local area network (LAN) coupled between computer 32 and bus 14.

In this way controller 31 need not be used and computer 32 assumes its function with the LAN providing for communication with and to the bus.

A typical controller is illustrated in block form in Figure 2. The controller has various input and output terminals including: pilot or data bus 1,2 seven current (or voltage) inputs 5,6 7,8 9,10 11,12 13,14 15,16 17,18 programmable outputs 26 to 36.

field supply 21 -various control outputs 37, 38 and 39 Spower supply input 22 to logic inputs 42 to status inputs 40,41 Terminals 5 to 18 provide the analog interface to the controller whilst terminals 21 to 50 are substation DC interface terminals. The contron ll o I-l i I -Am WO 89/12345 PCT/AU89/00239 8 and control switches 52. As shown diagrammatically, the board 50 may also have a "watch dog" circuit 53 with a unit healthy LED 54 and an alarm LED 55. The controller has seven analog inputs (terminals 5 to 18) which couple analog inputs to measuring/filtering elements 56 to 62. Elements 56 to 62 make the analog inputs available to an analog to digital converter (ADC) 63. The ADC 63 makes digital information available to the microprocessor in board 50. The ADC also includes analog input diagnostic circuitry which enables periodic checking of the integrity of the analog input measuring and filtering elements 56 to 62.

An FSK modem 64 is interfaced between board 50 and terminals 1,2 to which the pilot bus 14 is coupled.

Terminals 42 to 50 enable monitoring of local conditions or components of the device being controlled/monitored. These terminals couple the inputs to a digital input subsystem with diagnostics and debounce circuit Circuit 65 is coupled to board 50. Terminals 26 to 36 provide programmable outputs useful in providing remote switching or indications to remote devices at the substation containing the device being controlled/monitored by the controller of the invention. f Terminals 23,24,25,37,38,39,40,41 provide for i.

i circuit breaker but it should be appreciated that it may be configured for use with a device such as a capacitor bank, transformer or other device. Terminals 40 and 41 are used to monitor whether the circuit breaker is open or closed. Terminals 37 and 38 are close and trip outputs respectively, terminal 39 provides a second trip output and terminals 25,24 and 23 are three supply terminals either separate or the same voltage supply. Terminal 21 is the field supply terminal and I terminal 22 is the negative supply terminal.

Circuit 65 receives inputs from terminals 42 to as well as from terminals 23,24,25 and 38 to 41. For the sake of clarity the connections for terminals 40,41 have been shown and the connections for terminals 23,24,25,38,39 have been omitted.

A power supply, in this case a switched mode power supply 66 for supplying 24-140V is shown. This supply 66 is coupled between the negative and positive supply and is operative over a wide range of input voltages to provide a floating steady 24 volt output and a 5 volt output.

The controller of Figure 2 also has a digital output subsystem with diagnostics circuit 67 coupled between board 50 and relay coils K1 to K7. The coils are controlled i by circuit 67. The contacts associated with the coils are illustrated in this Figure.

With reference to Figure 3 details of various parts .3 1 k. WO 89/12345 PCT/AU89/00239 of the controller of Figure 2 are shown. The remainder of the controller is illustrated in detail in Figure 4.

In Figure 3 the block headed 7X C.T. inputs provides elements 56 to 62 (see Figure 2) while integrated circuits ull, u13, u14, u17 and u20 together with associated circuit components provide the analog to digital converter and diagnostics 63. While block 7X C.T. is shown configured for current inputs it may readily be modified for receiving voltage inputs. Only one circuit of the seven, namely the circuit coupled to transformer T3, is shown in the block. All other circuits in that block are identical to the one shown. The circuit includes diode bridge D2,D4,D1 and D3. These diodes are matched with each other and with diodes D29,D30. Capacitor C2 is optional and improves small signal low frequency response of the bridge. Resistor R1 is a load resistor whilst resistor R2 and capacitor C1 provide a low pass filter. The output from this filter is applied to one input of input multiplexer u16.

A bias signal is supplied to the bridge via amplifier u20 and transistor Q7. This bias is equal to the sum of two diode voltage drops and is applied to the anodes of D2 and D4. This bias is derived from diodes D29,D30 coupled to amplifier u20. In the diagnostic mode a high 4i m. *c m l T T n WO 89/12345 89/12345 PCT/AU89/00239 11 of D2,D4 than two diode junction drops and thus an output is supplied to pin 1 of multiplexer u16. The remaining 6 circuits of the 7X CT block function in a like fashion to that described and the diagnostics of each of these circuits is also as mentioned.

The ADC is provided by ull (a 12 bit binary counter) u16 (a multiplexer ,ich receives inputs from the 7X CT block) u17 (a multiplexer like u16) and weighing resistors P2 and R91 to R95, summing amplifier u18 and two 8 bit analog to digital converter circuits u13,u14. The counter ull alternately addresses circuits u13,u14 to enable A to D conversions to be carried out. The counter ull addresses multiplexers u16 and u17 to ensure that the desired input to u16 appears at output pin 3 and that the multiplexer u17 elects the desired weighing resistor for the proper gain for amplifier u18. The output from amplifier u18 is converted to digital information by u13 and u14. The digital output derived from u13 and u14 a supplied to shift register u2. Shift register u2 forms part of the block 65 in Figure 2.

As shown in Figure 3 the block 65 of Figure 2 includes terminals 42 to 50. These terminals provide inputs to be supplied to shift register u2 as well as to u3. The input circuitry falls into three distinct types. Interposed between terminals 23,24,25 and registers u2,u3 are identical circuits including Diodes D33, D34, R15, R16, R21 and r@

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z uL LtaLing and enabling said programmable outputs to control the device, a plurality of monitoring inputs 40, 41 for receiving signals indicative of the state of the device, a plurality of digital alarm inputs 42-50 and alarm input I4 -*li WO 89/12345 PCT/AU89/00239 12 t capacitor C15. Low pass filter (R21 plus C15) functions as a ms debounce circuit. When terminal 24 is high so is the output supplied by the debounce circuit.

Terminals 42 to 50 (the alarm inputs) all have identical circuitry interposed between them and registers u2,u3. This circuitry includes (for terminal 50) diode D39, and resistors R50, R25, R24 and capacitor C18. Resistor R24 and capacitor C18 function as a debounce circuit. Whenever terminals 42 to 50 are high a high input is supplied to the registers u2,u3.

Terminals 37 to 41 have a different circuit interposed between them and registers u2,u3. Terminal 41 has diode D48, resistor R59, D49, resistor R43, resistor R42 and capacitor C27, where R42 and C27 provide a debounce circuit. Resistor R59 is coupled to +24 volts via resistor R82 and when circuit terminals 38 to 40 are open, a high output is supplied to the register u3. When the terminals go low, a low output is supplied to register u3.

The block 65 includes two multiplexers u6,u7 which derive inputs from serial outputs of 8 stage shift/store register u8. The control inputs to multiplexers u6,u7 receive signals from register u8. In this way shift registers u2,u3 may be loaded with the status of the terminals 37 to 50 or the output of multiplexers u6,u7 via register u8 for input self-diagnostic purposes and upon receipt of signals from the pilot bus.

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j WO 89/12345 r'I r/AIilO/nnaQl WO 89/12345 PCT/AU89/00239 13 The block 67 of Figure 2 and relays K1 to K7 are shown in greater detail in Figure 3 and include shift register u4 with its outputs coupled to the relays by respective diodes D70 to D76, 8 stage shift/store register u9 with its outputs coupled via open collector transistors u5 to the relays as well as transistors Q5,Q6 and associated components. Register u4 is able to receive data from register u3 and output the status of the relays to the computer via pin 3 and connector J1. Register u9 derives an i.,put from the computer (Fi._re 4) via line TXS from J1 and provides an input to u8 and receives an enable signal from the computer. Diodes D70 to D76 enable register u4 to monitor the state of the relays K1 to K7 whilst open collector transistors u5 in Figure 3 enable u9 to control the state of the relays in response to signal TXS derived from the computer.

Transistors Q5,Q6 are such that when Q5 is off Q6 is also off and the relays are connected across 5 volts and cannot function to change the state of the associated contacts. When a signal (high logic level) is applied to the base of Q5 from u9 (via J1) it switches +24V to the cathode oZ diode D58. Thus, the relays have 24 volts applied to them and may then, in response to open collector transistors be energized.

Thus, input diagnostics is provided by u8 whilst output diagnostics is provided by monitoring the state of the

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l (57) Abstract A controller for protection and monitoring of devices networked in a distribution system, The controller includes an input or pilot bus enabling communication from and to the controller, a plurality of analog signal inputs (5-18) for receiving signals representative of conditions of the device being monitored and diagnostic circuitry (63) for periodically simulating desired conditions of the device, a plurality of programmable outputs (26-36) for providing control signals for controlling the device output di- Sagnostic circuitry (67) for enabling one programmable output to control the device, a plurality of monitoring inputs (37-41) for receiv;ng signals indicative of the state of the device, a plurality of alarm inputs (42-50), alarm diagnostic circuitry a modulator/demodulator (64) and a computer (50) for controlling the controller.

WO 89/12345 PCT/AU89/00239 14 relays and only enabling a change in the relays to occur by having the computer provide a diagnostic function and a signal to the bPse of A strobe ST signal from J1 provides a latch signal to registers u2,u3,u4 as well as to u8,u9,ull13,u3,u14 and latches data into the registers such that a word consisting of the diagnostic signals from u8, the relay states from u4, input data from registers u2,u3 and analog information from the CT inputs and the ADC appear as a serial stream at pin 3 of u4 and are supplied to the computer via terminal block Ji.

Periodically internal diagnostics are generated and a signal supplied to Q5 via line OE or to U5 to enable the state of low drivers u5 anE. high driver u6 to be tested without changing the state of the relays. Control for the relays may be achieved internally via the computer or by information supplied to the pilot bus and demodulated and applied to RXA1 on J1 so that the computer may generate appropriate control signals for the relays.

The computer periodically generates signal at TXA1 which is modulated by modulator ul0 and applied to the pilot bus.

Jl provides clock signal CKS for u2,u3,u4,u8,u9 and thos signal is inverted (by inverter u12) and supplied to ull as well as the ADC u13,u14.

The connector J1 also provides clock pulses CKA1 for modulator ul0 and data TXA1 for that modulator. An i 4 1 1 1 was marketed by Brown Boveri and is typical of similar WO89/12345 PCT/AU89/00239 enable signal RTSA1 is also supplied to u10 from Ji. Power supplies at +5 and -5 volts are available at Ji.

Transformer T8 is coupled to pilot lines or data bus 1 and 2 and forms part of a local area network (LAN).

The LAN includes a DC bias resistor R101 which sets the bias for amplifier u20 and a high frequency bypass capacitor Zener diode Z3 ensures that the output of amplifier u20 is at a desired level and also forms part of the LAN as does the capacitive divider C47 and C46. The LAN is a hybrid circuit and functions as a high impedance device when in the listening mode and as low impedance device when in the transmit mode. When in the listening mode 5 volts applied to both inputs of amplifier u20 and thus the secondary of T8 sees effectively an open circuit. Signals appearing on bus 1 and 2 appear at the output of u20 via the transformer T8 and are amplified by u20, level controlled by Z3 and divided by C47/C46 and made availahle as an input to the FSK demodulator ul9. u19 has a data rate of 9600 bits/sec.

The LAN when in the transmit mode receives FSK data from the junction between R102/R103. This signal is amplified by u20 and applied to the secondary of T8 in the feedback path of the amplifier. The transformer action of T8 provides a low impedance in the transmission of signals onto WO 89/12345 PCT/AU89/00239 16 the presence of data from line TXA1 from J1) provides a high frequency signal for low data bits and a low frequency signal for high data bits. Typically, these frequencies are 38.4 KHZ and 25.6 KHZ respectively. Modulator ul0 is typically a CD4018 presettable divide-by-N counter by National Semiconductor. The clock pulses for u10 are supplied from J1 on line CKA1. Circuits u10 and u15 in Figure 3 also function to introduce a phase lag in the data stream when switching between a high frequency signal to a low frequency and a phase lead when switching between low frequency signal and a high frequency signal. This aids in compensating for group delay on the pilot bus.

Demodulator u19 is an FSK demodulator which receives its input at pin 2, u19 is typically an FSK demodulator/tone decoder XR2211 and provides its output at pin 6. This output is inverted by inverter u12 and supplied to line RXA1 of J1. Figure 3 shows a switched mode power supply coupled to a negative terminal 22 and via diodes to terminals 23,24 and Figure 4 shows CPU u5 and associated memory, memory address, expansion bus modem connector and a watch dog circuit. Connector J1 of Figure 3 is coupled to connector J3 of Figure 4.

The watch dog circuit includes timer u8, latch u7, LED D2 and associated components. The NAND gate coupled to pin 12 of u8 receives two signals R and S3. Signal S3 is i I The analog signal inputs may either be signal inputs for current or voltage.

The analog signal input diagnostics may include a

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Ii fll f? 1 r-i i I: I~ Ilr~ r -~I1-I iii WO 89/12345 PCTr/AU89/00239 I I 17 periodically supplied by CPU u5 generated by software.

Normally both R and S3 are high logic levels. This causes t±mer u8 to run for a period of time set by coupling a selected output Q4, Q9 or Q14 of u8 to the inverter shown.

If the counter is not periodically reset by a change in state in signal S3 the output from the inverter triggers latch u7 and ensures that LED D2 is turned off. This indicates that there has been a CPU malfunction. LED D1 is an alarm LED and indicates that an alarm condition is present on the device controlled by the controller. The watch dog circuit is manually reset by operation of reset Si. Normally, with the circuit as shown capacitor C13 is charged and when S1 is depressed C13 discharges through transistor Qi. This causes Q1 to switch and provide a low signal to reset the latch and reset the timer u8. The link coupled to pins, 7, 13, 3 of u8 is used to preselect the time out period for the timer. A reset time of approximately two minutes has been chosen.

The CPU u5 provides the various signals required at or receives signals from terminal block J3. The RS232 port J2 is connected to the CPU via an RS232 buffer u12. Circuit u9 (an ICL7660) is employed to provide a -5 volt supply voltage for various parts of the controller. Pull up resistors are coupled to various outputs of u5 these may be 4.7K ohm resistors for pins 4, 6 to 11 and 54 of u5 and 100K ohm for pins 26, 62, 63 and 41 as indicated in Figure 4.

Device u4 consisting of two separate chips is tf *i: r Si 'i ii ft ~r I Figure 1 is a block diagram of a system hierarchy

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WO89/12345 PCT/AU89/00239 18 decoder/memory address for ROM ul, RAM/ROM u2 and RAM u3.

Capacitor Cl is a storage capacitor which provides memory back-up in case of power failure. This capacitor may be coupled selectively to any one of the memories by bridged selected ones of the links shown in the Figure. Capacitor C4 is a filter capacitor whilst diode D3 is used for level limiting. The links shown associated with the memory devices enable reconfiguration for alternative types of memory devices. The bridging shown pertains to the arrangement illustrated.

Various buses are coupled to the connector J1 of Fjjure 4 (cont.). These are bus DO to D7, REF, WR, RD and AO to A17 and DREQ1, TEND1 WAIT BUSACK BUS REQ RESET and INTO to INT 2.

Device u6 is a negative logic decoder whilst ull is an octal latch.

Figure 4 (cont.) is a view of a display circuit having an LCD 2 line X16 character display LI. This display is linked to the CPU via lines Al, S2, AO and bus DO-7.

Supply is applied as shown. The LCD display L1 is also coupled via buffers u8 and debounce network to switches S1 to S4. These switches are identified as switches 52 in Figure 2. The debounce network consists of resistors R1 to R8 and four 47nF capacitors. Device ul in this figure is an additional address decoder for extra memory and is coupled to the CPU. Device u2 to u7 is an expansion connector for extra memory which may be used if desired.

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Claims (22)

1. A controller for protection and monitoring of devices capable of being networked in a distribution system, said controller including input data or pilot bus enabling communication from and to the controller, a plurality of analog signal inputs 5-18 for receiving signals representative of conditions of the device being monitored and diagnostic circuitry associated with said analog signal inputs for periodically simulating desired conditions of the device for checking the function of said analog inputs, a plurality of programmable outputs 26-36 for providing control signals for controlling operation of the device, output diagnostic circuitry for testing and enabling said programmable outputs to control the device, a plurality of monitoring inputs 40, 41 for receiving signals indicative of the state of the device, a plurality of digital alarm inputs 42-50 and alarm input diagnostic circuitry for checking the integrity of the signals supplied to the alarm inputs, a modulator ul0 Fig.3d and demodulator u19 Fig.3d for transmitting signals onto the pilot bus at a low impedance and for receiving signals from the pilot bus at a high impedance and a computer programmed to control the function of the controller including control of reception by and transmission of signals by the demodulator and modulator respectively, said computer including memory, memory address and decoders and input/output ports.

2. The controller of Claim 1 wherein said modulator and demodulator are part of a local area network with a hybrid circuit including isolation between the modulator and f i;;liX i i iB

3- I~ WO 89/12345 PC/AU89/00239 demodulator and the pilot bus. 3. The controller of Claim 2 wherein the modulator/demodulator is an FSK modulator/demodulator.

4. The controller of Claims 2 or 3 wherein the isolation is provided by a transformer.

The controller of Claim 4 wherein the transformer is part of the hybrid circuit and said hybrid circuit includes an amplifier having a winding of the transformer in its feedback path.

6. The controller of Claim 2 wherein said modulator/demodulator provides a high frequency signal for low data bits and a low frequency signal for high data bits of a data signal being transmitted.

7. The controller of Claim 5 including a bias resistor in series with the winding.

8. The controller of Claim 7 including a high frequency bypass capacitor in parallel with the bias resistor and a zener diode coupled across the amplifier with a capacitive divider network in parallel with the diode whereby said hybrid circuit functions as a high impedance device when in a listening mode and as a low impedance device when in a i transmit mode. h

9. The controller of any one of Claims 1 to 8 wherein each said analog signal input includes a current transformer and a diode bridge coupled to a secondary winding thereof.

The controller of Claim 9 including an amplifier The controller of Figure 2 has been configured for use with a i j i r I::i i I- i B'i if it:. -I iY .v r r~' 7 p i YEir;~ WO 89/12345 PCr/AU89/00239 for selectively applying a bias signal to said diode bridges to simulate the presence of an analog signal.

11. The controller of any one of Claims 1 to 10 wherein the alarm input diagnostic circuitry includes comparison means for comparing alarm inputs with said programmable outputs.

12. The controller of Claim 11 wherein said comparison means comprises one or more shift registers.

13 The controller of any one of Claims 1 to 12 wherein said programmable output testing and enabling diagnostics is controlled by the coir. ter for enabling or checking the programmable output sig.. .s at selected time periods.

14. The controller of any one of Claims 1 to 13 including controllable relays contiolled by the programmable outputs for controlling the device.

The controller of Claim 10 including an analog to digital converter (ADC converter) for providing a data stream representative of each said analog signal.

16. The controller of Claim 15 including a filter coupled between each said diode bridge and the ADC converter for processing each said analog signal prior to conversion in the ADC converter.

17. The controller of Claim 12 including debounce circuitry coupled between the alarm inputs and the shift registers.

18. The controller of Claim 1 wherein said computer i I_ A i F' With reference to Figure 3 details of various parts 3 i ljl e I~ Fl C~T-i. rr ~PI~ I-ll I -R It .I WO 89/12345 PCT/AU89/00239 22 includes a memory and memory address.

19. The controller of Claim 1 including a watch dog timer with a connecter, a latch circuit responsive to a timer output and indicators coupled to the latch whereby in the absence of the connecter being periodically reset said indicators provide a signal indicative of computer malfunction.

The controller of Claim 1 including a display circuit controlled by the computer.

21. A network controller system including one or more controllers according to any one of Claims 1 to 20 located at substations of the system, each said controller being associated with a device the operation of which is controlled and monitored by the associated said controller, each said controller being coupled to a common pilot bus, a group controller coupled to the pilot bus and having a computer for controlling the operation of the controllers at the substations.

22. The network of Claim 21 including a modem coupled to the group controller computer enabling the group controller to either be controlled remotely or to convey information to a remote location. I I I t I~ri i