AU616506B2

AU616506B2 - Digital modulator

Info

Publication number: AU616506B2
Application number: AU33297/89A
Authority: AU
Inventors: Arnoul Octaff Gabriel Vanwelsenaers
Original assignee: Alcatel NV
Current assignee: Alcatel Lucent NV
Priority date: 1988-05-06
Filing date: 1989-04-24
Publication date: 1991-10-31
Anticipated expiration: 2009-04-24
Also published as: BE1001969A6; AU3329789A; FI892082A7; FI892082A0; FI892082L

Description

j i 616506 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENIION ENTITLED a a "DIGITAL MODULATOR" The following statement is a full description of this invention, including the best method of performing it known to us:- Tnis invention relates to a digital modulator including a digital frequency synthesizer providing a modulated output signal whose output frequency is a function of the clock frequency of a clock signal and a digital frequency value of a modulating input signal.

Such a digital modulator is already known from the article "New Universal All-Digital CEA Iodulator" by A. Kopta et al, published in IE Transactions on Coimnunications, Vol. COM-35, No 4, April 1987, pp 45B-462.

In this known digital modulator the digital frequency synthesizer is a so-called number controlled oscillator which is controlled by the abovementioned digital frequency value and provides a modulated output signal whose frequency is equal to the clock frequency multiplied by a factor which is smaller than half of unity.

0 Because the presently available number controlled oscillators operate at a clock frequency of e.g. 30 YMz tb; known modulator is not suit-,2ole for being used in a system operating at a much higher frequency, such as a cellular mobile radio system having a frequency range of e.g. 890.2 to 9114.8 MUz.

I C If one would neverthelesP, like to use this known modulator to provide an output signal whose frequency is very much higher than the clock fre- *:2b quency by which it is controlled, it would be possible to mix in a frequency mixer the output signal of this modulator with a carrier wave having t a higher frequency, thereafter removing by suitable filter means all unwanted frequency signals. If the output signal should have a selectable carrier frequency, such as in a cellular mobile radio system, it would be necessary to make use of a frequency synthesizer able to generate a range of such carrier waves. However, in this case the filter means would have to be different for each of the selected carrier frequencies and to be very selective since they have to filter out unwanted frequencies belonging to the range of frequencies generated by the frequency synthesizer.

This possible solution is therefore not acceptable.

An object of the present invention is to provide a digital modulator of the above type, but which is able to provide a modulated output signal which has a selectable frequency equal to a fractional multiple larger than 1 of the clock frequency and does not require the use of a frequency mixer nor of filter means whtich are a function of the selected frequency.

According to the invention this object is achieved by using a digital frequency synthesizer of the type which performs a fractional multiplication of said clock frequency, said output frequency being equal to the product of said clock frequency and factor equal to the sum of an integer value and a term constituted by the sum of a first fractional part of unity and a second fractional part of unity which is said digital frequency value.

t In this way the digital frequency synthesizer with fractional multi- *rt quency value in the same way as the first fractional part off unity normally used to realise a fractional multiplication and therefore provides an output signal which is modulated by this digital frequency value. In other itElwords, the invention is based on the insight a digital frequency synthesizer with fractional multiplication ma be used as a modulator by processing the modulating input signal in the same way as the first fractional part of unity by which the clock frequency is normally multiplied.

It should be noted that a digital frequency synthesizer with fractional multiplication is well known in the art, e.g. from the book "Frequency Synthesizers Theory and De-sign" by V. Nanassewitsch, Second Edition, John Wiley and Sons and more particularly from pp 43-4l8 thereof, as well as from the book "Fnase-Locked Loops Theory, esign and Applications" by R.F.

Best, McGraw Hill, 1984 and more particularly from pp 222-229 thereof.

However, none of these known frequeno-y synthesizers is used as a modulator.

The abovementioned and other objects and features of the invention will becom'e more apparent and the invention itself will be best understood 3 by referring to the following description of an embodiment taken in conjunction with the accompanying drawing which shows a digital frequency modulator according to the invention.

This digital frequency modulator includes a digital frequency synthesizer with fractional multiplication of the same type as the one shown and described in the last mentioned book. Indeed, it has a clock input CLI and a signal output SO and includes a phase-locked loop, an accumulator ACC, a digital-to-analog converter DAC and registers REG1 and REG2.

The phase locked loop comprises a forward path which includes the cascade connection between CLI and SO of a phase detector PD, an adder circuit S, a lowpass filter LF and a voltage controlled oscillator VCO. The feedback 0o° path of this loop includes the cascade connection between SO and an input of the phase detector PD of a cycle removing circuit CRC and of a divider S* circuit DIV to which the output DIV of register REG1 is connected.

4 The accumulator ACC has a carry output connected to an input of the adder circuit S through the converter DAC as well as four inputs each, except the first, comprising in reality a set of parallel terminals a first S one connected to the clock input CLI, a second one connected to the accu- S mulator carry output, a third one connected to the output F of the register 2 0 REG2, and a fourth one SI to which a modulating input signal equal to a fractional part of unity M and having a positive or negative value is ap- S plied. The accumulator ACC also has a number of control outputs Sl to S3 S which are connected to the cycle removing circuit CRC.

The above modulator is for instance adapted to be used in a cellular mobile radio system to frequency modulate a carrier wave having one of the fequencies spaced apart by 200 kHz and defined by fl 890.2 0.2(p-1) MHz (1) with 1 p 124. (2) This frequency range is used for transmission between the mobile unit and the base unit, whilst for the tranmission in the reverse direction the I4 frequency range is from 935.2 to 959.8 MHz. To this end Gaussian M~inimum Shift Keying is used. A clock signal having a frequency of ff2 =3.25 M4Hz is applied to the clock input CLI, whilst modulating digital frequency samples M are supplied to the signal input SI. Each of the digital f'requency values f2.M is coded in a 6-bit code of which one bit represents the sign and 5 bits represent the magnitude comprised between 0 and 200 kllz. This means that the magnitude of the algebraic variable f2.M is expressed in units, say m, having a frequency value equal tc 200 =6.25 kllz (3) Oe 0 so 0 0 0 *t 00:00 *O 0 a0 0 To be noted that the modulating digital frequency samples are for instance obtained from an input bitstream, in a manner similar to the one described in the abovementioned article. This happens by using each set of the last three bits of this bitstream as an address for one of 8 possible frequency paths stored in a Read-Only-Memory (ROM) and by then reading 12 stored digital samples of the thus selected frequency path.

Whlen expressing the abovementioned carrier frequency ff1 as a fractional multiple of the clock frequency ff2, i.e. as the product of f2 and a factor equal to the sum of an integer N and an adjustable fractional part of unity F, one may write the following relationship if f2.F is expressed in, say f, of the same units, equal to 6.25 kflz, as the above algebraic magnitude 14 fl f f2 (N F) (14) withF f 520 and f varying between 0 and 519 because ff2 =3.25 MHz 520 x 6.25 kllz For instance, the carrier wave frequencies ff1= 890.8 may be written as fcollows: 890.8 MHz =3.25 (2714 48) MHz (6) Miz and ff1 897 MHz (7) 897 MHz 3.25 (276 0) MHz (8) 520 Because the modulating input signal M is also expressed in m units of 6.25 kHz it is equal to M m (9) 520 with m for instance varying between -31 and 31.

Hence, M is able to vary over a range which is a fraction of the range over which F may vary.

As described in the last mentioned book, when an integer value N and the fractional part of unity F are applied to the inputs DIV and F of the frequency synthesizer respectively, the latter provides at its outputs SO a carrier wave having a frequency fl whose mean value is given by the relation Thereby the accumulator ACC operates the cycle removing cir- Q* t" C cult CRC via a control signal depending on the integer value of the *t 1t accumulated arithmetic sum in such a way that it removes one cycle, each time this value is equal to one. The accumulator then also applies the carry value, i.e. the accumulated sum minus 1, to its first input.

4't r The accumulator ACC used here differs from the known one in that it t has an additional input SI which is fully equivalent to the input F but to which the algebraic fractional part of unity M is applied and in that it is able to accumulate the algebraic sum F M and to generate distinct control signals S1/3 each for a different integer value of this sum.

Because the accumulator AC processes the term F M in the same way as the value F in the known frequency synthesizer, the modulated output signal provided at the output SO of this synthesizer has a frequency whose mean value is given by the relation f f2 (N F M) This means that the carrier frequency fl f2 (N F) is modulated by the signal f2.M.

With the above given fractional values of F and M the integer value of the algebraic sum accumulated in the accumulator ACC is comprised between -1 and +2.

Indeed, when for instance the previous accumulated value Al =519 and F+ M =504+ 31 =535 then the new accumulated value A2 =Al+ F +M 1054 =2 34, 520 520 when Al 0and F+ M =535 then A2=1 00 10 when Al 0 a ago0 520 000 9D a and F 31 then A2= 31 00 0 520 520 to when Ali=-519 and F+ M =-31 00 00 520 520 0 then A2=-550 -1 0:0 shul order that the frequency synthesizer should operate correctly it 0 00 houldrealise a division by N-1, N, N+1 and N+2 when the integer value of 0~0 the accumulated algebraic sum is equal to 0, 1 and 2 respectively. The accumulator ACC could control the circuit CRC in such a way that the latter: 0 0~ removes 0, 1 or 2 cycles of the output signal of the WCO when the integer value is equal to 0, 1 and 2 respectively; adds 1 cycle when this integer value is equal to -1.

But such a circuit CRC should then be able not only to remove one or two cycles but also to add one cycle Since this is not possible the divider circuit DIV is controlled by the value N-1, instead of N, stored in the register REGi. Then, to realise the abovementioned division by N-1, N, N+l, or N+2 a corresoonding number of 0, 7 i I 1, 2 or 3 cycles or pulses have to be removed. To this end the control signals Sl, S2 and S3 generated by ACC to indicate that the integer value of the accumulated algebraic sum is equal to 1 or 2 are used to control the cycle removing circuit CRC in such a way that the latter removes a corresponding number of 1, 2 or 3 cycles or pulses.

In general, when the integer value of the sum accumulated in ACC can take one of the values -q to n then the divider DIV realises a division by N-q and the accumulator ACC provides control signals indicating that 1 to q+n cycles have to be removed from the 7CO output signal.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on Sthe scope of the invention.

9 9 a U A U o v 1 91 4

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Claims

2. A digital modulator as claimed in claim I, wherein said first fractional part and the absolute value of said second fractional part are each larger than or equal to S zero and smaller than 1. S,3. A digital modulator as claimed in claim 2, wherein said second fractional part of unity has a range of variation which is a fraction of that of said first fractional part of unity.
4. A digital modulator as claimed in claim I, wherein said digital frequency synthesizer includes an accumulator which is controlled by said clock signal, calcu- lates the accumulated algebraic value of said term and provides at least one first control signal which is function of the integer part of said accumulated value, as well as a phase-locked loop whose forward path is controlled by said clock signal and in- cludes the cascade connection of at least a phase detector and a controlled oscillator providing said output signal and the feedback path of which includes the cascade connection of at least a cycle removing circuit able to remove cycles from said output signal and a divider circuit, said cycle removing circuit being controlled by said first i 25 control signal and said divider circuit being controlled by a second control signal which is a function of said integer value. A, digital modulator as claimed in claim 2 or claim 4, wherein said accumulator has first and second inputs for said first and second fractional parts and is provided with a number of outputs which are activated for distinct values of said integer part of said accumulated algebraic value. DATED THIS FOURTEENTH DAY OF AUGUST, 1991 ALCATEL N.V.