AU618399B2 - Integrated logic device for controlling functions in a pcm branch exchange - Google Patents

Description

h. FC 0 03 5 A~j~z'f BY: Signature of Applicant To: The Commissioner of Patents 618399 Sees *5

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COMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED '!INTEGRATED LOGIC DEVICE FOR CONTROLLING FUNCTIONS IN A PCM BRANCH EXCHANGE" The following statement is a full description of this inven-rtion, including the best method of performing it known to us:- .6

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5* 5 S S* 5* Signature of Declarant To: The Commissioner of Patents.

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This invention is directed to the technical field of electronic apparatus for telephone operator stations, and relates to an integrated logic device for controlling the functions of a PCM branch exchange, which device comprises a known microprocessor associated with memory means and with service functions concerning the control of the branch exchange itself.

As it is known, in the field of electronic apparatus for telephone operator station branch exchanges, it is very important that control circuitry architecture be very simple in structure, in order to avoid circuit malfunctions and minimise costs.

i0 Now, in case of a PCM branch exchange, the control circuitry is mainly e used for providing the central (control) unit with determined services associated with particular functions.

Such functions are those related to PCM, in which it is necessary to ee establish channel switching, clock generation, tone generation and auxiliary functions, such as channel control, measuring of various levels as well as functionality tests and user conference installations.

At present, in PCM branch exchanges, these functions are realised by means of separate circuits, each carrying out one of the above refer'ed functions. Such circuits are of a commercial type and there is no device covering the entire range of above referred functions by a suitable combination thereof.

CC C In more detail, it is pointed out that there are commercial integrated circuits for carrying out some of the above mentioned functions, and there are other integrated circuits of a dedicated type, which carry out part of these functions; but there is no device incorporating, in an integrated form, all those functions related to the control system of a PCM technique branch exchange.

Moreover, this limitation causes a speed limitation of the control system, as well as a high cost and a lower reliability as compared with an embodiment incorporating the whole range of the above referred functions.

2 0IC ALT ATENT ,F I 01iS 1 1 14 The basic idea for solving such problems, is to integrate the whole range of service functions, related to PCM system control, in a single multifunction circuit, and to use time division techniques in order to optimise the service operating times of the circuit itself.

It is an object of the invention to eliminate, through the exploitation of such measures, the above mentioned drawbacks connected with the devices at present in use by providing an integrated logic device for controlling the functions of a PCM branch exchange in which all the circuitry relevant to the control functions of a PCM branch exchange has been integrated in such a way as to increase the integration degree. It is a further object of the present invention to reduce the manufacturing costs, as well as to increase the speed of the control circuitry service of the 0* device itself.

According to the invention, there is provided an integrated logic device for controlling the functions of a PCM branch exchange, comprising a microprocessor, connected to memory means and to circuit means relative to service functions concerning the control of the said branch exchange, wherein said memory means comprises an external memory functionally struc- I tured as a plurality of pages, each associated with a particular function, said memory being electrically connected to said circuit means which consist of a single circuit in which there are integrated a circuit for gener- S ating clock signals relative to PCM system frame, a non-blocking circuit for PCM system switching of one hundred and sixty channels subdivided into five links at a bitrate of 2 Mbits/s, a circuit for controlling the signalling channels between peripheral channels and the real control unit, a circuit for providing four simultaneous conferences of three users each, a circuit for PCM system tone generation, a circuit for signal peak level measurement, and auxiliary circuits for testing said integrated circuits, the whole being controlled by said microprocessor which allows the simul- 3 ,r~ 4'

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taneous handling of said integrated circuits by subdividing the external memory as a resource, by means of time division techniques.

In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to a drawing showing a schematic block diagram of the device according to the inventor.

Referring to the figure of the drawing, the section of the block diagram concerning the device, according to the present invention, is designed as a whole by the reference numeral 1 and delimited by a broken line.

The reference numeral 2 indicates the clock generation function associated to the PCM frame, 3 represents the PCM switching function, 4 represents the signalling channels control function, 5 represents the conference circuits running function, 6 stands for the system tones generator; 7 represents the peak level measure of each signal used for diagnostic purposes; 8 stands for an auxiliary test circuit, circuitally connected with all the former circuits, the function of which is to ascertain the operability of said circuits and 9 indicates a memory located outside the aforesaid circuit and consists of a plurality of pages, each associated with the circuit functions related to the supervision of switching and PCM frame clocks.

Device 1 has as an external control unit (CPU) in the form of a microprocessor 10 and a data input-output gate 11 (10 buffer), which is used for the input of the incoming data and the clocks, as well as for the output of transmission and reception signals. From a manufacturing point of view, the integrated logic circuitry of the device according to the invention has been embodied as a single large scale integrated (LSI) circuit. This circuit is of the gate array kind, i.e. a multi-gate circuit and, in the present embodiment, it is designed with sixty-eight pins, a number which can be considered as very limited.

In operation, circuit 2 generating clocks related to PCM frame, generates four types of clock signals from a 8 KHz up to a frequency of 4.096 MHz.

Circuit 3 associated with PCM switching is a circuit used for running the five 2 Mbit/sec, PCM system links of 32 channels each, and which consists of a non-blocking digital matrix circuit based on a time division programmed logic.

In this function are used three of the pages in which memory 9 is subdivided that are the following: i the S.B. area (speech buffer); Se the D.B. area (CPU buffer); the M.B. area (map buffer).

The S.B. area associated with each voice channel a memory location containing the PCM byte arrived in the last receiving frame.

Furthermore, under the control of the memory portion related to the M.B. area, each of the aforesaid bytes may be inserted in a specific output channel.

Finally with the C.B. area it is possible to load some values in the output signalling channels, stored in this area by microprocessor 20 Memory 9 is preferably commercially available low cost random access memory (RAM).

@0 In this way, the interfacing of microprocessor 10 with the memory 9 is controlled in a manner faster than commercial devices presently in use, allowing a large reduction of utilisation time of microprocessor 10, due to a high memory access frequency.

Such memory access is of the parallel type and is performed in i single cycle using a pre-assigned time interval, unlike other devices of commercial kind where the access is controlled during several cycles and, in particular solutions, also in a serial form.

r- J( i 1 1 i. I 1 As to circuitry related to signalling channel control, it provides the possibility for the microprocessor to read the incoming data present on said channels, and to associate the expected signalling data on output desired channels, in appropriate and provided locations.

The tone generation circuitry may supervise four simultaneous conferences of three users each, and it uses four reception and three transmission channels. The fourth reception channel is used to receive the conference tone to be distributed together with the speech.

The tone generating circuitry may generate twelve different tones through the use of six memory areas in memory 9, each one consisting of 512 bytes. From the operating point of view, the above referred services, access to microprocessor included, are supervised at repetitive intervals of 3.9 microseconds, a period of time equal to a time slot duration in the PCM frame.

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*r S *9 5 o• o •2o For this purpose, the time slot interval has been subdivided into forty equal portions, ten portions of which being dedicated to the direct access of microprocessor 10 into memory 9, whereas the remaining thirty portions have been used for handling the above referred services.

In conclusion, the device according to the present invention achieves the intended objects. In fact, the control circuitry of the PCM branch exchange is more compact, having been manufactured with a higher degree of integration involving much lower costs, since it is a device embodied on a single chip. The device of the present invention allows an optimisation of microprocessor access times into the memory, since the operating frequency has been increased. Moreover, it is possible to handle simultaneously all the mentioned function circuits, by distributing appropriately the external resource formed by outside memory 9, and using to this end the time division technique.

6 iiJi It is evident that the use of circuits and/or equivalent protocols, even if structurally different, as well as practical modifications, do not depart from the scope of the present invention.

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Claims (3)

1. An integrated logic device for controlling the functions of a PCM branch ex- change comprising a microprocessor connected to memory means and to circuit means relative to service functions concerning the control of the said branch ex- change, wherein said memory means comprises an external memory designed as a plurality of pages each associated with a particular function, said memory being electrically connected to said circuit means which consist of a single circuit inll which there are integrated a plurality of circuit blocks including a clock circuit for generat- ing clock signals related to PCM systen frame, a non-blocking circuit for PCM sys- tem switching of one hundred and sixty channels subdivided into five links at a bitrate of 2 Mbits/s, ea;h link having 32 channcls, a channel control circuit for con- trolling the signalling channcs bletwccn peripheral cha anls and the microprocessor, a conference circuit for providing four sitmulta,' ous conferences of three users each, a tone circuit for PCM system tone generation, a circuit for signal peak level imeas- urement, and auxiliary circuits for testing said circuit blocks, the whole being con- i trolled by said microprocessor which allows the simultaneous operation of the circuit blocks by subdividing the external memory by means of time division technique.

2. An integrated logic device as claimed in claim 1, wherein said external memory comprises a RAM subdivided into dlist inct buffers. 20

3. An integrated logic clevice substantially as herein described with reference to the figure of the drawing. DATED THIS THIRD DAY OF OCTOBER 1991 ALCATEL N.V. 1