AU627096B2

AU627096B2 - Receiver for a digital additional signal in a digital transmission system

Info

Publication number: AU627096B2
Application number: AU68154/90A
Authority: AU
Inventors: Gerhard Thanhaeuser
Original assignee: Siemens AG; Siemens Corp
Current assignee: Siemens AG
Priority date: 1989-12-18
Filing date: 1990-12-17
Publication date: 1992-08-13
Anticipated expiration: 2010-12-17
Also published as: EP0433707B1; DE59009063D1; ATE122516T1; EP0433707A2; EP0433707A3; AU6815490A

Abstract

According to a prior patent application, the digital user data signal is transmitted in CMI code and, when the code is generated, a binary signal content of the auxiliary signal is allocated to one of the element combinations excluded according to the CMI code rule. Since only the start of a one bit or zero bit of the auxiliary signal is marked, pulses which severely impede the generation of a clock signal occur at the receiving end at comparatively large intervals only. According to a parallel application, a clock pulse pattern is therefore transmitted with sporadic data pulses. The described receiver is able to generate a new clock signal from the clock pulse pattern without the jointly transmitted data pulses being able to cause phase interference. The entire arrangement can be set up fully integrated in CMOS technology. <IMAGE>

Description

-i ai~pjlaiuui1-"T iU1 i-iIu LU Iin paragrapil L ut LII Declaration was/were the first application(s) made in a Convention country in respect of the invention the subject of the application.

Declared at Sydney this 17 day of Septenrrer 1990 Signat re of Declarant(s) SFP4 To: The Commissioner of Patents ti 11/81 i i r II

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FORM FORM S F Ref: 140787 COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION

(ORIGINAL)

FOR OFFICE USE: Class Int Class oa0 00 0 o 000 oo o o e0 a 0000'0 Q 0 m 0 r a-oa Complete Specification Lodged: Accepted: Published: Priority: Related Art: Name and Address of Applicant: Siemens Aktiengesellschaft Wittelsbacherplatz 2 D-8000 Munich 2 FEDERAL REPUBLIC OF GERMANY j eo o 6000 0 a o 0440 o* 0 0 o 0 a 0 a K 1* Address for Service: Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Complete Specification for the invention entitled: Receiver for a Digital Additional Signal in a Digital Transmission System The following statement is a full description best method of performing it known to me/us of this invention, including the

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r 5845/7 .II~ I~ i l;e I c.: 1 89 P 2023 DE Siemens Aktiengesellschaft Receiver for a digital additiional signal in a digital transmission system The invention relates to a receiver for a digital additional signal with comparatively low bit rate which is transmitted together with a digital wanted signal in one channel of a digital transmission system.

Additional signals, by means of which an operating telephone channel or a telemetry channel can be o 10 transmitted parallel to the wanted signals, are i frequently provided in analog and digital transmission systems.

Thus, a transmission system for digital signals with a high modulation rate is known from DE-Al-3,330,68- 15 3, in which a signal of comparatively low modulation rate is also transmitted additionally. In the line terminals this known transmission system contains code converters which convert the digital wanted signal to be transmitted into a link code at the transmitting end and convert it 20 back at the receiving end. For this purpose, in the code converter at the transmitting end the clock signal required is generated by means of a phase-locking loop, and for transmitting the additional signal the control voltage of the phase-locking loop can additionally be amplitude-modulated and hence the clock signal and the transmission signal can be phase-modulated. At the receiving end the phase discrir.nator contained in the phase-locking loop for the clock generation also acts as a demodulator for the additional signals.

As a result of the limited transmission capacity owing to a limited phase-angle deviation permitted, a method described in German Patent Application P 39 39 640.1 was developed in which the digital wanted signal is transmitted in CMI code, and in the generation of which at least one of the element combinations forbidden according to the CMI code rule is assigned a binary signal content.

In order to disturb the transmission of the wanted signal i iii i i -i i

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as little as possible, in this ,Llethod only the beginning of a one-bit or of a zero-bit of the additional signal is marked. In this way comparatively very short data pulses, in comparison with the bit duration, are produced at the receiving end, from which a clock signal can be generated only with great difficulty.

In a parallel application, an improved method for transmitting a digital additional signal is described, in which the digital additional signal and an associated clock signal are combined to form a combined signal, the bit rate of which corresponds to that of the digital additional signal. A comparatively short clock pulse in comparison wit"-h the bit period is generated thereby at the beginning of each bit of the combined signal and, at 15 fixed time intervals from this, in each case one data pulse is generated whenever a bit with algiven logical level begins in the digital additional signal. It is possible here to select whether the beginning of a onebit or the beginning of a zero-bit in the combined signal is to be marked in this way. While the clock pulse is transmitted directly at the beginning of each bit of the additional signal with a short duration in comparison with the interval between adjacent clock and data pulses, a data pulse of approximately equal length follows after 25 the clock pulse at a time interval of approximately 1/4 bit period. The clock pulses and the data pulses are transmitted by means of code rule infringements of the digital wanted signal. The comparatively short duration of the clock pulses and of the data pulses results here from the necessity of producing no overlapping of clock and data pulses even in the case of pulses with jitter.

Full-bit wide digital signals corresponding to tihe original additional reignal and an associated clock signal mnust be generated here again at the receiving end.

The object of the present invention is to develop a receiver of the type mentioned at the beginning which can generate at the receiving end i,,,in a digital additional signal with associated clock signal from the error signals,,. which correspond to the combined signal of 8000 00ff 4 I8 Of 0 0f 0 0 0 8 a Of 0 04 o 0 o 800 f~1O* 4 S3- clock and data signal, output by a code rule violation tester si Luated at the receiving end.

In accordance with the present invention there is disclosed a receiver for a digital additional signal with a comparatively low bit rate which is transmitted together with a digital wanted signal in one channel of a digital transmission system such that the digital additional signal and an associated clock signal are combined to form a combined signal, the bit rate of the combined signal corresponding to that of the signal to be transmitted additionally, and a comparatively short clock pulse in comparison with the bit period is generated at the beginning of each bit of the combined signal and, at fixed time intervals from this, a likewise short data pulse is generated whenever optionally either a one-bit or a zero-bit occurs in the digital additional signal; wherein the combined signal is also inserted into a transmission or link code during the code conversion of the binary wanted signal, and al the receiving end at least one error pulse is generated by a code rule violation tester for each code rule violation detected, and is output to Sa receiver input of said receiver; wherein the clock inputs of a first and of a third D-type flip-flop acr, connected to the receiver input; the clock input of a second D-type flip-flop is connected to the h non-inverting output of the first D-type flip-flop; the data inputs of the first, of the second and of tile third D-type 5 flip-flop are connected to a terminal asserting a potential corresponding to the logical high level; the inverting output of the second D-type flip-flop is connected via a first resistor to the plus input of an operational amplifier and via a first capacitor to a reference potential; ec tile output of the operational amplifier is connected via a second capacitor to the minus input of the operational mplifier, the minus input being connected to tie centre tap of a' voltage divider formed from a second and a third resistor; the output of the operational amplifier is connected to the control input of a voltage-controlled oscillator either directly or via a fourth resistor; IAD/ o0 0 i Tt.

3A 1 the output of this oscillator is connected to the clock inputs of a first binary counter and of a second binary counter; the enable input of the first binary counter is connected to the inverting output of the first D-type flip-flop; the enable input of the second binary counter is connected to the reference potential; the output of the first binary counter is connected via a first inverter to the reset input of the first D-type flip-flop; the output of the second binary counter is connected firstly to the reset input of the second D-type flip-flop, secondly to the clock input of a fourth D-type flip-flop, and thirdly, via a second inverter, to the reset input of the third D-type flip-flop which also represents a clock output; and the non-inverting output of the third D-type flip-flop is conn2cted to the data input of the fourth D-type flip-flop, and the non-inverting output of the fourth D-type flip-flop being connected to a data output for the full-bit wide additional signal.

Of particular advantage in the receiver according to the invention 20 is the possibility of constructing the said receiver in fu'ly integrated technology as a user-specific integrated circuit. In a transmission system for digital wanted signals with a bit rate of approximately 140 Mbit/s and a digital additional signal for transmitting telemetry information, there is in this case the possibility of constructing the receiver in very energy-efficient CMOS technology.

A preferred further development of the receiver describes the case where the code rule violation tester of the digital transmission system b generates output signals which do not correspond to the CMOS level, according to the invention a pulse shaper which generates an output signal with a CMOS level is connectcd upstream of the receiver input.

The invention will be explained in greater detail below with reference to an exemplary embodiment illustrated in the drawings, in wh i c Fig. 1 shows a receiver according to the invention; and ii 3 Fig. 2 shows an associated pulse diagram.

IAD/1530o '0 t ob rese inut f th seondD-tye fip-lop secndl tothe loc inut of a orhDtpefi-lp adtidy iaascn nvret h r 1 i' .l.;ii-.Lli:Li.I~I; ;ii 3B- In Fig. 1, connected upstream of the receiver input E is a pulse shaper PF with an input EO which shapes the error pulses generated by a code rule violation tester situated at the receiving end into pulses with the CMOS level, since the entire receiver connected downstream is F designed as an integrated circuit in CMOS technology. Connected to the receiver input E is the clock input of a first D-type flip-flop DFI, the non-inverting output of which is connected to the clock input of a second D-type flip-flop DF2. Further connected to the receiver input E is roo~ o o ~~r

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4 89 P 2023 DE -r o 4r 9*9 4,4,r o 4 *9 r 44 *94999 94 94 9ri 9 the clock input of the third D-type flip-flop DF3, to the non-inverting output of which the data input D of a fourth D-type flip-flop DF4 is connected. The data inputs D of the first to third flip-flop DFi...DF3 are connected to a terminal H for a potential corresponding to the logical high level. The inverting output of the first D-type flipflop DF1 is connected to the enable input of a first binary counter Z1, while the inverting output of the second D-type flip-flop DF2 is connected via a first resistor to the plus input of an operational amplifier OV and to the one terminal of a first capacitor Cl, the other terminal of which is connected to reference potential. The first resistor R1 and the first capacitor Cl together form a low-path filter.

The minus input of the operational amplifier OV is connected via a second resistor R2 to supply voltage VC, via a third resistor R3 to reference potential and via a second capacitor C2 to the output of the operational amplifier OV; the control input of a voltage-controlled oscillator VCO is connected to this output via a fourth resistor R4. The third resistor R3 is selected to have a resistance corresponding to seven times the second resistor R2, so that 7/8 of the supply voltage VC is present at the junction of the voltage divider formed by the two resistors and hence at the minus input -f the operational aiiplifier OV.

25 Together with the voltage divider and the second capacitor C2, the operational amplifier OV forms a proportionalintegral final control element with the reference voltage of 7/8 of the supply voltage VC. The voltage-controlled oscillator VCO oscillates at eight times the bit clock frequency of the combined signal transmitted and outputs a corresponding clock signal to the clock inputs of the first and of the second binary counter Z1, Z2. The enable input of the second binary counter Z2 is connected to reference potential. Both binary counters are designed as four-stage counters, so that a counter or divider ratio of 8 1 is obtained. The output of the first binary counter Z1 is connected via a first inverter 11 to the reset input R of the first D-type flip-flop DF1, the counter output of the second counter Z2 is analogously connected to the reset

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a o 000 o oe 0 0 0 040 0 *000 u a 0 0 o o a o ft II 0 00 0 00 0 ii input R of the second D-type flip-flop DF2, and in addition however also to the clock input of the fourth D-type flipflop DF4 as well as via a second inverter R2 to the reset input R of the third D-type flip-flop DF3 as well as a clock output TA. The non-inverting output of the fourth Dtype flip-flop DF4 is connected to an output DA for fullbit wide data pulses.

For explaining the function of the receiver illustrated in Fig. 1, reference is made to the pulse diagram according to Fig. 2, in the top line of which the received pulses EP present at the receiver input E are shown. The received pulses EP can be clock pulses TP or data pulses DP. The clock pulses TP always occur at the beginning of the bit period of the transmitted combined 15 signal, data pulse (sic) DP can occur at an interval of approximately 1/4 bit period after the clock pulses. In the exemplary embodiment, the data pulses DP indicate the presence of a one-bit of the additional signal, so that these data pulses only occur sporadically in the received signal. The duration of the clock and data pulses TP, DP i. comparatively short here in comparison with the interval of 1/4 bit period.

The first D-type flip-flop DF1 forms together with the voltage-controlled oscillator VCO and the first binary counter Zl a time element with a behaviour similar to that of a monostable multivibrator. It is intended that this arrangement is to be triggered solely by received clock pulses and the logical level is to be held thereafter until received data pulses DP are covered, and are hence made ineffective. In order to explain this procedure, it is first of all assumed that the non-locked state of the phase-locking loop is present, that is to say a plesiochronous state of the voltage-controlled oscillator VCO.

The leading edge of a received clock pulse then triggers first of all the first D-type flip-flop DF1, the inverting output of which enables the first counter Zl until the counter position A is reached in accordance with half a bit clock period. The first D-type flip-flop DF1 is subsequently reset and, via the inverting output thereof, in i i,

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a 0 0 oa a a a @0 o series, also the first binary counter Zl. The width of the pulse produced at the output of the first D-type flip-flop DF1 can in this case be between 3 and 4 periods of the voltage-controlled oscillator VCO depending on the phase position between voltage at the voltage-controlled oscillator and received clock pulse. The output pulse of the first D-type flip-flop is then approximately between 0.375 and 0.5 times the bit clock period, so that a data character following the clock pulse is reliably covered. On the other hand, an incorrect synchronization of the arrangement with a received data pulse is out of the question, since in the case of first possible triggering by a data pulse the output of the first D-type flip-flop DF1 is again in the quiescent state until the arrival of the next pulse, which 15 must be a clock pulse. The first D-type flip-flop DF1 is then triggered again by means of this clock pulse and hencs the desired correct synchronization with the clock pulses is directly ensured. As a result of the synchronization, the leading edges of the output pulses generated by the first D-type flip-flop DF1 are firmly linked to the leading edges of the received clock pulses, so that the leading edges of the output pulses can serve as guide values for the downstream phase-locking loop for clock regeneration.

In the phase-locking loop the phase discriminator required 25 is formed by the second D-type flip-flop DF2, the inverting output of which feeds the active loop filter formed by the first resistor Rl, the first capacitor Cl aid the operational amplifier OV. Owing to its construction in CMOS technology, the second D-type flip-flop switches between reference potential and the supply voltage VC, in this case the reference voltage of the operational amplifier OV is here equal to 7 x R2 owing to the selection of the resistances for the second and the third resistor R3, given a voltage value of 7/8 of the supply voltage VC.

During the phase comparison the second D-type flip-flop DF2 is triggered by the positive edge of the non-inverted output pulse of the first D-type flip-flop DF1 and is reset by the next trailing edge of the output voltage of the second counter Z2, and is held in this i i' i: ij j i 7 89 P 2023 DE @000 00 I 0~00 0 000000 state during the entire negative clock half-wave. The output voltage at the inverting output of the second Dt1-pe flip-flop DF2 and hence the mean DC voltage value at the input of the active loop filter is directly proportional to the time interval between the reference edge and the next clock edge. In this case, a lagging of the phase of the voltage-controlled oscillator generates a control voltage directed to negative values from the supply voltage VC, so that the voltage-controlled oscillator VCO is set up in such a way that a frequency rise takes place when the control voltage falls. Owing to the integral effect of the loop filter, the output voltage of the second D-type flip-flop DF2 is exactly at the reference voltage of 7/8 of the supply voltage, so that in the steady-state condition the clock edge must come at 1/8 of the clock period after the reference edge.

This corresponds to line TA in the phase diagram in the Fig. 2; this line shows the recovered clock signal present at the clock output TA and it can be seen that 20 the leading edge of the clock signal comes 1/8 bit period after the reference edge. The construction of the phase discriminator by means of a D-type flip-flop, and its resetting and turning off for half a bit period, has the additional advantage that in the case of asynchronous operation of the voltage-controlled oscillator to the reference frequency the mean output voltage value is likewise 7/8 of the supply voltage VC and hence a locking of the phase-locking loop is possible without an additional capture circuit.

As can be seen from line TA in Fig. 2, the generated clock signal enables the clock input of the third D-type flip-flop DF3 for half a bit duration in the middle between the clock pulse TP and the data pulse DP.

If a data pulse occurs during this tie, the noninverting output of the third D-type flip-flop DF3 is set to the logical one level. During the trailing edge of the recovered clock, in accordance with a leading edge before the second inverter 12, the data signal is transferred into the fourth D-type flip-flop DF4 and is stored there 0040 a 0 4 0 0 1 S S1 L l

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8 89 P 2023 DE in its full bit width. At the same time as the transfer into the fourth D-type flip-flop DF4, the third D-type flip-flop DF3 is reset and is disabled for half a bit clock period to 1/8 bit period D after the next clock pulse, so that a received clock pulse TP cannot simulate a data pulse DP. At the output of the fourth D-type flipflop DF4 the regenerated data, that is to say the transmitted additional signal, is present in the full bit width, as shown in line DA. The likewise newly generated associated clock signal is largely freed of possible phase jitter by the phase-locking loop. This also applies to phase fluctuations which can arise at the transmitting Send when the date pulses are inserted.

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Claims

1. I 9 -9- The claims defining the invention are as follows: I. A receiver for a digital additional signal with a comparatively low bit rate which is transmitted together with a digital wanted signal in one channel of a digital transmission system such that the digital additional signal and an associated clock signal are combined to form a combined signal, the bit rate of the combined signal corresponding to that of the signal to be transmitted additionally, and a comparatively short clock pulse in comparison with the bit period is generated at the beginning of each bit of the combined signal and, at fixed time intervals from this, a likewise short data pulse is generated whenever optionally either a one-bit or a zero-bit occurs in the digital additional signal; wherein the combined signal is also inserted into a transmission or link code during the code conversion of the binary wanted signal, and at the receiving end at least one error pulse is generated by a code rule o violation tester for each code rule violation detected, and is output to a receiver input of said receiver; wherein the clock inputs of a first and of a third D-type flip-flop are connected to the receiver input; the clock input of a second D-type flip-flop is connected to the non-inverting output of the first D-type flip-flop; the data inputs of the first, of the second and of the third 0 .D-type flip-flop are connected to a terminal asserting a potential S"0:0 corresponding to the logical high level; i the inverting output of the second D-type flip-flop Is connected via a first resistor to the plus input of an operational amplifier and via a first capacitor to a reference potential; the output of the operational amplifier is connected via a second capacitor to the minus input of the operational amplifier, the minus input being connected to the centre tap of a voltage divider formed from a second and a third resistor; the output of the operational amplifier is connected to the control input of a voltage-controlled oscillator either directly or via a i fourth resistor; the output of this oscillator is connected to the clock inputs |1 of a first binary counter and of a second binary counter; ci 9^0/15300 I S- 10 the enable input of the first binary counter is connected to the inverting output of the first D-type flip-flop; the enable input of the second binary counter is connected to the reference potential; the output of the first binary counter is connected via a first inverter to the reset input of the first D-type flip-flop; the output of the second binary counter is connected firstly to the reset input of the second D-type flip-flop, secondly to the clock input of a fourth D-type flip-flop, and thirdly, via a second inverter, to the reset input of the third D-type flip-flop which also represents a clock output; and the non-inverting output of the third D-type flip-flop is connected to the data input of the fourth D-type flip-flop, and the non-inverting output of the fourth D-type flip-flop being connected to a data output for the full-bit wide additional signal.

2. A receiver according to claim 1, wherein the resistance of the third resistor is seven times the resistance of the second resistor, and in that the voltage-controlled oscillator oscillates at a frequency corresponding to eight times the bit clock frequency of the digital :additional signal and the first and the second binary counters have a I counting or dividing ratio of 8 1.

3. A receiver according to claim 1, wherein a pulse shaper which generates an output signal with a CMOS level is connected upstream of the receiver input.

4. A receiver according to claim 1, wherein the voltage- controlled oscillator (VCO) outputs an oscillation with rising frequency :when the control voltage falls. A receiver substantially as described herein with reference to the drawings. DATED this TWENTY-EIGHTH day of MAY 1992 Siemens Aktiengesellschaft i Patent Attorneys for the Applicant SPRUSON FERGUSON I Ao/ 0o i 3 IAD/15300 1^'