AU640367B2 - Waveform generation and control - Google Patents

Description

OPI DATE 05/09/90 APPLN. ID 50934 PCT AOJP DATE 11/10/90 PCT NUMBER PCT/AU90/00045 INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 5 (11) International Publication Number: WO 90/09704 HO3K 3/017, HO2M 7/5395, 7/5387 Al H03F 3/17 H02M 7/5395 7/538 (43) International Publication Date: 23 August 1990 (23.08.90) (21) International Application Number: PCT/AU90/00045 (81) Designated States: AT, AT (European patent), AU, BB, BE (European patent), BF (OAPI patent), BG, BJ (OAPI (22) International Filing Date: 7 February 1990 (07.02.90) patent), BR, CA, CF (OAPI patent), CG (OAPI patent), CH, CH (European patent), CM (OAPI patent), DE, DE (European patent), DK, DK (European patent), ES, Priority data: ES (European patent), FI, FR (European patent), GA PJ 2680 9 February 1989 (09.02.89) AU (OAPI patent), GB, GB (European patent), HU, IT (European patent), JP, KP, KR, LK, LU, LU (European patent), MC, MG, ML (OAPI patent), MR (OAPI patent), (71) Applicant (for all designated States except US): SIEMENS MW, NL, NL (European patent), NO, RO, SD, SE, SE LIMITED [AU/AU]; 544 Church Street, Richmond, (European patent), SN (OAPI patent), SU, TD (OAPI VIC 3121 patent), TG (OAPI patent), US.

(72) Inventor; and Inventor/Applicant (for US only) BUTLER, Dale, John Published [AU/AU]; Woodbrook Road, Woodbrook Via Castle- With international search report.

maine, VIC 3450 With amended claims.

(74) ~gent: SPRUSON FERGUSON; GPO Box 3898, Syd- 6 ney, NSW 2001 6 43 6 (54)Title: WAVEFORM GENERATION AND CONTROL (57) Abstract The present invention discloses an inverter circuit for producing a sinusoidal waveform from a DC power supply. One quadrant of the sinusoid has its magnitude stored and applied to a monostable to produce a sequence of pulse width modulated pulses. These pulses are then applied to the control inputs of a four quadrant switch supplied from the DC supply. The techniques disclosed herein are not limited to sinusoids and other waveshapes are possible. Amplification of indeterminate digital waveforms is also disclosed.

WO 90/09704 PCT/AU90/00045 -1- WAVEFORM GENERATION CONTROL The present invention relates to the generation of voltage or current waveforms and finds particular application in the inverting of a DC power supply so as to create a sinusoidal waveform. However, the present invention is not limited to this application since the method is also able to reproduce an incoming waveform and thereby amplify, or generate other different types of waveforms.

TECHNICAL FIELD In relation to inverters, such circuits are required at remote locations where an AC main supply is not available. The generally preferred method of supplying a mains frequency AC supply under such circumstances is to store energy in a battery, whether the energy is derived from solar cells, wind power generators, diesel generator sets, or the like, and then invert the DC voltage of the battery into the necessary AC voltage.

It is necessary that the inverter be of relatively low cost and also be able to handle substantial amounts of power, typically of the order of a kilowatt or more.

BACKGROUND ART One prior art method of achieving this object is to generate a square wave having a pulse repetition rate equal to the desired AC frequency, and then filter the waveform so as to remove particularly the higher frequency harmonics. Whilst this produces a result, many white goods manufacturers and the manufacturers of other small electrical appliances, will not guarantee the operation of their appliances where the supply is derived in thisiwtaam from a square wave. Accordingly, this approach has a limited appeal to the consumer.

In addition to filtering a square wave having a pulse repetition rate equal to the intended frequency of the desired sine wave, various other techniques have been used to generate sine waves. One of these is disclosed in Australian Patent Application No. 56814/80 which discloses the generation of a pseudo-sinusoidal signal by means of 4 eaeE&.11 r time to pulses each of the same duration by dividing the output of a high frequency clock, and combining the pulses in accordance with a staggered phase relationship in order to produce a stepped waveform which is approximately sinusoidal. Australian Patent Specification No. 53018/79 discloses a similar arrangement save that the fundamental frequency of the pseudo-sinusoidal waveform is selectable between two different frequencies.

It is one object of the present Invention to provide a method of generating a waveform which will overcome the abovementloned consumer appeal problem inherent with square wave inverters.

SUMMARY OF THE INVENTION According to one aspect of the present invention there is disclosed a method of generating a predetermined voltage or current waveform, said method comprising the steps of determining the magnitude of said waveform at each of a series of equally spaced time intervals, generating a series of pulses each of which corresponds to one of said time intervals, modulating the pulse width of each said pulse of said series of pulses in accordance with the determining magnitude of the corresponding time interval, and applying said pulse width modulated pulses to the inputs of a four quadrant switch means to generate said waveform at the output of said four quadrant switch means.

In accordance with another aspect of the invention there is provided a method of generating a predetermined voltage or current waveform, said method comprising the steps of: determining a magnitude of said predetermined waveforem at each oF a series of equally spaced time intervals without generating an internal reference waveform representative of the said predetermined voltage or current waveform, generating a series of discrete pulses each of which corresponds to a sequential one of said time intervals, modulating the pulse width of each pulse of said series of pulses in accordance with said determined magnitude at each corresponding time interval, ann applying said pulse width modulated pulses to inputs of a four quadrant switch means for generating said predetermined waveform on an output of said four quadrant switch means.

In accordance with yet another aspect of the present Invention there Is disclosed an Inverter circuit for creating a sinusoidal waveform from a DC supply, said circuit comprising memory means to store a representation of the intended magnitude of said sinusoid waveform at each of a plurality of equally spaced time intervals, the output of said memory means being connected to a monostable means to control the pulse width of the output thereof, and said monostable output being connected to the control terminals of a four quadrant switch means supplied by said 117o DC supply, the output of said switch means constituting said sinusoidal waveform.

In accordance with a fourth aspect of the present invention there is provided an inverter circuit for creating a sinusoidal waveform from a DC supply without the use of an internally generated reference waveform representative of the said sinusoidal waveform, said circuit comprising memory means to store a representation of an intended magnitude of said sinusoidal waveform at each of a plurality of sequentially and equally spaced discrete time intervals, an output of said memory means being connected to a monostable means to modulate pulse width of output pulses of an output of said monostable means, and said monostable means output pulses being connected to control terminals of a four quadrant switch means supplied by said DC supply, an output of said switch means constituting said sinusoidal waveform.

BRIEF DESCRIPTION OF THE DRAWINGS Three embodiments of the present invention will now be described with reference to the drawings in which: Fig. 1 is a circuit diagram of the preferred inverter circuit of the Z.Lo) IAD,117o WO 90/09704 PCT/AU90/00045 -3present invention, Fig. 2 is a circuit diagram of another inverter circuit in which the predetermined magnitude of the output waveform is stored in a read only memory (ROM), Fig. 3 is a circuit similar to Fig. 2 but in which a different control circuit is provided, and Fig. 4 is a schematic block diagram of an amplifier circuit.

BEST MODE OF CARRYING OUT THE INVENTION As seen in Fig. 1, a conventional clock which has a pulse reDetition rate of 3kHz drives an up down counter CN the output of which is supplied to a 1:16 decoder. Whether the counter CN counts up or down is controlled by an RS flip-flop having its inputs connected to the 0 and 15 output lines of the 1:16 decoder.

The outputs 1-15 of the 1:16 are each connected via a respective resistor R1-R15 to a common line which forms the input to a monostable of adjustable pulse width. Each of the resistors RI to R15 inclusive has a S k cee n eq_-3 cc e-S c-c k L 1 a value which representsA t =A one quarter or quadrant of a sine wave. Since it is the relative magnitudes of the resistors Rl-R15 which is important rather than their absolute magnitudes, the resistors R1-R15 are easily fabricated using thick film techniques.

The output of the monostable which constitutes a pulse of variable width, is supplied to a gating and driver circuit which provides four outputs A-D which are respectively connected to the control terminal of four corresponding switches S1-S4. Although in this embodiment the switches S1-S4 are each realized by an NPN transistor and a protection counter-poled diode, other switching devices such as power.fes or thyristors could be used.

The switches S1-S4 together constitute a four quadrant switch having input terminals Tl and T2 which are respectively connected to the positive and negative terminals of a battery supply (not illustrated). The output terminals T3 and T4 of the four quadrant switch are connected to a load impedance Z which typically is reactive including both resistive and inductive elements. Inductor L1 and capacitor L2 constitute a simple filtering circuit.

As illustrated in Fig. 1, a' operational amplifier OA is provided having one terminal connected to a reference voltage Vref and having the other input terminal connected to a feedback voltage Vfb. The output of the comparator is connected to a control input of the monostable. As S.s WO 90/09704 PCT/AU90/00045 -4indicated schematically in Fig. 1, the feedback Vfb can be derived from the output terminals T3 and T4 of the f our quadrant switch by rectification and filtering so as to generate a feedback voltage Vfb which is representative of the amplitude of the sine wave appearing at the output terminals T3 and T4.

The operation of the circuit of Fig. 1 is as follows. At a rate determined by the clock, the counter CN counts, say, up from 0 to 15. This count when applied to the 1:16 decoder results in each of the resistors RI to R15 in sequence being connected to the input of the monostable as a current source. At count 15, the SR flip-flop is reset thereoy causing the counter CN to count downwardly from 15 to 0. This results in each of the resistors R15 to R1 in turn being connected as a current source to the input of the monostable. When count 0 is reached, the SR flip-flop is set thereby causing the counter CN to recommence counting upwards once again.

Simultaneously, the zero output of the 1:16 decoder is used to trigger the flip-flop F2 in order to switch the gating circuit at the conclusion of the first and second, say, positive quadrants of the desired sine wave and commence the third and fourth negative quadrants.

It will be appreciated that the pulse produced by the monostable is pulse width modulated in accordance with the predetermined relative resistor values R1-R16. As a consequence, the time during which the switches S1-S4 areA~pe is controlled by the duration of the monostable pulse. This time directly reflects the desired magnitude of the sinusoidal waveform to be created and it is reflected in the control duty cycle of the switches S1-S4.

D_

Since each quadrant of th desired 50Hz sinusoidal waveform is divided into 15 time intervals, and there are four such quadrants, this requires a total of 60 time intervals in one cycle of the sinusoidal waveform. Accordingly, the clock frequency is 60 x 50 3kHz.

The feedback provided by the operational amplifier OA adjusts the overall gain of the monostable and thus does not effect the relative -fp aFEaa of the output waveform, but rather the absolute magnitude of the peak voltage. It will also be apparent analogue control voltages do not have to be converted to digital representations in order to enable feedback to be implemented. This is because the digital to analogue aspects represented by resistors R1-R15 are outsideAthe feedback loop and therefore do not introduce any feedback delay.

S It will be apparent to those 'killed in the art that the resistors R1 WO 90/09704 PCT/AU90/00045 to R15 constitute a non-volatile, permanent memory source in the form of a digital representation of the desired analogue waveform, in this particular embodiment one quadrant of a waveform which is symmetric both with respect to time and to zero magnitude (polarity). Accordingly, this digitized information could also be stored in a read only memory (ROM) which is operated under microprocessor (uP) control as indicated in Fig. 2. In the circuit of Fig. 2, the data stored in the ROM is sequentially read out to the digital to analogue converter in order to provide an analogue input to the monostable as before. An output from the D to A converter is used to control the sequence of the gating and driver circuit as before.

The microprocessor provides timing and control signals to both the monostable and the gating and driver circuits.

As before, the output of the operational amplifier OA is used to control the monostable. The reference voltage Vref is as before and an analogue control voltage Vcon is provided which can be the feedback voltage Vfb of ;ig. 1, or some other control voltage if desired.

Fig. 3 represents a variation on the arrangement of Fig. I. The predetermined sequence of magnitudes of the waveform to be generated are stored within the ROM as before and read out under microprocessor control to the D/A converter as before. The output of the D to A converter can be regarded as a reference voltage which is compared in comparator CR against a feedback voltage Vfb derived from the ultimate output. This sampled output voltage is compared with the reference voltage such that when the output voltage is greater than or equal to the reference voltage, then the output of the comparator changes in order to reset the RS flip-flop used to realize the monostable. The RS flip-flop is set by the microprocessor and is clocked at the necessary clock frequency as explained above in relation to Fig. 1. The operation of this circuit is somewhat reminiscent of a conventional delta modulator, however, the arrangement is greatly simplified since the generation of analogue sine and triangle waves is not required.

Fig. 4 illustrates the schematic circuit of an amplifier in which a digital input voltage Vin (for example from a CD player or vibration tester) is applied to a latch having an output connected to a digital to analogue converter the output of which is applied to the comparator CR. The comparator output is in turn is applied to an RS flip-flop and thence the gating and driver circuit as in Fig. 3. Thus the four quadrant switch Sl-S4 's operated so as to generate at the output terminals T3-T4 an WO 90/09704 PCT/AU90/00045 -6accurate amplified representation of the input voltage making use of the power supplied to the switch S1-S4 via the terminals T1-T2.

The foregoing describes only some emoodiments of the present invention and modifications, obvious to those skilled in the art, can be made thereto without departing from the scope of the present invention.

For example, the four quadrant switch S1-S4 is reversible in the sense that alternating current can be input on terminals T3 and T4 and converted to direct current and fed to the battery (not illustrated) or other DC supply in a controlled manner provided that the peak voltage of the AC input is less than the magnitude of the DC supply.

Claims (28)

1. A method of generating a predetermined voltage or current waveform, said method comprising the steps of determining the magnitude of said waveform at each of a series of equally spaced time intervals, generating a series of pulses each of which corresponds to one of said time intervals, modulating the pulse width of each said pulse of said series of pulses in accordance with the determined magnitude of the corresponding time interval, and applying said pulse width modulated pulses to the inputs of a four quadrant switch means to generate said waveform at the output of said four quadrant Fwitch means.

2. The method as claimed in claim 1, wherein an input voltage Is sampled at each of said time intervals to determine said magnitudes, whereby the output of said switch means comprises an amplified reproduction of said input voltage.

3. The method as claimed In either one of claims 1 or 2, wherein said magnitudes are predetermined and stored in a memory means.

4. The method as claimed in claim 3, wherein said waveform is symmetric with respect to both time and polarity whereby one quadrant of said waveform is stored in said memory means.

The method as claimed In claim 4 wherein said waveform comprises a sinusoid.

6. The method as claimed in any one of claims 1 to 5, wherein said magnitudes are digitally determined and converted to analogue magnitudes for modulating said pulse widths.

7. The method as claimed In claim 6, wherein an analogue representation of said output of said four quadrant switch means Is used for a feedback signal to control said pulse width modulation.

8. The method as claimed in claim 7, wherein said digital to analogue conversion takes place external to a feedback loop formed by said feedback signal.

9. A method of generating a predetermined voltage or current waveform, said method comprising the steps of: determining a magnitude of said predetermined waveforem at each of a series of equally spaced time intervals without generating an internal reference waveform representative of the said predetermined voltage or current waveform, generating a series of discrete pulses each of which corresponds to a sequential one of said time intervals, m)dulating the pulse width of each pulse of said series of pulses In accordance with N ,IAD/117o It -8- said determined mnintude at each corresponding time Interval, and applying said pulse width modulated pulses to inputs of a four quadrant switch means for generating said predetermined waveform on an output of said four quadrant switch means.

The method as claimed in claim 9, wherein an input voltage is sampled at each of said time intervals to determine said magnitudes, whereby the output of said switch means comprises an amplified reproduction of said input voltage.

11. The method as claimed in either one of claims 9 or 10, wherein said magnitudes are predetermined and stored in a memory means.

12. The method as claimed in claim 11, wherein said waveform Is symmetric with respect to both time and polarity whereby one quadrant of said waveform is stored in said memory means.

13. The method as claimed in claim 12 wherein said waveform comprises a sinusoid.

14. The method as claimed in any one of claims 9 to 13, wherein said magnitudes are digitally determined and converted to analogue magnitudes for modulating said pulse widths.

The method as claimed in claim 14, wherein an analogua representation of said output of said four quadrant switch means is used for a feedback signal to control said pulse width modulation.

16. The method as claimed In claim 15, wherein said digital to analogue conversion takes place external to a feedback loop formed by said feedback signal.

17. An inverter circuit for creating a sinusoidal waveform from a DC supply, said circuit comprising mnemory means to store a representation of the intended magnitude of said sinusoid waveform at each of a plurality of equally spaced time intervals, the output of said memory means being connected to a monostable means to control the pulse width of the output thereof, and said monostable output being connected to the control terminals of a four quadrant switch means supplied by said DC supply, the output of said switch means constituting said sinusoidal waveform.

18. A circuit as clalmed In claim 17, wherein said memory means comprises a resistive array etch 'eslstor of which Is connected to the corresponding output of a sequential counter means.

19. A circuit as claimed In claim 17, wherein said memory means /C comprises a digital memory outputable to a digital to analogue converter.

UY.- IAD/117o -9- A circuit as claimed in any one of claims 17, 18 or 19, wherein said monostable means includes a feedback control input and a rectified representation of said sinusoidal waveform and a reference voltage are connected as inputs to a comparator means the output of which is connected to said feedback control Input.

21. A circuit as claimed in any one of claims 17, 18 or 19, wherein said monostable means comprises comparator means to compare the output of said memory means with a rectified representation of said sinusoid waveform. the output of said comparator means being connected to flip flop means to switch same when the output of said memory means is substantially equal to said rectified sinusoid representation.

22. An inverter circuit for creating a sinusoidal waveform from a DC supply without the use of an Internally generated ,eference waveform representative of the said sinusoidal waveform, said circuit comprising memory means to store a representation of an Intended magnitude oF said sinusoidal waveform at each of a plurality of sequentially and equally spaced discrete time intervals, an output of said memory means being connected to a monostable means to modulate pulse width of output pulses of an output of said monostable means, and said monostable means output pulses being connected to control terminals of a four quadrant switch means supplied by said DC supply, an output of said switch means constituting said sinusoidal waveform.

23. A circuit as claimed in claim 22, wherein said memory means comprises a resistive array each resistor of which is connected to the corresponding output of a sequential counter means.

24. A circuit as claimed in claim 22, wherein said memory means comprises a digital memory outputable to a digital to analogue converter.

A circuit as claimed In any one of claims 22, 23 or 24, wherein said monostable means includes a feedback control input and a rectified representation of said sinusoidal waveform and a reference voltage are connected as inputs to a comparator means the output of which is connected to said feedback control Input.

26. A circuit us claimed in any one of claims 22, 23 or 24, wherein said monostable means comprises comparator means to compare the output of said memory means with a rectified representation of said sinusoid waveform, the output of said comparator means being connected to flip flop means to switch same when the output of said memory means is substantially equal to said rectified sinusoid representation. 10

27. A method -f generating a predetermined voltage or current waveform substantially as described herein with reference to any one of the drawings.

28. An inverter circui~ substantially as described herein with reference to any one of the d,'awings. DATED this TWENTY-SEVENTH day of APRIL 1992 Siemens Ltd Patent Attorneys for the Applicant SPRUSON FERGUSON rO I IAD/117o