AU655308B2 - High speed switching architecture - Google Patents

Description

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OPI DATE 11/02/93 APPLN. ID 22416/92 AOJP DATE 08/04/93 PCT NUMBER PCT/AU92/00322 llI~ll II IAI 11111U922246111111 ll II I 11|1 AU9222416 INTERNATIIONAL AVLI _A I IUIN ruoD Jll- 1i u3r i.j I ,PCT) (51) International Patent Classification 5 (11) nternational Publication Number: WO 93/01669 H04L 12/54, 12/56 Al (43) International Publication Date: 21 January 1993 (21.01.93) (21) International Application Number: PCT/AU92/00322 (81) Designated States: AT. AU. BB, BG, BR, CA, CH, CS, DE, DK, ES, FI, GB, HU, JP, KP, KR, LK, LU, MG, (22) International Filing Date: I July 1992 (01.07.92) MN, MW. NL. NO, PL, RO, RU, SD, SE, US, European patent (AT, BE. CH, DE, DK, ES, FR, GB, GR, IT, LU, MC, NL. SE), OAPI patent (BF, BJ, CF, CG, Priority data: CI, CM. GA, GN, ML, MR, SN, TD, TG).

PK 6968 1 July 1991 (01.07.91) AU i c -CI- C LW- .v j Published (71) Applicant (for all designated Sttes except US): A-STRA-f- ith international search report.

-IAN -AND-OVERSEAS-TELEC-OMMU-N-LC-A-ONS-- CORPOR-ATON-tl-MITED [AU/AU]; 231 Elizabeth Street, Sydney, NSW 2000 (72) Inventor; and l Inventor/Applicant (for US onl') FOLLETT, Douglas, James [AU/AU]; 4 Colin Place, Carlingford, NSW 2218 (74) Agent: WATERMARK PATENT TRADEMARK AT- TORNEYS; Level 4, Amory Gardens, 2 Cavill Avenue, Ashfield, NSW 2131 (AU).

(54)Title: HIGH SPEED SWITCHING ARCHITECTURE "i (57) Abstract A high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics (16, 17, 18, 19) to switch slices of serial packets in parallel. A highly parallel interconnect network within each fabric allows for high speed effective data switching at relatively low clock speeds.

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WO 93/01669 PCT/AU92/00322 HIGH SPEED SWITCHING ARCHITECTURE Technical Field The present invention relates to a high speed switching architecture, particularly for ATM or fast packet switches.

Background Art The banyan-based architectures are one type of space division packet switching. However, while the banyan-based switches have less crosspoints than other techniques, they do require a means of overcoming blocking, improving throughput and reducing cell loss. This is because of the contention that occurs at a crosspoint when two (or more) inputs want to access the same outlet. These 'means' therefore further classify the banyan-based switches into either buffered-banyan or batcher-banyan architectures. The buffered banyan architectures have buffers at the points of contention while the batcher-banyan architectures minimise the contention by sorting the input cells. The buffered banyan architecture has been adopted to realise a switching fabric subsystem. However, these generally involved several levels of buffers at the input, output and intermediate switching stages.

Disclosure of Invention It is an object of the present invention to provide an architecture which improver the throughput of and minimises the delay through the switching fabric by a packet or ATM cell.

This is achieved by providing a manyfold parallel path internal switch architecture, which requires minimal buffering and multiplexing. According to one aspect the present invention comprises a packet switch, comprising a switching fabric unit (SFU) having a plurality of inputs and a plurality of outputs, each input and output having a respective port controller means, wherein said input port controller means are adapted to convert each input serial packet into a plurality of parallel packets, said SFU including internal parallel paths for each of said plurality of packets, and said output port controller means including means for converting said parallel packets into a serial packet form as input.

The invention will be described with reference to a 16 x 16 switching architecture, an architecture for switching input ATM cells from 16 inputs and switching to any one of 16 outputs. However, it will be appreciated that the inventive concept is equally applicable to other n x n switches.

WO 93/01669 PCT/AU92/00322 Brief Description of Drawings Figure 1 is a schematic view of one embodiment of a switch according to the present invention; Figure 2 is a conceptual view of a format of a packet; Figure 3 is an illustration of a switching fabric unit architecture according to one embodiment of the invention; Figure 4 illustrates schematically in part one switching fabric architecture; Figure 5 illustrates schematically a preferred switching fabric architecture; and Figure 6 illustrates the multi-plane switch architecture.

Detailed Description S Referringto Figure 1, a schematic block diagram conceptually illustrates a switch 10 comprising a'switching fabric with inputs 0 15 and outputs 0 15, i.e. a 16 x 16 switching fabric. The switch also includes input port controllers 30n, on each input 0 15 and output port controllers 20,n on each output 0 15. In a suitable construction input and output port controllers may be the same unit.

Packets to be switched preferably arrive at the input port controller in the form of ATM frames. Referring to Figure 2, an ATM frame according to an embodiment of the invention comprises a header of at least 3 bytes, and an ATM cell as defined by CCITT recommendation 1.361 comprising 53 bytes as payload.

Input port controllers 30, n convert incoming serial ATM frames into an 8 bit wide data stream. The serial ATM frames are converted to parallel packets by sequentially placing received bits onto each parallel link. The output port controllers perform the reverse operation.

It will therefore be appreciated that links 21n, 3 1 n between the SFU and output and input port controllers are in fact each 8-fold parallel connections.

The switching fabric 10 according to the present invention comprises four parallel planes, each plane being a 16 x 16 switching fabric sub-unit 16, 17, 18, 19, as can be seen in concept from Figure 6. Thus, two bit wide slices of the 8-bit wide data stream are received by each 16 x 16 switching fabric sub-unit 16, 17, 18, 19.

A general architecture for a 16 x 16 switching fabric sub-unit constructed from 4 x 4 elements 11 and 12, is shown in Figure 3. Other architectures at this level may be used within the scope of the invention, but this architecture will be used by way of example.

i~f U" 1 WO 93/01669 PCT/AU92/00322 3 Figure 4 shows one embodiment of the invention in detail. This corresponds to two 4 x 4 elements 11 and 12 of a single plane of the switching fabric with interconnect as indicated.

Two bit wide inputs 39 are converted to an 8-bit wide data stream by serial to parallel converters 40, and enter 8-bit wide FIFO buffer 42. Interconnect network 43 provides separate parallel paths for each frame segment from buffer 42 to the addressed multiplexer 44.

Multiplexer 44 routes the inputs via link 45 to input FIFO buffers 46 of the second switching stage. Again, interconnect network 47 provides separate parallel paths 1 0 for each packet to the addressed one of multiplexers 48. Parallel connection 49 connects to serial to parallel converters 50, which produce each a 2 bit wide output from 8 bit wide input 49, and hence output 51 comprises a 2 bit wide data for output to the respective output port controller.

It will be appreciated that the various slices from all the planes will be recombined at the output port controller to reconstitute the original serial data stream.

A preferred embodiment is shown in Figure 5, showing two 4 x 4 elements of a single plane.

The input 60 from input port controller 30o, is a 2 bit wide slice presented to FIFO buffers 61. Once the packets reach the output of buffers 61, they are sent via parallel interconnect network 62 and gating means 69 to FIFO buffers 63 of the second stage. It should be appreciated that if required gating means may involve more elaborate multiplexing. Once the packets are clocked to the end of buffers 63 and multiplexers are available, the packets are sent via parallel interconnect network 64 to multiplexers and then via output 66 to the respective output port controller.

It will be appreciated that in this embodiment, no further serial to parallel conversion is introduced beyond the port controller stage. Instead internal parallel paths alone are used to provide a non-blocking capability and Improved throughput.

It will be appreciated that the configuration of Figure 5 represents an improvement in throughput as compared with a basic buffered-banyan architecture.

Using the preferred embodiment of the present invention throughput limits at approximately 70% of offered load. Results previously published for a 16 x 16 single buffered-banyan network with 2 x 2 switching elements show limiting at about 52% (Jenq YC, "Performance Analysis of a Packet Switch based on Single-Buffered-Banyan I Network", IEEE Journal of Selected Areas is Communications Vol SAC-1 No, 6 Dec. 1983 pp 1014-1021).

i' al WO 93/01669 PCT/AU92/00322 4 Implementation The following discussion relates to one implementation of the invention and is not to be taken as limitative of the general scope of the invention.

This implementation uses li CMOS standard cell technology, principally because of availability custom ASICS would probably result in a more optimum arrangement.

The design chosen uses dual port RAM for the FIFO buffers to reduce chip area and power dissipation.

The implementation uses 4 switching Fabric Chips (SFC) operating in 1 0 parallel as discussed previously. Each SFC switches 2bits, i.e. one quarter of the byte which is input to port controller 30n. The data is clocked at about 20MHz between the port controllers 30n and SFU It is important to note that packets from all ports are aligned in time, and that progress through each parallel SFC is aligned, so as that at the output the fragments of each packet may be reliably reassembled.

To provide control and timing to internal circuits within each SFC, a 2-phase clock with 900 phase shift is required. This is particularly required for the dual port RAM selected. Preferably, clock skew across the entire switch is less than nanoseconds.

In order to maximise throughput, the SFC architecture should be optimised as much as possible. The key parameters for maximising throughput have been identified as: .kaJ buffer sizes and distribution increasing internal transfer rate simultaneous read from and write into buffers cut-through capability.

The implementation shown in Figure 5 has a number of advantages, including: avoids serial to parallel and parallel to serial conversion allows for read in and write out simultaneously from buffers (thereby reducing buffer size) simplified control circuitry simplifies cut-through implemeniation.

Each inlet 60 has a FIFO buffer 61 with a depth of 1 packet 64 addressable locations) and a width of 2bits. Each second stage element, however, has 16 FIFO buffers 63 each 1 packet deep. Hence, In the second stage there are a total of 64 j i i .i %I~ i WO 93/01669 PCT/AU92/00322 FIFOs (allowing for the other 4 x 4 elements) and so the internal data transfer rate is effectively 160 Mbps. Stage 1 merely requires selection of the correct stage 2 buffer 63.

In the implementation chosen, the 80 FIFO (16 stage 1 64 stage 2) buffers are implemented as a dual-port RAM operating as a FIFO with packets stored in parallel.

This allows for a vastly reduced area requirement on the chip. A schematic illustration is shown as Figure 7, for four FIFO buffers.

The RAM block is dual port to permit simultaneous read and write as in a FIFO. Since the buffers are combined in a block they have common address, read and write lines. Each of the four FIFO buffers in this RAM block however, operate as separate buffers. Since packets entering the SFC are synchronised the address can be identical for each buffer. But eachi buffer must have its own control for either reading the last packet and writing a new packet or storing the last packet. This is achieved with the multiplexers at the RAM write port which selects either data already in the RAM or newdata.

The differences between stages 1 and 2 arise because of the fourfold increase in parallel interconnection paths between them. From Figure 5, it can be seen that stage 1 has 4 buffers, associated requester control and 16 output paths which are arrarnged in 4 groups of 4. The second stage therefore, has 16 buffers arranged in parallel. The 4 outputs have access to each of the 16 buffers under the control of the granter associated with each output.

The RAM buffer block differ slightly. Stage 1 delays the input before writing the packet into the main block of RAM, whereas stage 2 delays the data already stored in RAM. This occurs because of the requirement to have the input and output packets from 25 the SFC aligned.

The maximum frequency of operation is to be 25MHz. Thus, the time allowed for propagation delay and set-up time etc. is 40 nanoseconds. Under worst case conditions of temperature and process variations a factor of 1.69 is used to calculate the maximum typical delay allowed for correct device operation. This equates to 23.67 nanoseconds. The design is to follow synchronous design rules which means that flip flops are only clocked by the master clock. This simplifies the realisation process to basically 3 constraints: 1. the minimisation of clock skew over the ch;p, and 2. keeping the propagation delay through combinational logic etc. between 2 flip flop or latches to less than 22 nanoseconds. (Allowance must also be made for set-up Ji: ]i WO 93/01669 PCT/AU92/00322 6 times, clock skew etc.) 3. keer;ig the propagation delay through combinational logic etc. between a flip flop and RAM write port to less than 17 nanoseconds. (Allowance must also be made for set-up times, clock skew etc.).

Further improvements in throughput can be achieved with variations in the architectures but which still are within the scope of the invention.

It will be appreciated that the preferred embodiment is adapted to allow easy implementation using integrated circuit techniques. Further, the inventive concept is V applicable to other n x n switches, using other sub-elements than 4 x 4 e.g. 2 x 2 if i1 0 desired. Variations and additions within the spirit and scope of the invention will be apparent to the skilled addressee and are incorporated within this application.

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Claims (3)

1. 2. A packet switch according to claim 1, wherein each of said internal parallel paths comprise a first stage comprising a first buffer means, a parallel interconnect network and a second stage comprising at least one buffer means associated with each of a plurality of addressable outputs.
2. 3. A packet switch according to claim 1 or claim 2, wherein said packets are self addressing.
3. 4. A method of packet switching in a system comprising a switching fabric unit (SFU) having a plurality of inputs and a plurality of outputs, each input and output having a respective port controller means, comprising the steps of: converting each input serial packet into a plurality of parallel packets at said Input port controller means, switching each of said plurality of parallel packets to an addressed output of sa!d SFU using Internal parallel paths for each of said plurality of packets, and reassembling each serial packet from the parallel packets at said output port controller means 5 A packet switch comprising a plurality of packet switches according to claim 'eASUBSTITUTE SHEET