AU674187B2 - Circuit and method for driving and controlling gas discharge lamps - Google Patents

Description

C -I lyl 1

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATTON FOR A STANDARD PATENT

ORIGINAL

o Name of Applicant: Actual Inventor: ETTA INDUSTRIES, INC.

Fazle S. QUAZI o Address for Service: Invention Title: SHELSTON WATERS Clarence Street SYDNEY NSW 2000 "CIRCUIT AND METHOD FOR DRIVING AND o ea o

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CONTROLLING GAS DISCHARGE LAMPS" Details of Original Application No. 51066/90 dated 12th February, 1990 The following statement is a full description of this invention, including the best method of performing it known to us:- ~PI--~QLC- a lb r 1 91 sra~e -e ~s IC- I I I 0 0 0 .4

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-la- The present invention relates to a control circuit and in particular to a control circuit for controlling a power circuit, wherein the power circuit supplies power variably to a fluorescent lamp load in response to the DC level of a variable control input voltage applied to a control input.

BACKGROUND OF THIE INVENTION In recent years, the fluorescent lamp, which requires less energy than the incandescent lamp to produce the same amount of light, has enjoyed increasing popularity. In many modern offices, fluorescent lamps are used to the complete exclusion of incandescent lamps. However, the energy efficient fluorescent lamp has not 10 replaced incandescent lamps to the same extent in other applications.

Since the advent of electrical lighting, people have desired to vary the brightness of lamps, so that a single lamp or group of lamps can provide varying light levels appropriate for a variety of activities. Dimming circuits for incandescent lamps have been well-known for many years, but dimming circuits for fluorescent lamps are more difficult to construct; previous efforts at producing effective fluorescent lamp dimmers have not been entirely successful. This is especially true when dealing with reliable lamp starting and maintaining optimum lamp life.

To achieve the highest functionality possible, a fluorescent dimming circuit should compensate for several inherent disadvantages of the fluorescent lamp relative to the 20 incandescent lamp. First, fluorescent lamps must be "started" at full intensity.

Generally, these lamps will not "start" at all at reduced intensity. In any case, low intensity startups will reduce their lifespan. Second, fluorescent lamps glow as a result of continuous excitation. The level of excitation can be reduced after the initial startup, but even a momentary interruption in this reduced 17331-00DOC/ma I L b I L LL -2excitation will put the lamp out, so that it must be restarted with greater excitation.

Third, the fluorescent lamp requires external ballast circuitry to "start" the lamp, so that it becomes important that the ballast uses minimal power and starts the lamp in a way that does not reduce the life of the lamp. Finally, excitation of fluorescent lamps requires storage of potentially dangerous charges, so that it becomes important that the controls for the lamps be isolated from the excitation circuitry.

Further, an ideal fluorescent dirmning circuit should provide safeguards against electrical shock. An inverter's output terminal(s) typically are connected resistively or capacitively to ground or a grounded inverter case. Depending on the inverter's output voltage, frequency and amount of resistive and or capacitive coupling, a significant amount of high frequency current can flow between the inverter' s output terminal(s) and S'ground. This can cause an electrical shock or a fire. Thus, there is a need for a fluorescent dimming circuit that prevents or limits the amount of current that can flow between a power inverter outtput terminal(s) and ground.

°15 It is an object of the present invention to overcome or at least ameliorate one or more of the disadvantages of the prior art.

SUMMARY OF THE INVENTION In accordance with the invention there is provided a control circuit for controlling a power circuit, wherein the power circuit supplies power variably to a fluorescent lamp load in response to the DC level of a variable control input vctago applied to a control input, said control circuit comprising: a brightness control input for setting a desired brightness of the long; 17331-00.DOC/mnja II~LIji. -LLI I L -3control pulse generating means connected to the brightness control input for generating control pulses of variable duty cycle, the duty cycle of the control pulses varying with the setting of the brightness control input; and integrating means connected to the control pulse generating means for integrating the control pulses over time to produce the variable control input voltage and provide t variable control input voltage to the power circuit control input.

In its preferred form, the control circuit incorporates delay circuitry which suppresses the pulse output at powerup, so that the lamp starts at full intensity.

Thereafter, the delay circuitry adjusts the pulse signal so that the lamp intensity is 10 adjusted smoothly to the desired level. A reset circuit resets the delay circuitry in case of o a momentary power failure so that the lamp will restart at full intensity and then smoothly dim to the desired intensity, rather than starting at a h w intensity. A brightness control circuit allows the user to set the desired light intensity, and an adjustable pulse control circuit allows limitation of the maximum amount of dimming.

15 Overcurrent circuitry disables pulse output if excessive current is drawn from the circuit.

In a preferred embodiment, the invention advantageously provides a system for dimming fluorescent or high intensity discharge lamps while maintaining optimum lamp life and as well as ensuring lamp starting under all conditions.

In other embodiments, the invention provides a control system for dimming gasdischarge lamps which starts the lamps at full intensity, then dims the lamps to the desired level.

In yet another embodiment, the invention provides a control system for dimming gas-discharge lamps which detects the occurrence of lamp-extinguishing momentary j.0On 17331-00,DOC/nja I I I ~I-II power interruptions and restarts the lamps at full intensity, thereafter dimming the lamps to the desired level.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a combined schematic and block diagram of a resonant inverter in accordance with the prior art.

Figure 2 is a combined block and schematic diagram of a resonant inverter for use with a gas discharge lamp or the like.

Figure 3 is an equivalent schematic diagram of the resonant circuit and gas discharge lamp of Figure 2.

10 Figure 4 is a schematic diagram of a first illustrative embodiment of preferred resonant inverter circuitry utilising resonance mode starting at the fundamental frequency of the excitation signal and parallel resonance mode operation at the fundamental frequency of the excitation signal.

S: Figure 5 is a schematic diagram of a first illustrative current sensing circuit for use 15 with the circuitry of Figure 4.

0 Figure 6 is a circuit diagram of a second illustrative current sensing circuit for use with the circuitry of Figure 4.

Figure 7 is a circuit diagram of an illustrative embodiment of another preferred resonant inverter circuitry utilising harmonic mode starting and fundamental resonance mode operation.

Figure 8 is a circuit diagram of a further illustrative embodiment of the resonant inverter circuitry utilising resonance mode starting and series resonance mode operation.

1733100ODOCinja s I II I- *0* Figuro 9 is a circuit diagram of a further illustrative embodiment of the resonant inverter circuitry utilising harmonic mode starting.

Figure 10 is a graph of the ringing signal which will occur across the gas discharge lamp to effect the firing thereof in the circuitry of Figure 9.

Figure 11 is a graph of the voltage occurring across Ihe gas discharge lamp of Figure 9 during operation thereof-- that is, after the firing thereof by the voltage waveform of Figure Figure 12 is a circuit diagram of a further modification of the resonant inverter circuitry incorporating illustrative sense circuitry for sensing the voltage across the gas S 10 discharge lamp of the circuitry of Figure 9.

*e *Figure 13 is a block diagram of an off-line power inverter.

Figure 14A is a circuit diagram of a full-wave rectifier for use with the power inverter of Figure 13.

Figures 14B and 14C are voltage waveforms occurring at different points in the 15 rectifier of Figure 14A.

Figure 15 is a block diagram of an off-line resonant inverter utilising an integrated circuit controller circuit.

Figure 16 is a schematic diagram indicating possible current flow paths in the power inverter of Figure 13 in response to a person inadvertently contacting one of the inverter output terminals and the inverter chassis with the load disconnected.

Figure 17 is a simplified schematic diagram of the circuitry of Figure 16.

Figure 18 is a schematic diagram corresponding to that of Figure 16 and including an output transformer for the power inverter.

17331-00 DOC/ija I I I_ -6- Figure 19 is a simplified schematic diagram of the circuitry of Figure 18.

Figures 20 and 21 are schematic diagrams of illustrative sensing circuits for use with the current limiting circuitry.

Figure 22 is a block diagram of an illustrative connection of the sensing circuitry of Figure 21 with the power inverter of Figure 13 where possible locations of relays for disabling the inverter are illustrated.

Figure 23 is a schematic diagram illustrating how the power inverter according to Figure 13 may be used to drive a fluorescent lamp.

Figure 24 is a schematic diagram corresponding to Figure 23 and further 10 illustrating the dangerous condition that may exist when a person is in contact with one of the output terminals of the inverter and earth ground while the fluorescent lamp is disconnected.

Figure 25 is a schematic diagram corresponding to Figure 24 and further i1i: illustrating sensing circuitry for disabling, if necessary, the controller for the power inverter.

Figure 26 is a circuit diagram showing direct connection of the control circuitry of the present invention to the resonant inverter circuit of Figure 2.

Figure 27 is a circuit diagram corresponding to Figure 26 but showing the control circuitry of the present invention connected to the resonant inverter circuit by an optocoupler.

Figure 28 is a circuit diagram of the control circuitry of the present invention.

Figure 29 is a graph of the waveform applied to the current sense terminal of the UC2843 by circuitry associated with the control circuitry of the present invention.

17331-00.DOC/mja L -7- DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Reference should be made to the drawings, where like reference numerals refer to like circuit elements and where several embodiments of circuitry are described for starting and operating gas discharge lamps utilising fundamental and harmonic resonance modes.

Although the invention is directed toward a control circuit, the preferred embodiment is made up of three major circuit sections which will be described separately with reference to the Figures briefly described above. These circuit sections are: Resonant Inverter Circuitry, Current Limiting Circuitry, and Control

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6J *j 733 1.00 DOC/mja I Resonant Inverter Circuitry A block diagram of a resonant inverter utilizing the integrated circuit (IC) SG2525 is shown in Figure 1. The combination of CT2 and RT2 determines the oscillator frequency of the IC. A resistor R4 is usually required between the terminals P15 and P13. A resistor divider comprising resistors R5 and R6 determines the amount of DC voltage applied to the non inverted terminal (pin 2) of the operational amplifier contained in the SG2525 integrated circuit. This voltage, in turn, sets the magnitude of the duty cycle of the output pulses from pin 14 and pin 11 of the SG2525. Depending on circuit requirements, an impedance Z2 is necessary between the inverted terminal 15 (pin 1) and the compensation terminal (pin 9) of tha SG2525 for loop stability of the IC.

Output signals from pin 11 and pin 14 periodically and alternately turn Q2 and Q3 on ard off. Thus, when Q2 is on, Q3 is off, and when Q2 is off, Q3 is on.

During the time when Q2 is on, energy flows through Q2 and the resonant inductor LR to charge the resonant capacitor CR. Then, when Q2 is off but Q3 is on, stored energy from CR flows back through LR and Q3.

With this arrangement, if the pulse repetition 25 frequency is identical with the resonance frequency of the LC (LR and CR) network, the circuit can be described as a resonant inverter.

An efficient and economical ballast configuration based on a resonant inverter technique is shown in Figure 2. In Figure 2, LR and CR form a resonant circuit and the lamp Ti acts as a load across CR.

Figure 3 is a circuit diagram equivalent to the Figure 2 connections of LR, CR, aid Tl, where the impedance of load TI is RL. The respective impedances of the L_ -4circuit parameters of Figure 3 can be described as follows: For the load, the impedance is RL, for the resonant capacitor, the impedance is 1/jw(CR) -jXCR and for the resonant inductor, the impedance is jw(LR) jXLR. Here, j is the complex number and w 2(fr) X. fr is the excitation frequency. At resonance, XCR XLR. Further, fr 1/w (LR. CR.) In the equivalent circuit shown in FIgure 3, under the resonance condition, the voltage across CR or RL depends on the quality or Q-factor of LR and CR, and value of RL. This is true because, at resonance, j'.RjXCR 0, that is, the impedances offered by the induccor and the capacitor are mutually cancelled. In 15 the present application, RL is replaced by the lamp T1.

Initially, before the lamp T1 fires, it offers an infinite impedance ;hat is, no current flow therethrough) and as a result the voltage across CR or T1 (Figure 2) continues to grow. However, once the 20 voltage across T1 reaches the lamp firing potential, the la'np T1 fires and offers much lower impedance. At this instance, due to the lamp chracteristic, the voltage across T1 clamps down to the normal lamp operating potential and stays there. This is a 25 convenient and reliable mechanism for: starting and operating a fluorescent lamp.

During normal operation, the current through the resonant inductor LR is equal to the vector sum of the current through the resonant capacitor CR and the current through the load or the lamp T. This is true, because, during the normal operation the lamp T can be considered mostly a resistive load and, as a result, the current through the capacitor CR will have degree phase difference, with respect to the lamp

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current. Thus, the current through LR, which is also the total circuit current, can be described as, 1 LR Total (i2 p i2CR) During normal operation, the voltage across the resonant capacitor is the same as the voltage across the lamp, Vlamp. Thereby, the current through CR is, iCR, running=Vlamp XCR. During starting, before the lamp fires, the current through the capacitor CR is determined by the ratio of the lamp firing potential to the impedance of CR. That is, iCR, firing vlamp, firing *o

XCR

Moreover, during starting, iCR, firing equals the total load current, which is circulating between CR and LR through the power switches Q2 and Q3. For this reason, if the lamp firing potential is very high, depending on XCR, a very large amount of circulating current can flow through Q2 and Q3 before the lamp fires. This large circulating current during starting may exceed the maximum rated current through Q2 and Q3 and thereby, may destroy Q2 and Q3.

The novel and improved resonant inverter circuitry 'of the present invention will now be described in detail. In a first embodiment as illustrated in Figure 4, resonance mode starting (at the fundamental frequency (fr) of the excitation signal) and parallel resonance mode operation (also at the fundamental frequency fr) are effected utilizing two separate inductors, L1, L2, or a single inductor with two sections L1 and L2 connected to a lamp T1 and capacitors C1 and C2. C1 is much smaller than C2.

;j e r_ C Moreover, the component values are chosen such that (L1 L2) C1 Li (CI C2). Excitation frequency (fr) is the same as the natural resonance frequency of (LI L2) C1 L1 (Cl C2) combinations. During normal operation (after the lamp has fired), the switches Sl and S2 are closed and thus the L1 (CI C2) combination is utilized. In this case, as explained earlier, iLR iTotal 2Lamp i2CR) and iCR v.1IM X(C1 C2) On the other hand, during starting (that is, before firing) S *xc P ,CR, firing yLam.frn XC1 since the (L1 L2) C1 combination is used at this time. Since C1 is much smaller than C2, the impedance offered by C1 is much greater than the impedance offered by (CI C2), for the same excitation frequency As a result, during starting while S1 and S2 are 20 open, the current through the capacitor C1 cal. be made very small while voltage across T1 reaches the firing potential. Hence, the current circulating through the inverter circuit including power switches Q2 and Q3 (Fig. 2) is maintained, during starting, at a value less than the maximum ratings of Q2 and Q3.

After the lamp fires, the switches Sl and S2 are closed by, for example, sensing current through the lamp and using this sense signal to activate a switch that will close Sl and 52, for example, a relay.

Current sensing can be accomplished conveniently by using a sense resistor (RS) that is placed in series IP D

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with the lamp T1 as shown in Figure 5. Current through T1 can also be sensed by using a conventional current transformer (CT) as shown in Figure 6 where the Fig. and Fig. 6 sensing circuits may also be used in the other embodiments of the invention.

In an example of this first embodiment, assume L1 1.8mH, L2 =3.6mH, C1 0.005 uF, C2 0.01 uF and fr 30 kHz. Accordingly, the natural resonance frequency of the (LI L2) Cl combination or the LI (Cl C2) combination is 30 kHz. Since for the 30 kHz excitation frequency, the impedance of C1 is 1.06 k ohm and the impedance of C2 is 353 ohms, it can be seen that the starting current can be effectively limited to value less than the maximum ratings of Q2 and Q3 of Fig. 2.

15 In a second embodiment of the invention, as also illustrated in Fig. 4, harmonic mode starting (at a harmonic (fn) of the fundamental fr of the excitation signal) but parallel resonance mode operation (at the fundamental frequency fr) are effected. In this case, 1/2 (L1 L2) C1 fn is utilized during starting where fn n x fr. Depending on the values of (LI L2) and C1, the natural resonance frequency of the circuit can be .ade equal to any higher harmonic frequency (fn) of the excitation frequency (fr).

25 During starting, the voltage C1 developed across Cl is dependent on the values of (L1 L2) and C1 and their quality. Thereby, the right value and quality omponents should preferably be selected. Examples of preferred components are polypropylene capacitors, as will be further discussed below.

In an example of this second embodiment, assume L1 -1.9 mH, L2 1.2 mH, C1 0.001 uF, C2 0.012 uF, and fr 30 kHz. Accordingly, the natural resonance frequency of (L1 L2) Cl combination is 90 kHz. On the other hand, the natural resonance frequency of L1 (Cl C2) combination is 30 kHz.

i( L I Harmonic mode starting and resonant (fundamental) mode operation can also be effected utilizing the circuitry of Figure 7. In this third embodiment fn 1/2 (L1.C1) and fr 1/2 (LI (Cl C2) where S2 is open during starting and closed during operation of the lamp.

In a fourth embodiment of the invention, resonance mode starting and series resonance mode operation is shown in Figure 8. In this case C1 is much much greater than C2, so that when considering C1 in series with C2, the effect of C1 can be neglected. Then, one can choose, fr 1/2 (L1 L2) C2 1/2 )L1 Cl).

During starting, inductors L1 and L2 with C2 form the resonance circuit that resonates at the excitation frequency. After the lamp starts, the switch S1 closes, and L1 and C1 forms the resonant network. The effect of C2 can now be ignored where, in this mode, the lamp T1 is in series with C1 and L1. Since C2 can 20 be made very small in value, current flow through through C2 (and thus power switches Q2 and Q3) can be kept very small. Moreover, during starting, the high impedance of C2 at fn is such that a firing voltage sea* sufficient in magnitude to fire the lamp can readily be developed across this capacitor.

In an example, of this fourth embodiment, assume L1 1.8 mH, Cl 0.015 uF, L2 4.6 mH, C2 0.005 uF, and fr 30 kHz. C1 is 30 times higher than C2, thus, the capacitance offered by the C1 and C2 series combination is 0.00048 uF. The natural resonance frequency of 0.0048 uF and (LI L2) is 90 kHz. On the other hand, the natural resonance frequency of L1 and t_ C1 combination is 30 kHz.

Depending on the quality and the values of L1, L2, Cl and C2, Figure 8 can also be arranged for: 1) resonance mode starting but non-resonance series operation, 2) harmonic mode starting but series resonance mode operation and 3) harmonic mode szarting and non-resonance series operation.

In a fifth and most preferred embodiment of the invention, harmonic mode starting and non-resonance operation are utilized as shown in Figure 9. In this embodiment, fn nxfr 1/2 (L1 Cl).

a.

Thus, depending on the quality or Q-factor of the 0 resonance inductor L1 and the resonance capacitor C1, 15 during starting, voltage across C1 can be increased to a very high level by choosing low loss L1 and C1 and by resonating them at harmonics higher than the fundamental. That is, by keeping the excitation i frequency (fr) fixed, the resonant network is so chosen 20 that it resonates at the nth harmonic frequency, (fn).

As an example, this embodiment can be used in the circuit of Figure 1 where the sensing circuits of Figs.

5 or 6 are not required. Assume T1 is a commercially available 250 watt High Pressure Sodium (HPS) lamp. It 25 typically requires approximately 2,500 peak voltage to "ooe start. Once the lamp is fired, the operating potential across the lamp is only 100 volts. Lamp firing voltage and operating voltage waveforms are shown in Figures and 11. Let the excitation frequency fr 30,000 Hz and Vin 360v. Then, for LR 0.26 mH and CR 0.0043 uf, the resonance frequency, fn 1/2 (LR CR) 150,000 Hz, which is the fourth harmonic of the fundamental frequency of 30,000 Hz.

As can be seen in Figure 10, when the Figure 9

AN'T

\1- Ytjy P -C I I I C II 1 circuit is excited with the fundamental frequency signal fr, the circuit will ring with the largest peak occurring at the natural resonant frequency of the circuit that, is the fourth harmonic. Although the third harmonic peak does not exceed the lamp firing potential, the fourth harmonic does, as can be seen in Figure 10, and of course fires the lamp.

Thus harmonic mode starting is advantageous because there is a rapid build-up of voltage such that at the natural (or resonant) frequency of the circuit, the lamp firing potential can be easily exceeded.

Moreover, the circuit impedance is typically such in harmonic mode starting that the average power flow can be kept within the maximum rating of the power switches Q2, Q3, for example.

Thus, at the resonant frequency of 30 kHz of the 'excitation signal, the impedances are LI 49 ohms and Cl 1.233 k ohms for the example given above for the Figure 9 circuit. However, at 150 kHz the impedances of LI and C1 are the same, namely, 245 ohms. In other words, since the natural resonance frequency of a 0.26 mH inductor and a 0.0043 uF capacitor combination is 150 k Hz, at the natural resonance frequency the impedance of LI must be equal to the impedance of CI so that they cancel each other. Thereby, in this example, when LI and Cl are excited by a lower multiple of 150 kHz frequency source, that is a 30 kHz source, the excitation will result in various frequency contents see.

over one 30 kHz frequency period. This is shown in figure 10. Note that the period of 30 kHz frequency is, 1/f 33.3 microsecond. The frequency content which includes 150 kHz frequency will have the highest amplitude because, at 150 kHz the impedance of LR is equal to CR but opposite in magnitude so that they cancel each other and thereby a large current can flow through the circuit. However, as can be seen from v /21

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1 Figure 10, this current flow occurs during only a fraction of one period of 33.3 microsecond. Thereby the average power flow per period is small.

The amount of current flow and thereby the voltage growth across C1 can be further controlled by incorporating a sense network as shown in Figure 12.

Accordingly, a high impedance resistor divider network (Ri R2) placed across Cl, senses voltage which is then rectified by the diode Di. This rectified signal can now be used to interrupt the frequency generator (SG2525 in Fig. 1) which generates fr. The interruption of the frequency generator via the soft start pin is further described in the current limiting circuitry section below.

15 The Q-factor or the quality of the inductors and 4 the capacitors should be good in order for harmonic mode starting to be effective not only in the embodiment of Figure 9 but in the other harmonic mode starting embodiments. The quality of an inductor depends primarily on the magnetic core material, resistance of the winding, skin depth associated with the high frequency excitation, etc. Poorly designed high frequency inductors can cause core saturation, and excessive heat dissipation. On the other hand, the 25 quality of a capacitor depends on its construction, such as, frequency response characteristic of the dielectric film, associated effective series resistance leakage current characteristics, high frequency ripple current capability, etc. Also, the voltage that can be applied across a capacitor without dielectric breakdown varies with frequency. In this regard, a polypropylene capacitor would be preferred over a polyester capacitor, for example.

Thus starting (or firing) of the lamp occurs in an harmonic mode. The operation of the lamp in the Figure 9 (or 10) embodiment after firing is effectively a nonpsaqg~r 1 "C JI resonant mode, since, upon lamp firing, most of the current through C1 switches to the path through the lamp. At this time, the inverter circuit is effectively constituted by the switches Q2 and Q3 and the series connected LI and T1.

As described above, with respect to Figure 4, other embodiments of the invention, after harmonic mode starting, switch to a resonance mode of operation after firing as opposed to the non-resonance mode of operation of Figure 9. These other embodiments of the invention also realize the advantages of harmonic mode starting as described above with respect to Figure 9.

Current Limiting Circuitry 0 4* The current limiting circuitry of the present 15 invention will now be described in detail with particular reference to Figures 13 through A block diagram of an off-line power inverter is shown in Figure 13. Switch 17 is an input section for AC power. Power line protection circuitry section 18 20 includes a fuse, etc. EMI section 19 comprises conducted electro-magnetic interference (EMI) suppression circuitry. Here, L3 is a common mode inductor, L4a and L4b are differential mode inductors, Y1 and Y2 are equal value capacitors for limiting leakage current, to earth ground where the values of Y are such the high frequency EMI generated by the inverter are shunted to earth ground while the lower frequency AC signal is not so shunted.

Rectifier section 20 comprises half or full wave rectification circuitry. Ripple voltage is filtered in filer section 21. The DC voltage is converted to a high frequency by a high frequency inverter and control circuitry as shown in section 22. Isolation PgPBIIACsllS~-. ~BY II II -C -4 transformer section 23 is optional, and provides a high frequency transformer for voltage isolation, step-up, step-down or for multiple output secondary voltages.

In operation, potential difference between the neutral AC line and the earth ground (EG) is very low. However, the potential difference between the live AC line and the earth ground (EG) is the full AC voltage. For 120V AC input and for a full wave rectific.tion case as illustrated in Figure 14A, the voltage between the lead and the earth ground, and voltage between the lead and the earth ground are shown in Figures 14B and 14C, respectively.

High frequency power inverter circuitry 22 may preferably comprise the SG2525-based resonant inverter '15 circuitry previously described with reference to Figures 1 through 12. For example, a block diagram of an off-line resonant inverter utilizing the integrated circuit (IC) SG2525 is shown in Figure 15. However, the off-line high frequency power inverter disclosed herein is not limited to use with the resonant inverter circuitry described previously. The off-line high frequency power inverter can also be constructed using power inverter topology other than resonant inverter topology. For example, push-pull topology, half bridge 25 topology, and others can be used.

In the circuit of Figure 15, when a resistor Rp is placed between the inverter output terminal A or B and round, current will flow between them. The magnitude of current flow will depend primarily on the following: a) with respect to ground, the magnitude of the high frequency AC voltage that appears at the terminal A or B; b) the value of the resistor (Rp) placed between A or B and ground; c) the amount of parasitic capacitive coupling (Cp) between high-frequency circuitry, wires and D PC I II L I1__I C LI- l

I

grLounded case, as discussed below and illustrated in Figure 16; and d) the values of the Y capacitors used in the EMI section 19.

In the case of a transformer isolated load, the current flow will be determined by the construction of the transformer. For example, electrostatic shielding between primary and secondary winding, capacitive coupling (Cw) between these two windings, etc., will play major roles.

Possible current flow paths between the terminals A or B and the ground G are shown in Figures 16 and 18 where Figure 18 includes an isolation transformer placed between the inverter output and the load.

15 Figures 17 and 19 are simplified equivalent circuits of Figures 16 and 18, respectively. In these simplified cases, the effects of bridge rectifier diode drop voltages are neglected.

With resistor Rp in place, the high frequency voltage developed across A and G or B and G is also reflected between the points G and P or between G and P where P is circuit ground. Thus, by placing a sensing circuit between G and P or, Z and P the amount of current flow through Rp can be detected.

A simple resistor sensor circuit is not suitable in the circuitry of Figure 13 because, during normal operation, a continuous high voltage pulsating DC potential exists between G and P or, G and P The frequency of this pulsating high voltage DC is determined by the input AC, as discussed hereinbefore with respect to Figures 14A, 14B, and 14C. However, if such pulsating voltage is not present, a simple resistor circuit would be suitable.

On the other hand, high frequency AC voltage sensing can be accomplished by a capacitor and v I Ri C resistors combinations as shown in Figures 20 and 21.

The circuit of Figure 21 converts the high frequency AC signal into a DC signal. In either case, the amount of sense voltage VS is determined by: the inverter frequency Rp, CS, RS1, and RS2.

The impedance (XCS) offered by CS is given by, XCS 1/(2w.fi.CS). As an example, assume fi 30,000 Hz, input line frequency fac= 60 Hz, CS 0.0033 microFarads. Then, at the inverter frequency, XCS 1607 Ohms. But, at the input AC frequency, XCS 803,500 Ohms, which is 500 times higher.

As a consequence, the 60 Hertz AC input signal will be attenuated 500 times compared to a 30,000 Hertz AC signal. Thus, for the circuits of Figures 20 and 15 21, one can easily detect the high frequency signal SI even though a continuous 60 Hertz pulsating DC signal exists between points G and P or G and P The high frequency signal that is detected by the circuits of Figures 20 and 21 is a function of the high frequency current that is flowing between power !inverter output terminal and ground, when the resistor SRp is placed between them. Thus, the detected signal can be used, for example, to turn on a relay or some other switch to disable the power inverter output 25 (Figure 22) temporarily or permanently in order to avoid that current flow. The relay can be placed between any of the sections shown in the circuit, i.e.

'in any location indicated by an X.

In another and preferred embodiment of the current limiting circuitry of the present invention, either of the sensing circuits of Figures 20 or 21, for example, may replace either the Y1 or the Y2 capacitor of Figure 13 where preferably the Y2 capacitor would be replaced with one of the sensing circuits. Assuming the Y2 capacitor is replaced, the value of CS of Figures 20 or 21 could preferably be exactly the same as the V1 u~ap---l--19 r bL-lr- remaining Y1 capacitor. In particular, if the Y2 capacitor were replaced by ,-he sensing circuitry of Figure 20, the earth ground portion of the Figure circuitry would correspond to the earth ground portion of the Figure 13 circuitry while the terminal 24 of Figure 20 would correspond to the terminal 26 of Figure 13. Thus, in this embodiment, the sensing circuitry serves not only its sensing function as described above, but also serves the EMI suppression function formally performed by the replaced Y1 capacitor.

Further, the detected signal via the circuits described by Figures 20 and 21 can also be used to regulate or limit current between the inverter output and ground when they are short circuited or connected 15 by a resistor. As an example, refer to the resonant o inverter of Figure 15. As discussed above, the *o 0 resonant inverter can drive a load such as a fluorescent lamp Ti. This is shown in Figure 23.

During installation or removal of a lamp a person can accidentally be in contact with terminal A and the grounded inverter case simultaneously. In analyzing this situation, the person can be replaced by an equivalent resistor of 500 ohms, as shown in.Figure 24.

According to Underwriters Laboratories Inc., USA, .0 25 safety standards UL 935, Paragraph 20.5, when a 500 ohm resistor is placed between the terminal A and ground, then the maximum acceptable peak current through the 500 ohms resistor must be limited to 43.45 milliamperes, when the inverter frequency is 10,000 Hertz or more. This corresponds to a maximum peak voltage of 21.7 volts across the 500 ohm resistor. By using the detection circuits of Figures 20 or 21, one can easily achieve this goal.

Figure 25 shows one such detection circuit connected to the resonant inverter circuit described previously. In Figure 25, the values of CS, RS1 and RPEIL lll~e -PI I-I- -s I I -22- RS2 are preferably chosen such that, as soon as the peak voltage across Rp reaches 21.7 volts, the voltage that develops between the base and emitter of a transistor Q4 is enough to turn on the transistor where soft start capacitor 24 is connected across the collector and emitter of Q4. Turning Q4 on causes a pull-down of the soft start pin 8 of the SG2525 IC, This, in turn, causes an immediate shut-down of the output drive pulses emanating from pin 11 and pin 14. Power inverter switches Q2 and Q3 then stop functioning. In this situation no current flows through Rp, and Q4 turns off. But, when Q4 turns off then SG2525 starts working again and turns on Q2 and Q3. Current starts .flowing through Rp and turns on Q4 again as soon as the voltage across Rp reaches 21.7 S* 10 volts, and the cycle continues. Shut-down of the IC SG2525 could also be accomplished in a similar manner by applying the signal to the shut-down pin 10 of the IC instead of to i pin 8.

Control Circuitry The control circuitry of the present invention will now be described in detail with a S 15 particular reference to Figures 26 through 29.

FirJt, the interface between the control circuitry of the present invention and the 0 resonant inverter ballast described above will be explained. Referring now to Figure 26, the new and improved pulse generating circuit is shown generally at 42 (this circuit will be described later in full detail). The output 43 of this 17331 WO flO(*Am; L h ~s J lit I circuit is connected to the base of an output transistor 44. The collector of an output transistor -4 is connected to non-inverting input NI (pin 2) of the SG2525 IC, while the emitter of output transistor 44 is connected to ground. An integrating capacitor 46 is connected between the non-inverting input NI and ground. The pulse generating circuit 42 preferably generates a variable duty cycle, square wave pulse train at a fixed frequency greater than 1 kHz.

The output pulses at output 43 control the charging of integrating cap citor 46. When pulse generating circuit 42 produces a pulse at output 43, the voltage applied to the base of transistor 44 turns on transistor 44, allowing current to ilow from the 15 collector to the emitter of the transistor 44. Because the collector of transistor 44 is connected to the capacitor 46 and the non-inverting input NI, and since the emitter of transistor 44 is connected to ground, a pulse from pulse generating circuit 42 effectively 20 grounds the integrating capacitor 46, tending to discharge the capacitor 46. When output 43 is not producing a pulse, transistor 44 is turned off, nd integrating capacitor 46 tends to charge to the level e of the voltage drop across variable resistor R6 as determined by the voltage divider comprising resistor R5 and variable resistor R6.

The voltage at non-inverting input NI (pin 2) ,varies with the duty cycle of the pulses at output 43.

Since the output 43 produces a series of pulses at high frequency, the pulses produce a periodic pull up and down of the DC level across integrating capacitor 46.

The integrating capacitor 46 integrates over time the DC level shift produced by the pulsed output 43, so that for a given pulse duty cycle, a continuous DC voltage appears at non-inverting input NI (pin The DC voltage at non-inverting input NI (pin 2) will vary IPrPb 91"1P ss I Irl I I I ~u with the duty cycle of the pulsed output 43 in the following manner. As the duty cycle increases, the capacitor 46 will be grounded for a relatively greater portion of time, and the voltage at non-inverting input NI (pin 2) will be reduced. Conversely, as the duty cycle of pulses at output 43 is reduced, the voltage at non-inverting input NI (pin 2) will be increased.

Because the voltage level at non-inverting input NI (pin 2) controls the apparent brightness of load T1, those skilled in the art will immediately appreciate that the light output of load T1 can be adjusted by varying the duty cycle of the pulses at output sJ.

Thus, a novel and unique method of controlling a solidstate dimming ballast by varying the duty cycle of a 15 pulsed input has been disclosed.

Figure 27 shows a preferred embodiment of the circuit of Figure 26 wherein the output transistor 44 is replaced by a conventional opto-isolator 48. The opto-isolator 48 comprises a light-emitting diode (LED) 50 and a phototransistor 52. The light-emitting diode is connected between output 43 and ground. The phototransistor 52 has its collector connected to noninverting input NI (pin 2) and its emitter connected to ground.

The phototransistor 52 turns on in response to light 25 emissions from LED 50, which operates in response to the pulses from output 43. This embodiment thus operates in substantially the same manner as the 'embodiment shown in Figu' 26. However, the optoisolator 48 electrically isolates ti resonant inverter circuitry from the pulse generating circuitry 42. The resonant inverter circuitry may contain large voltages and current, and as will be seen, controls for the pulse generatxng circuit 42 will be hardled by human operators. Therefore, this electrical isolation provides a substantial safety benefit.

The circuit and operation of the novel pulse

"U

4 IC k ~C generating circuit 42 will now be described in detail.

As shown in Figure 28, the pulse generating circuit 42 comprises a power supply section 54, a reset section 56, a delay section 58, an overcurrent section 60, a pulse control section 62, a brightness control section 64, and a variable duty cycle frequency source The variable duty cycle frequency source 65 may preferably be an UC2843 integrated circuit manufactured by Motorola, although other integrated circuits could be used or a circuit could be constructed to perform the necessary functions. The operation of the frequency source 65 is described in detail in Motorola publications which will be familiar and accessible to those skilled in the art. However, the functions of 15 ihe pins used in this circuit are described in Table 1 in sufficient detail to permit those skilled in the art to understand the circuit and to practice the invention disclosed.

MMUSIAW ~li~~IT cY LI---l I IL cs_.

Pin Connections of UC2843 Frequency Source PIN NAME 1 Compensation 2 Inv. Input 3 Current Sense 0 0.

*00 0 0 0 4 OSC

DESCRIPTION

Voltage may be applied externally to vary the duty cycle of the pulses.

Not Used (connected to ground).

Inhibits pulse output if more than one volt is applied externally.

Provides sawtooth wave output with frequency depending on external circuitry.

Connected to ground.

Produces variable duty cycle pulse output with frequency depending on exturnal circuitry connected to OSC terminal and duty cycle depending on voltage applied to Compensation terminal.

Power supply (+12v DC).

Reference voltage output (5.1v DC).

e a a aa e Ground 6 Output 7 Vcc 8 Vref TABLE 1 Referring again to Figure 28, the power supply section 54 comprises a transformer 66, a full-wave AJ3 I~IPVC_ ICP 1---~311 N .27 bridge rectifier 68, a capacitor isolation diode and a smoothing capacitor 72. The power supply section 54 is preferably also provided with a conventional three-terminal 12 volt voltage regulator 84 and an associated capacitor 86. The voltage regulator 84 has an input terminal 88, an output terminal 90, and a ground terminal 92.

Alternating current input from an AC source 74 is connected to the primary coil of transformer 66. The turns ratio of transformer 66 is selected with reference to the voltage of AC source 74 so that 12 volts AC is produced on the secondary coil. Full-wave bridge rectifier 68 is a conventional device. The rectifier 68 has two input terminals 75 and 78 and two output terminals 80 and 82. The two terminals of the secondary coil of transformer 66 are connected respectively to input terminals 75 and 78 of rectifier 68. Output terminal 80 of rectifier 58 is connected to circuit and Earth ground, while output terminal 82 is connected to the anode of isolation diode 70 and provides a rectified 12 volt DC output thereto. The cathode of diode 70 is connected to the input terminal 88 of regulator 84 and to the positive terminal of smoothing capacitor 72. The negative terminal of smoothing capacitor 72 is connected to both circuit ground and Earth ground.

cThe output terminal 90 of regulator 84 is connected to Vcc (pin 7) of variable duty cycle frequency source 65, and ground terminal 92 is connected to ground. The capacitor 86 is connected between the output terminal 92 of regulator 84 and ground. The voltage regulator 84 compensates for variations in the voltage of AC source 74, thus stabilizing the 12 volt DC power provided to the integrated circuits of frequency source 65. A stable voltage supply for frequency source 65 is necessary to avoid variations in the pulse signal output 43 of the frequency source Preferably, the 12 volt DC regulated output at output terminal 90 of regulator 84 will be used as the DC source 24 connected to Vcc of the pulse width modulator 4 (shown in Figure 26). In this way, the entire circuit may be controlled by a single power switch (not shown in the drawings). This switch may be any conventional switch and may be installed in the power supply circuitry in a number of ways which are conventional and will be immediately apparent to those skilled in the art.

The brightness control section 64 comprises a variable resistor 94 and a voltage divider resistor 96.

15 The variable resistor 94 is connected between the compensation pin (pin 1) of frequency source 65 and ground. The voltage divider resistor 96 is connected between Vref (pin 8) of frequency source 65 and the compensation pin (pin 1) of frequency source 65. Vref (pin 8) of frequency source 65 provides a constant 5.1 volt DC signal. Thus, the variable resistor 94 and resistor 96 form a voltage divider so that, as the variable resistor 94 is adjusted, the voltage applied tc the compensation pin (pin 1) of frequency source will vary. As described in the table of Figure 29, ti voltage on the compensation pin (pin 1) of frequency source 65 controls the duty cycle of the pulses 'produced at output 43, the duty cycle determining the brightness of the load T1 as described previously with reference to Figure 26.

The power supply switch.previously described may be integrated with the variable resistor 94 in a manner well known in the art.

The delay section 58 comprises a PNP transistor 98, a resistor 100, capacitor 102, and resistor 104.

The emitter of transistor 98 is connected to the I~ r I,_r Icompensation terminal (pin 1) of frequency source while the collector of transistor 98 is connected to ground. The base of transistor 98 is connected to one terminal of resistor 104, the other terminal of the resistor 104 being connected to the output terminal 82 of bridge rectifier 68. The positive terminal of capacitor 102 is connected to the base of transistor 98, while the negative terminal of capacitor 102 is connected to ground. Resistor 100 is c..-nected between the base of transistor 98 and ground.

As will be seen, the delay section 58 provides novel and uniquely advantageous operation because, in operation, the delay section 58 suppresses transmission of the dimming signal 43 at power-up. With the dimming 15 signal suppressed by delay section 58, the load T1 (shown in Figure 26) is started at full brightness.

Full-brightness starting is essential for two reasons: First, full-brightness starting prolongs the life of the fluorescent tubes. Second, fluorescent tubes may 20 not start at all if power is not provided for the full duty cycle.

The operation of delay section 58 to suppress the dimming signal 43 will now be described in detail.

When no power is applied to the circuit 42 from AC source 74, the transistor 98 will conduct fully, thus effectively grounding the compensation terminal (pin 1) of frequency source 65. When the compensation terminal is grounded in this manner, a zero duty cycle at output 43 is selected. As explained previously, the brightness of the load T1 (shown in Figure 26) varies inversely with the duty cycle of the pulsed output 43.

A zero duty cycle of the pulsed output 43 corresponds to full brightness at the load T1 (shown in Figure 26).

Therefore, when the transistor 98 is fully conductive, the load T1 will be at maximum brightness.

When power is applied to the circuit 42, the 1--slllI

I

capacitor 102 will charge according to a time constant determined by the values of resistors 100 and 104 and capacitor 102. As the capacitor 102 charges, the transistor 98 will be rendered less conductive, until the transistor 98 ceases to conduct. When the transistor 98 ceases to conduct, the delay section 58 will have no effect on the voltage at the compensation pin (pin I) of frequency source 65. The voltage at the compensation pin (pin 1) of frequency source 65 will then be controlled entirely by the brightness control section 64.

Thus, when power is applied to the circuit 42 and the resonant inverter solid-state ballast circuit (shown in Figure 2) the delay section 58 will initially inhibit any dimming of the load T1 (as shown in Figure regardless of the setting of variable resistor 94 (the brightness control). The load T1 will "start" at full brightness. After a brief period of time, the delay section 58 will cease to inhibit 20 dimming and the load T1 will dim to the level selected by means of variable resistor 94. An important feature of the present invention is that the fluorescent lamp T1 does not come on at full brightness and then suddenly become dim; the steadily increasing voltage 25 across capacitor 102 as it charges reduces the conductance of transistor 98 steadily over a brief period of time. The voltage at the compensation pin ,(pin 1) of frequency source 65 will therefore increase steadily from zero to the level determined by the setting of variable resistor 94. As a result, the fl.uorescent lamp T1 will come on at full brightness, and then dim to the preset level in a smooth and pleasing manner.

Of course, the length of the delay produced by delay section 58 can be adjusted by changing the value of resistors 100 and 104 and capacitor 102 in C_ I 3/ accordance with well-known time constant principles.

During a power failure, fluorescent lamp T1 will be extinguished. If the power failure is brief, the capacitor 102 may retain its charge, so that delay section 58 will not provide the desired full-brightness startup and transition to the set dimming level as described. As explained previously, the lamp T1 may not start at a low-brightness setting, and even if the lamp T1 does start, its life will be shortened by a low-intensity startup. Reset section 56 operates to reset the delay section 58 during a power failure, preparing delay section 58 to operate properly when power is returned to the circuit.

Reset section 56 comprises a diode 106, resistor 108, PNP transistor 110, filter capacitor 112, and voltage divider resistors 114 and 116. The anode of diode 106 is connected to the base of delay section transistor 98, and the cathode of diode 106 is connected to one terminal of resistor 108. The other S 20 terminal of resistor 108 is connected to the emitter of transistor 110. Resistor 108 preferably has a small value, in the range of 5-7 Ohms. The collector of transistor 110 is connected to ground. The positive terminal of filter capacitor 112 is connected to the 25 base of transistor 110, while the negative terminal of •coo the capacitor 112 is connected to ground. One terminal of resistor 114 is connected to the output terminal 82 of full-wave bridge rectifier 68, while the other terminal of the resistor 114 is connected to the base of transistor 110. Resistor 116 is connected between the base of transistor 110 and ground.

**Resistors 114 and 116 together form a voltage divider which determines the voltage at the base of transistor 110. The values of resistors 114 and 116 are chosen with reference to the values of resistors 100 and 104 so that transistor 110 does not conduct L C_ C while AC power source 74 is providing power to the circuit 42. The value of capacitor 112 is chosen with reference to the values of resistors 114 and 116 so that, if power is removed from the circuit, capacitor 112 will discharge through resistor 116 in about 1 millisecond.

If a failure of power from AC source 74 occurs, the reset section 56 operates as follows: The voltage at the base of transistor 110 falls to zero within one millisecond as the capacitor 112 discharges through resistor 116. Because delay section capacitor 102 is still charged, the voltage at the emitter of transistor 110 is considerably greater than zero. Therefore, transistor 110 begins to conduct, effectively shorting and discharging the delay section capacitor 102. Thus, the reset section 56 quickly prepares the delay section 58 so that the fluorescent tube T1 may be restarted automatically at full brightness as described previously.

It should be noted that the diode 70 is provided in the power supply section 54 to isolate the reset section 56 from filter capacitor 72 so that, during a power interruption, filter capacitor 72 will not discharge through the reset section 56 and prevent proper operation of the reset section 56.

0. The pulse control section 62 determines the frequency of the pulsed output 43 and limits the m" aximum duty cycle of said output pulses. Pulse control section 62 ccmprises NPN transistor 118, frequency set capacitor 120, frequency set resistor 122, resistor 124, variable resistor 126, and resistor 128. The base of transistor 118 is connected to the oscillator terminal (pin 4) of frequency source The collector of transistor 118 is connected to Vref (pin 8) of frequency source 65, and the emitter of transistor 118 is connected to one of the two terminals I -n 33 of resistor 124. The other terminal of resistor 124 is connected to one of the two terminals of variable resistor 126. The other terminal of variable resistor 126 is connected to the current sense terminal (pin 3) of frequency source 65. The resistor 128 is connected between the current sense terminal (pin 3) of frequency source 65 and ground. The frequency set resistor 122 is connected between the oscillator terminal (pin 4) of frequency source 65, and Vref (pin 8) of frequency source 65. The frequency set capacitor 120 is connected between the oscillator terminal (pin 4) of frequency source 65 and ground.

The oscillator terminal (pin 4) of the frequency source 65 will produce a ramp signal (sawtooth wave) with a DC offset, the frequency of the ramp signal depending on a time constant determined by the values of frequency set resistor 122 and frequency set capacitor 120. Preferably, the resistor 122 and capacitor 120 will be chosen so that the frequency of 20 the ramp signal is greater than 1 kiloHertz.

The ramp signal from the oscillator terminal (pin 4) of frequency source 65 is transmitted by means of the transistor 118 to a voltage divider formed by resistors 124 and 128 and the variable resistor 126.

The operation of these voltage divider resistors causes the signal on the current sense terminal (pin 3) of frequency source 65 to be at all times a percentage of the varying voltage at the oscillator terminal (pin 4) f S"of frequency source 65. The percentage or fraction of 30 the oscillator terminal output that will appear at the current sense terminal (pin 3) of frequency source is determined by the setting of variable resistor 126.

The peak voltage output of the oscillator terminal (pin 4) of an UC2843 integrated circuit is approximately 2.8 volts; the minimum voltage output offset) is 1.2 volts. Preferably, resistors 124 and 128 and the ^Ca I~L~ setting of variable resistor 126 are chosen so that the peak voltage applied to the current sense terminal (pin 3) of frequency source 65 will be approximately 1.4 volts.

The frequency source 65 will inhibit generation of a pulse signal at output 43 whenever the voltage applied to the current sense terminal (pin 3) is greater than about one volt. Therefore, the effect of applying a high frequency ramp signal to the current sense terminal (pin 3) is to suppress pulse generation during a portion of each ramp cycle.

Referring now to Figure 29, a portion of a typical ramp signal 131 as applied to the current sense terminal (pin 3) of frequency source 65 is shown. The ramp signal 131 has a peak voltage Vmax. As explained previously, due to the action of the voltage divider comprising resistors 124, 126, and 128, Vmax is a fraction of the peak voltage of the ramp signal at the oscillator terminal (pin 4) of frequency source 65. As stated, Vmax is preferably about 1.4 volts. In the drawing, a single ramp cycle 129 takes place over a time period encompassing a first time period 130 and a secznd time period 132. Tin the time period 130, the voltage of the ramp signal rises from 0.6 volts to one volt; during this period 130, the frequency source is not inhibited form transmitting a pulse at output 43. Of course, whether a pulse is transmitted by requency source 65 and the actual duration of any pulse transmitted are determined by brightness control section 64, delay section 58, and reset section 56 in o* .e the manner explained previously. During the second time period 132, the voltage of the rankp signal 131 applied to the current sense terminal (pin 3) exceeds one volt, and the frequency source 65 is inhibited from producing any signal at output 43. Thus, the application of the ramp signal 131 to the current sense I ~slr c terminal (pin 3) limits the maximum duty cycle of the pulses at the output 43. In the preferred embodiment described, with Vmax 1.4 volts and with the output 43 inhibited when voltages greater than 1.0 volts are applied to the current sense terminal (pin 3) of frequency source 65, the maximum duty cycle of pulses at output 43 is 50%. Referring back to Figure 27, it will be apparent th,t limiting the pulsed output 43 to. a 50% duty cycle places an upper limit on the amount of dimming of the load Ti. This limitation is desirable because dimming the load T1 excessively may shorten the life of the load T1 and will in some cases result in an unpleasant flickering effect when the load T1 is a fluorescent tube.

Referring now to Figure 28, the maximum duty cycle of the pulsed output 43 can be adjusted by means of variable resistor 126, and may be set at a value other than 50% as dictated by the requirements of the consumer or the design parameters of the resonant 20 inverter ballast (shown in Figure 27).

The overcurrent section 60 is a protective circuit that disables pulsed output 43 if excessive current is drawn from the output 43. Overcurrent section comprises a resistor 134 and a diode 136. The anode of 25 diode 136 is connected to an output reference 45 which may serve as the ground reference for the output signal 43. The cathode of diode 136 is connected to the current sense terminal (pin 3) of frequency source The resistor 134 is connected between the anode of diode 136 and ground. The diode 136 prevents transmission of the ramp signal at the current sense terminal (pin 3) to the output reference As explained previously, the output 43 of frequency source 65 is inhibited when more than one volt is applied to the current sense terminal (pin 3).

The voltage drop across diode 136 is approximately 0.6 I L I -36volts; therefore the output 43 will be inhibited i_ the voltage at the anode of diode 136 is greater than 1.6 volts. This condition will occur when the voltage drop across resistor 134 is greater than 1.6 volts. Preferabl', resistor 134 may be a 4.7 Ohm resistor, so that when more than 0.34 Amperes of current is drawn from output 43, the voltage drop across resistor 134 will be greater than 1.6 volts and the output 43 will be disabled.

Thus, the overcurrent section 60 prevents damage to the circuit of the present invention.

Of course, each resonant inverter ballast connected to the pulse generating circuit 42 will draw current, so that there is a practical limit to the number of resonant inverter circuits that can be controlled by a single pulse generating circuit 42. The pulse 10 generating circuit as disclosed will drive approximately 16 ballasts without exceeding 0.34 Amp current draw from output 43. However, if it is desired to control more than 16 ballasts using one pulse generating circuit 42, an NPN power transistor can be used to increase the fanout capability of the circuit 42. The base of the power transistor may be connected to the output 43, while the collector of the power transistor is connected to a DC power source such as that provided at Vcc (pin 7) of frequency source 65. The pulse signal output to the ballasts is then taken at the emitter of the power transistor. The fanout capability of the circuit 42 can be expanded to allow control of almost any number of ballasts using well-known techniques.

Although the invention has been described with reference to specific examples, it will be appreciated by those skilled in the art that it may be embodied in many other forms. More particularly, the scope of the invention is defined in the following claims and is not limited to the specific details provided in the above description.

*B 17331-00 DOC/Imja

Claims (4)

1. A control circuit for controlling a power circuit, wherein the power circuit supplies power variably to a fluorescent lamp load in response to the DC level of a variable control input voltage applied to a control input, said control circuit comprising: a brightness control input for setting a desired brightness of the load; control pulse generating means connected to the brightness control input for generating control pulses of variable duty cycle, the duty cycle of the control pulses varying with the setting of the brightness control input; and integrating means connected to the control pulse generating means for integrating 10 the control pulses over time to produce the variable control input voltage and provide the S* variable control input voltage to the power circuit control input.

2. A control circuit according to claim 1, wherein the control pulse generated means comprises a single integrated circuit pulse width modulator appropriately configured to genei.- said control pulses based on the setting of the brightness control input. C 15 3. A control circuit according to claim 1 or claim 2, further comprising delay means for providing a starting period during starting of the load, in which the delay means causes the power circuit to supply power to the load sufficient to start the load, regardless of the level selected by the brightness control input, thereafter allowing the power circuit to supply power to the load to provide the brightness level selected by the brightness control means, wherein at the end of the starting period the power circuit steadily modifies the brightness cf the lamp load until the load brightness matches the level selected by the brightness control input.

173.1100 DOC/mja a IL II -38- 4. A control circuit according to claim 1, further comprising delay means for providing a starting period during starting of the load, during which starting period the delay means increases the variable control input voltage to provide a voltage representative of brightness sufficient to start the load even though a power level selected by the brightness control input may not be sufficient to start the load, the delay means thereafter operating to steadily modify the variable control input voltage until said variable control input voltage represents the load brightness level selected by the brightness control input. 1, 5. A control circuit according to claim 3 or claim 4, further including reset means *10 responsive to a loss of power to the control circuit and operating to reset the delay means so that the delay means operates in accordance with its function when power to the control circuit is restored. *e 6. A control circuit according to any one of the preceding claims, fu-ther including limiting means to restrict the minimum load brightness level that can be selected by the S: 15 variable control input voltage. 7. A control circuit according to claim 6, wherein the limiting means includes adjustment means permitting variation of the minimum load brightness level that can be selected by the variable control input voltage. 8. A control circuit according to any one of the preceding claims, further including current limiting means for inhibiting the operation of the control circuit if current in excess of a selected value is drawn from the output thereof. 9. A control circuit of claim 1 wherein the power circuit supplie, alternating current power to the fluorescent lamp, the duty cycle of said alternating current power varying in

173111.00 UOC/mjt 9 -r b-rl C -39- response to the DC level of the variable control input oltage, with the duty cycle of the t ontrol pulses inversely related to the brightness level selected by the brightness control means, further comprising: delay means for providing a blocking period during starting of the fluorescent lamp wherein transmission of control pulses to the integrating means is blocked, the delay means thereafter allowing transmission of the control pulses so that the brightness of the lamp is set at the level selected by the brightness control input, wherein at the end of the blocking period the delay means operates to steadily increase the duty cycle of the control pulses until said control pulse duty cycle produces the lamp brightness lev'el SI 10 :elected 'y the brightness control means. S* 10. A control circuit substantially as herein described, with reference to Figures 26 to 29. DATED this 23rd Day of SEPTEMBER, 1996 ETTA INDUSTPIE INC. 15 Attorney: JOHN B. REDFERN FeLow Institute of Patent Attorneys of Australia of SHELSTON WIAERS a. 91- 0OCIn~ja V I. ABSTRACT A solid state, resonant inverter (SG 2525) ballast for a gas discharge lamp (T1) operating at a selected frequency. The ballast includes reactance elements C 2 L, and L 2 connected to the lamp (T1) such. that depending upon which of the reactance elements C 2 L, and L are connected in circuit with the inverter (SG 2525) the ballast forms either a natural resonant frequency with the lamp power irequency or one of the harmonics of the lamp power frequency. Se C o o• ~s