AU679609B2 - A manufacturing method for high quality discrete level displays - Google Patents

Description

1 -1- A Manufacturing Method and Apparatus for High Quality Discrete Level Displays The present invention relates to the manufacture of Flat Panel Displays such as liquid crystal displays.

The background of the present invention will now be described with reference to Fig. 1 which illustrates the basic operation of a liquid crystal display.

Although the present invention will be described in relation to a liquid crystal form of display, it will be obvious that the present invention is not limited thereto and is applicable in the construction of any flat panel display whereby it is necessary to set up various field between two substrates.

Flat panel displays such as a liquid crystal displays, plasma displays, and thin-film electro-luminescent displays normally operate on the principle of setting up a predetermined electric field setween two substrates, with the space, between the substrates normally being filled with liquid crystal material, phosphor material, gas or other substances depending on the form of the display.

Referring now to Fig. 1 there is illustrated the basic operation of a ferroelectric liquid crystal display device (FLCD) 101 which comprises a pair of electrode plates (normally consisting of glass substrates coated with a transparent form of electrodes) 102 and 103 and a layer of ferro electric liquid crystal having molecular layers 104 disposed between and perpendicular to the electrode plates. The ferroelectric liquid crystal assumes a chiral smectic C phase or an H phase and is disposed in a thickness thin enough (e.g: 5 microns) to release the helical structure inherent to the chiral smectic phase.

When an electric field E (or 105 exceeding a certain threshold is applied between the upper and lower substrates 102, 103 liquid crystal molecules 104 are oriented in accordance with the electric field. A liquid crystal molecule has an elongated shape and shows a refractive anisotropy between the long axis and the short axis. Therefore, if the ferroelectric liquid crystal device 101 is sandwiched between a pair of crossed polarisers (not shown) mounted on the glass substrates 102, 103, there will be provided a liquid crystal light modulation device.

When an electric field 105, exceeding a certain threshold, is applied, the liquid crystal molecules 104 are oriented to a first polarisation orientation state 106. Further, when a reverse electric field is applied, the liquid crystal molecules 104 are oriented to a second polarisation orientation state 107. These orientation states are further retained as long as the electric field which is applied does not exceed a certain threshold in the reverse direction.

In order to create the required electric field between the substrates it is necessary to create a series of conductive tracks on each of these substrates. These conductive tracks can then be driven by control circuitry so that the required electric fields are created.

The conductive tracks creating the electric field are normally formed on the substrate by means of a transparent electrode portion, often connected to a metallic INALIBEIMACRO08iPJT -9b~ _b~p~ I opaque portion. These portions can be laid out in long parallel strips on each substrate, with the parallel strips on one substrate being laid out at right angles to the strips on a second substrate, such that, at their intersection there is formed pixel cells. Hence by driving the two conductive strips in a predetermined manner, the pixel itself can be controlled. Such methods for the layout of pixels on Flat Panel Displays are known to those skilled in the art.

In designing a panel pixel layout for the display of images, it is desirable to maximise the brightnes.s and contrast with which the image is displayed. In liquid crystal forms of displays the luminosity is often achieved by means of a back light and hence it is desirable to maximise that portion of the light able to transfer through the display.

However, to ensure a high contrast ratio, it is often necessary to ensure that 100% of the light is controlled as it passes through the panel device. In liquid crystal type devices, this can be ensured by either using areas that are opaque to the transfer of light or, as will be further described hereinafter, are controlled by portions of the display that allow the light to pass depending on the state of certain control signals.

In order to create a fully functional display that operates within a set Oi predetermined standards and which 100% of the light is controlled by the panel, it is often necessary to layout complex patterns involving the interaction of the various portions of the substrates, being the colour filter layers and the various electrode layers.

Additionally, it is necessary to ensure that the alignment of the various substrates is accurate to a very low tolerance (in the order of a few microns for high quality flat panel displays) as slight misalignment of one panel with respect to another may cause the size of to transparent areas of eaich pixels to be altered thereby creating unwanted artifacts in the i final image to be displayed.

25 The formation of the metallic opaque portion of the substrate often proceeds in a manner akin to that used in the construction of metal electrodes on semi-conductor type devices. In this process a metal layer of aluminium or molybdenum is laid out over the surface of the substrate, then a layer of photoresist is laid over the .aluminium before being exposed through the required corresponding mask for creation of the desired metal tracks. Subsequent etching takes place leaving the required conductive metal track layout.

In the construction of devices using metal layers, the use of Molybdenum (Mo) has been preferred for the formation of the relevant circuitry. Molybdenum is preferred due to its superior patterning properties and planarisation properties.

Aluminium is also a possible candidate for use in patterning of the metal layer. The resistivity of aluminium is 0.027 I/fm at 25°C, whereas the resistivity of molybdenum is 0.0547 uzQm at 25 0 C, Hence a metal conductive layer made of aluminium is almost twice as conductive as one made of molybdenum. However, hillock or spike formation in aluminium, as a result of stress release during differential thermal expansion of.aluminium IN;\LIBERMACRO0a;PJT

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lc IJ -3creates a serious problem, in comparison with other substance, used in the formation of the substrates of the display, which currently prevents the use of aluminium.

In particular, as the distance between substrates is in the order of 1-2gm, a hillock in the metal layer of this order or greater may result in substrate separation beyond the specifications of the panel resulting in a defective panel.

Additionally, the construction of high definition displays requires the creation of a large number of pixel patterns in an exacting manner under extreme conditions of cleanliness. Therefore, expensive and advanced semiconductor type processing techniques are often required in the construction of such display devices and an error in just one of these techniques can render a display unusable. Although it is unlikely that the occurrence of errors can be totally overcome, it is desirable to provide a simple display construction in order to reduce the overall total possible number of errors occurring and thereby improve the overall yield.

It is an object of the present invention to provide an alternative form of display construction which alleviates some of the aforementioned difficulties.

In accordance with one aspect of the present invention, there is provided a flat panel display substrate, said substrate including: a multiplicity of opaque conductive areas laid out in a first predetermined pattern in a first plane; a transparent insulating layer positioned over said first plane and insulating areas of said opaque conductive layer from adjacent areas of said opaque conductive layer; and a transparent electrode layer overlying said insulating layer and including electrode *see portions laid out in a second predetermined pattern, each of said portions being connected :*Goes to a predetermined part of a corresponding one of said opaque conductive areas and o 25 extending away from said first plane and in a direction towards an adjacent opaque conductive area, while remaining electrically isolated from said adjacent opaque conductive area by means of said transparent insulating layer, said transparent electrode portions extending in said direction to, or beyond, a predetermined part of said adjacent G. .0 opaque conductive areas, wherein said first and second patterns edge abut when viewed in the display direction whilst being electrically insulated from each other.

"In accordance with another aspect of the present invention, there is provided a method of manufacture of a liquid crystal display comprising: °o providing a first substrate and a second substrate, creating an opaque conductive layer on each of said substrates in a predetermined pattern, creating a transparent insulating layer over portions of said opaque conductive layer on said substrate, said transparent insulating layer having a number of apertures defined therein,

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'lglSll() I~ L -4creating a transparent electrode layer on said transparent insulating layer and connected to portions of said opaque conductive layer through said apertures of said transparent insulating layer.

The preferred embodiment of the present invention will now be described with reference to the accompanying drawings in which: Fig. 1 illustrates a schematic perspective view of a ferroelectric liquid crystal device; Fig. 2 is a plan view of a portion of a panel constructed in accordance with the preferred embodiment of the present invention; Fig. 3 is a plan view of a single pixel of the preferred embodiment; Fig. 4 illustrates the number of red levels obtainable with the preferred embodiment; Fig. 5 illustrates the number of green levels obtainable with the preferred embodiment; Fig. 6 illustrates the number of blue levels obtainable with the preferred embodiment; Fig. 7 illustrates a graph of th,; aperture of a colour panel constructed in accordance with the preferred embodiment with respect to the panel size; Fig. 8 is a cross-section of a pixel through the line A-A of Fig. 3; Fig. 9 is a plan view of the upper substrate of a simplified form of a panel constructed in accordance with the preferred embodiment; Fig. 10 is a plan view of the lower substrate of a simplified form of a panel constructed in accordance with the preferred embodiment; l m"""Fig. 11 is a plan view of the upper and lower substrate of a simplified form of a 25 panel which has been properly aligned; Fig. 12 is a plan view of the upper and lower substrate of a simplified form of a panel which is not properly aligned; Fig. 13 is an enlarged view of a portion of the pixel of Fig. 8; Fig. 14 illustrates the effect of an aluminium hillock being formed within the metal layer of the preferred embodiment.

I* Fig. 15 is a cross sectional view of the construction of the colour filter layer of the preferred embodiment; sFig. 16 is a plan view of the colour filter mask used in construction of the colour filter layer; Fig. 17 is a cross sectional view of the construction of the data level metal layer of the preferred embodiment; Fig. 18 is a plan view of the data level metal mask used in construction of the data metal layer; tNAuLIBEIMACROs:PJT L II ~-LLI I I C ~1 Fig. 19 is a cross sectional view of the construction of the data level dielectric formation of the preferred embodiment; Fig. 20 is a plan view of the data level dielectric mask used in the construction of the data level dielectric layer; Fig. 21 is a cross sectional view of the construction of the data level transparent electrode layer of the preferred embodiment; Fig. 22 is a plan view of the data level transparent electrode mask used in the formation of the data level transparent electrode layer; Fig. 23 is a cross sectional view of the construction of the data level surface layers of the preferred embodiment; Fig. 24 is a plan view of the common level metal mask used in the construction of the common level metal layer; Fig. 25 is a plan view of the common level dielectric mask used in the construction of the common dielectric layer of the preferred embodiment of the present invention; Fig. 26 is a plan view of the common level electrode mask used in the construction of the common transparent electrode layer of the preferred embodiment of the present invention; Fig. 27 illustrates a graph of TAB connection pitch verses diagonal panel size; Fig. 28 is a cross sectional view of a single pixel of the preferred embodiment and illustrates the improved contrast ratio of the preferred embodiment; Fig. 29 is an enlarged cross sectional view of a portion of the panel of Fig. 8.

S• Fig. 30 is a plan view of a portion of a panel in accordance with the alternative i embodiment; 4 2ialr nFig. 31 is a plan view of the sub-pixel dimensions for a single pixel of the alternative embodiment; *Fig. 32 illustrates the number of blue levels obtainable with the alternative embodiment; C Fig. 33 is a plan view of the colour filter mask used in construction of the colour !filter layer of the alternative embodiment; Fig. 34 is a plan view of the data level metal mask of the alternative embodiment; Fig. 35 is a plan view of the data level dielectric mask used in the construction of the data level dielectric layer of the alterrative embodiment; memo, Fig. 36 is a plan view of the data level segment electrode mask of the alternative embodiment; Fig. 37 is a plan view of the common level metal mask used in the construction of the common level metal layer of the alternative embodiment; Fig. 38 is a plan view of the common level segment dielectric mask used in the construction of the common dielectric layer of the alternative embodiment; and, [N;\LIBEIMACRO08:PJt I I I -6- Fig. 39 is a plan view of the common level electrode mask used in the construction of the c" "-mon transparent electrode layer to the alternative embodiment.

i ring now to Fig. 2, there is shown a portion of a liquid crystal device 101 according to the preferred embodiment of the present invention. The liquid crystal display 101, is designed for the high resolution display of full colour images and includes a substantial number of common lines and corresponding common transparent electrodes 111 laid out on a first substrate. The common lines are laid substantially perpendicular to a large number of data drive lines and data transparent electrodes 110 formed on a second substrate.

Common sizes for high resolution computer displays included displays having 1024 distinct rows of pixels each divided into 1280 distinct columns of pixels, with one set of lines formed on a first glass substrate and the other set of drive lines formed on a second glass substrate. At the intersection of these rows and columns are formed pixels indicated by the designation 112. In the preferred embodiment of the present invention, each pixel of the display has more than one drive line and more than one common line associated with it.

In particular, with reference to Fig. 3, wherein there is shown the single pixel 112, each pixel 112 has three common drive lines 113, 114, 115 with the outer two common drive lines 113, 115 being optionally electrically connected together. Similarly each pixel has multiple data lines, divided into red data drive lines 116, 117, gren data drive lines 118, 119 and blue data drive lines 120,121.

The data drive lines are treated symmetrically for each colour and, as such, only the operation of the red data drive lines 116, 117 will now be described. The red data drive lines 116, 117 control the transparent electrode areas 122 127. The first red data drive line 116 controls the transparent electrode areas 122,124,126 and the second data drive line controls areas 123, 125 and 127.

Preferably, each transparent electrode area 122-127 which is able to be independently driven, forms a binary area relationship with other areas. For example, area 124 is equal to 1 square unit, area 125 is 2 square'units, areas 122 and 126 together 30 form a 4 square unit area, and areas 123 and 127 form an 8 square unit area. Therefore, in driving combinations of the drive lines and the common lines, and remembering that the outer drive lines 113 and 115 are preferably electrically connected together, 16 possible levels for each primary colour of the pixel 112 can be achieved or 163 4096 different colours per pixel 112. Of course, by forming such a binary relationship in illumination areas, substantially more levels can be achieved than if the areas were to be all of the same size.

Referring now to Fig. 4, the 16 possible levels for the red primary colour of the pixel 112 are shown. Similarly Fig. 5 and Fig. 6 show the 16 possible levels for the green primary colour and the blue primary colour respective. i1. In combination, each.

IN:\LIBEIMACOO08lPJT -L 1 Ir 0* 0000 *000** 0* 0 0 0 *000 0* 00 0 -7pixel of the preferred embodiment is therefore able to display 4096 different possible colours.

Sub-Pixel Dimensions As mentioned previously, the display of images is normally in accordance with predetermined standards. For example, a standard used with CRT type displays in common use with computer terminals is to display images with a resolution of 1,280 pixels by 1,024 lines. An image that is stored with reference to the above display format can be displayed on a variety of display sizes, in a similar manner that television displays come in a variety of display sizes and yet all display the s,,mi -e fimage. The difference is in the actual size of each pixel.

In the preferred embodiment, different sized pixels can be achieved by altering the area of the transparent electrode areas. With reference to Fig. 3, elmensions A, B, C and D can be altered depending on the desired pixel size. Preferably the width of the metal lines are kept constant at 2011-m. Table A below shows the various sizes (in microns) of the dimensions A, B, C, D for different sized displays, with the measurement for the display measured along its diagonal and the dimensions of the relevant pixel areas shown to the nearest 0. 1 micron.

TABLE 1. Dimensions For Various Pixel Sizes______ Panel size Metal Dim. A Dim. B Dim. C Dim. D Inches. width (J.Lm) (microns) (microns) (microns) (microns) 15 (38) 20.0 12.5 25.0 34.5 69.0 16 (40) 20.0 14.'2 28.4 37.6 75.2 17 (44) 20.0 15.9 31.9 40.7 81.4 18 (44) 20.0 17.7 35.3 43.8 87.6 19 (45) 20.0 19.4 38.8 46.9 93.8 (51) 20.0 21.1 42.2 50.0 100.0 21 (53) 20.0 22.8 45.6 53.1 106.2 22 (56) 20.0 24.5 49.1 56.2 112.4 23 (58) 20.0 26.3 52.5 59.3 118,6 24 (61) 20.0 28.0 56.0 62.4 124.8 (64) 20.0 29.7 59.4 65.5 131.0 26 (66) 20.0 31.4 62.9 68.6 137.2 27 (69) 20.0 33.2 66.3 71.7 143,3 28 (71) 20.0 34.9 69.7 74.8 149.5 29 (74) 20.0 36.6 73.2 77.9 155.7 130 (76) 1 20.0 1 38.3 1 76.6 1 81.0 1161.9 For each pixel size, a certain portion of the F.71xel area will be devoted, to the opaque metal lines and a certain portion will be apportioned to the transparent electrode~

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0000 area. Referring now to Fig. 7 there is shown a graph of the percentage of the pixel area devoted to the transparent electrode area, and is therefore a measure of the relative aperture size of each pixel.

Referring now to Fig. 8 there is shown a cross-section 139 of a pixel of a liquid crystal display of the preferred embodiment taken thorough the line A-A of Fig. 3. In order to better illustrate the preferred embodiment, the approximate scale of the crosssection has been magnified in the vertical direction by a factor of approximately 10 in comparison with the horizontal scale.

This cross-section includes an upper 102 and lower 103 glass substrate. On each glass substrate is deposited polarising film 140, 142, which, dependent on the required driving mechanisms, can have either parallel or perpendicular polarising axes with respect to one another.

Layers deposited on the substrates are designed to create a transparent electrode portion for the particular transparent area required, in addition to a supply means for delivering a voltage source to the transparent electrode so that the required electric field can be set up betweefi the top substrate 102 and the bottom substrate 103, and so that the liquid crystal 104, sandwiched between the substrates, can be forced into its relevant bistable state.

As mentioned previously, the bistability is with respect to the liquid crystal's influence on the polarisation of light. Hence, light 158 is shone through the panel by means of a backlight (not shown), and is polarised by the bottom substrate polariser 142.

It then has its polarisation state changed depending on the bistable state of the liquid crystal 104, before passing through a second polarising film 140 which, depending on o the required driving arrangement, may have its polarisation axis at right angles to, or parallel to, the bottom substrate polariser 142. Hence, depending on the state of the crystal 104, which is preferably of a ferro electric liquid crystal type, the light will be either blocked or transmitted by the combination of the polarisers 140, 142.

The state of the liquid crystal 104 is altered, as previously mentioned, by setting up electric fields between the transparent electrodes of the top and bottom substrates.

Soo.

30 This is done primarily by means of intersecting portions of transparent electrodes being a top common transparent electrode 145 and a bottom data transparent electrode e.g. 154. These transparent electrodes can comprise a layer, approximately 0.7 Am thick of Indium Tin Oxide (ITO) connected to a 0.7 Am metal voltage supply line. The common level transparent layer 145 is connected to common metal layer 143 which include the common metal lines 113, 114, 115 of Fig. 3. The data or segment level transparent layer 154 is connected to the data level metal layer which includes the data metal lines 116 -121 of Fig. 3.

As will become more apparent with respect to the discussion of the manufacture of the display, the transparent common electrode layer 145 is insulated from an adjacent,

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-9common metal electrode 143 by means of a common dielectric layer 144. Additionally, it is necessary to insulate the common transparent layer from the liquid crystal itself.

This insulation can be provided by a 0.1 Axm insulation layer 148 made up of Tantalum Pentoxide (Ta 2

O

5 A 0.1 Am layer of Silicon Titanium Oxide (SiTiOx) 146 is then provided to smooth out any irregularities in the surface of the substrate. An alignment layer 147 comprising approximately 0.02 Am of polyamide is then formed with the alignment layer being formed by laying down the polyamide layer and then rubbing the surface thereof in one direction with velvet, cloth, paper etc.

The two substrates 102, 103 are held apart by 1.5 Am glass spheres 149. These spheres are shown elongated due to the scaled dimensions of the panel. Sphere densities in the order of 100 spheres per square millimetre are approPriate. The substrates are he! gether by adhesive droplets 150, so that between the droplets 150 and the spheres 149, the panel is kept in a static equilibrium with the thickness of the liquid crystal being of the order of 1.5 being the diameter of the spheres 149.

The bottom substrate is constructed in a similar manner to the top substrate and is based around a glass substrate 103. On one side of the glass substrate is placed a polarising film 142, designed to polarise light 158 coming from a backlight (not shown).

On the other side of the substrate is placed a series of colour filters 157, 159 and 160.

These filters comprise a 1.5 gm thickness of polyamide and a colour dye. The colour 20 filters are designed to filter the light 158 so that the corresponding emitted light is that of one of the primary colours of the pixel. The colour filters can be fabricated on either the common substrate 102 or the data level substrate 103. If the colour filters are placed on the common substrate, then the two substrates must be aligned to less then accuracy. If the colour filters are placed in their preferred position on the bottom data level substrate 103, then the two substrates will not require alignment as the colour filters will already be aligned with the various data metal layer lines 116 -121.

**In order to enhance the contrast of the display, the colour filters are separated by potions of the data level metal layer 116, 118, 120. Additionally, data level metal portions 117, 119 and 121 are also provided. The data level metal portions 116-121 of 30 Fig. 12 correspond to similar numbered data metal lines of Fig. 3. Each data metal portion 117-121 is in electrical contact with a corresponding transparent data electrode portion. By way of example, data metal portion 116 is in electrical contact with transparent data electrode portion 122 and data metal portion 117 is in electrical contact with transparent data electrode portion 123.

The transparent data electrode portions are insulated from neighbouring data metal control portions by means of a segment or data level insulating dielectric 155 which comprises 2Am polyamide, which ensures the electrical isolation of the various data columns. A similar technique is used to insulate the common metal layer 143 and

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3 p II I -Ip I I adjacent transparent common electrodes 145 of the common level layer via a corresponding common level insulating dielectric.

As described previously with reference to the top substrate 102, further portions include a 0 ltm Ta 2 0 5 insulation layer 153, a 0.1 Am SiTiOx smoothing layer 152 and a 0.02 pm polyamide alignment layer 151.

Alignment A substantial attribute of the design of the preferred embodiment is its alignment free properties which will now be discussed with reference to Fig. 9 to Fig. 12 which illustrate a simplified version of a 4 pixel per line by 6 lines of pixels FLCD device constructed in accordance with the principals outlined previously.

Referring now to Fig. 9, there is shown the data level metal layer 170 and the colour filter layer 171 of the data level substrate of the simplified FLCD display. The data level transparent electrode layer is not shown as it is not normally visible to the human observer.

Referring now to Fig. 10 there is shown the portion of the display comprising the common level metal substrate 172. Again the transparent electrode layer is not shown as it is not normally visible to the human observer.

Referring now to Fig. 11 there is shown a schematic form of the final simple display where the common metal layer has been overlaid on top of the data level layer and the two layers have been correctly aligned. With the preferred embodiment however, the need to achieve perfect alignment is eliminated as the two layers can move with respect to one anoAher. An example of a panel that is out of alignment is shown in Fig. 12. Here the common level layer 172 has been moved down relative to the data level layer 170. It can be seen from a comparison of Fig. 11 and Fig. 12 that there has 25 been no change in the pixel layout pattern of the two devices. Hence, for example, the two layers can be out of alignment in the order of lmm with no effect on image quality, due to the fact that the patterns on each of the substrates consist of simple straight parallel lines, with the final pixels being formed through the intersection of these lines, To achieve the alignment free construction of panels in accordance with the preferred 30 embodiment, the colour filter layer is on the same side as the data level layer.

Referring now to Fig. 13, there is shown a portion of the display device 139 around metal drive line 117. The dimensions of Fig. 13, although approximate, have not been exaggerated in the vertical direction. Ferroelectric liquid crysta' 104, is placed between the two substrates 102, 103. In practice, the distance between the two substrates must be strictly controlled by the silicon spaces and adhesive (not shown) such that the thickness of the liquid crystal is in the order of between 1 and 2 p.m.

Metal drive line 117 has, with prior art type devices, normally been constructed from Molybdenum (Mo) which has a resistivity of 0.0547 fuQm at 25 Aluminium. is [N:\LIBEIMACROO8:PJT ~B~L L L~s -11 also a possible candidate for use in creation of a metal layer 117. The resistivity of aluminium is 0.027 pQm at 25 C. Hence, a metal conductive layer made of aluminium would be almost twice as conductive as one made of molybdenum. However, aluminium is prone to hillock or spike formation as a result of stress release during differential thermal expansion of aluminium in comparison with other substances used in the creation of the display. This has generally negated its use in prior art forms of displays as te distance between the aluminium metal layer of one substrate and opposed layers of the second substrate was in the order of 1 to 2 tm and any aluminium hillock greater than this size would result in panel separation beyond specification or alternatively panel substrate shattering.

In the preferred embodiment, the 2 um wide di-electric polyamide layer 155 distances the metal layer 117 from the opposed substrate 102 by approximately 4 um.

This results in a substantial reduction in the likelihood of any aluminium hillock in data metal layer 117 causing panel separation.

Referring now to Fig. 14, there is shown an example of an aluminium hillock 180, approximately 3 um thick, formed in the data metal layer 117. As can be seen, the dielectric insulating layer 155 provides a "buffer zone" whereby the hillock 180 does not effect the opposed substrate 102.

SManufacturing 20 The manufacturing process used in the construction of the FLCD panel 104 will S:•now be described. The manufacturing processes r 'e display construction are very Ssimilar to those used in the construction or fabricaL.n of Very Large Scale Integrated Circuit Devices (VLSI) and familiarity with the .onstructions of such devices is e .s assumed.

25 The construction of a .LCD display begins with the two glass substrates.

Referring now to Fig. 15, the construction of the bottom glass substrate 103 will now be described.

Colour Filters 0After the surface of the substrate has been thoroughly cleaned, an aluminium 30 chelate coupling agent (I.t shown) can be applied to ensure the proper adhesion to the glass of subsequent layers to the glass substrate.

A spin coating process is then used to apply a 1.5 /m layer of photosensitive polyamide con'aining a primary colour die, which in the first case will be red. To remove residual solvents, the polyamide is pre-baked for approximately 10 minutes at 80 0 C. The photosensitive polyamide is then exposed using a pixel mask as shown in Fig. 16, with the aperture 167 corresponding to the area of the red colour filter 159 to be exposed. The polyamide layer is then developed leaving the red colour filter portions 159 of each pixel on the substrate 103. This first colour filter portion is then post baked to form a stable structure before the process is repeated for the green filter 159 and blue

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1 118 I-_IBIC-M~ -12filter 160, with appropriate masks (not shown) whose aperture is appropriately shifted by a one third pixel width.

Data Level Metal Layer Referring now to Fig. 17 the next portion of the display device constructed is preferably the data level metal layer 116-121, 156. The deposition of this metal layer occurs directly over the colour filters.

In the coustruction of devices using metal layers, the use of Molybdenum (Mo) has been preferred for the formation of the relevant circuitry. Molybdenum has been used i due to its superior patterning properties and planarisation properties.

As previously discussed with reference to Figs. 13 and 14, aluminum is preferably used in the data meal layer of the preferred embodiment due to its lower resistivity. The preferred embodiment is designed to reduce the effect of any hillock formation as a consequence of using aluminum.

The manufacturing method does not eliminate the formation of hillocks. However, by positioning the data t etal layer on top of the colour filter layer and covering the data metal layer with a 2pi/ planarised dielectric layer (to be described below), the affect of hillock formation can be significantly reduced as most of the hillocks will be absorbed within the dielectric layer. Of course, extremely large hillocks (greater than 3-4/m) will S still cause panel separation.

The deposition of a metal layer is well known to those skilled in the art of semiconductor circuit fabrication and an example process for such deposition will now .be described A 0.3tpm layer of a Aluminium and 0.5% Copper (AICu) alloy is first sputtered onto the surface of the substrate. Preferably the aluminium is planarised to a 0.09m .f 25 surface height difference. The sputtered aluminium layer is then primed for photoresist adhesion by spin coating a monolayer of hexamethyldisilazane (HMDS). A 11m layer of positive" toresist such as AZ1370 is then spin coated on top of the priming layer. The ;i photoresist is then pre-baked for 3 minutes at 90°C using an infia-red oven. The photoresist is then exposed using the pixel mask showri in Fig. 18, which comprises 30 simple vertical stripes corresponding to the various areas of the data metal layer 116- 121, 156. The photoresist is exposed to the metal mask at 35rrJ/cm 2 The photoresist can then be developed for 50 seconds at 23 0 C in 25% aqueous solution AZ-351 and 40% aqueous solution AZ-311. A development inspection can then o take place before the resist is stripped and any out of tolerance panels are either discarded or reworked. The photoresist can then be post-baked at 1500 C before the sputtered aluminium is wet etched in an agitated solution of 80% phosphoric acid, 5 nitric acid, 5% acetic acid and 10% water at 40°C for 2 minutes.

N:\LIBEIMACRO0O8PJT 'I L _L11 i -13- Finally the remaining photoresist is stripped using a low phenol organic stripper such as Shipley remover "1112A", leaving the data level metal layer 116 -121 on the bottom substrate 103.

Data Level Dielectric Layer Referring now to Fig. 19, there is shown the data level dielectric layer 155. This layer is formed from a simple photosensitive polyamide process. The processing steps that can be used to form this layer include the spin coating of a 2pm of a photosensitive transparent polyamide layer. Preferably a good planarisation is obtained through the use of a ester oligomer solvent with 50% resin content rather than the more usual PIQ polyamide acid method.

The use of the polyamide process will planarise the metal lines to approximately of their actual height. Conventional PIQ polyamide should not be used, as this will only planarise to approximately 75% of the height difference. This is a result of the line spacing being large and the metal aspect ratio being small.

The polyamide is then prebaked for 10 minutes at 80° C. The polyamide is then exposed using the mask as shown in Fig. 20, before being developed and post-baked to ensure that the final dielectric layer 155 takes the form as shown in Fig. 19.

Data Level Transparent Electrode Layer of Referring now to Fig. 21, there is shown the data level transparent electrode layer including portions controlling the red primary colour area 122, 123. This layer is formed by applying a transparent electrode such as ITO on the substrate 103.

Although a functional display could be produced with the data level transparent layer being formed initially on the colour filter layer and the data level metal layer being a formed on top of the data level dielectric layer, the preferred embodiment includes the 25 data level dielectric layer being created before the data level transparent layer. This has the advantage that the data level trnsparent layer is created very close to the liquid crystal portion upon which it operates. Hence the electric field created between an adjacent data level transparent electrode and a corresponding common level transparent electrode is substantially increased..

30 The process of formation of the data level dielectric layer includes the sputtering of indium and tin in an oxygenated atmosphere to initially form a 0.074m layer of ITO.

This layer of ITO is then primed, again by spin coating a monolayer of HMDS. On top of this layer is spin coated a 1/m layer of positive photoresist such as AZ1370. The photoresist can then be pre-baked, to remove solvents, for approximately 3 minutes at °C using an infra-red oven.

The photoresist is then exposed to the data level electrode mask 168 as shown in Fig. 22 at an energy of approximately 35mJ/cm 2 The photoresist is developed for seconds at 23 0 C in a 25% aqueous solution AZ-351 and a 40% aqueous solution AZ311.

The photoresist is then post baked at 120°C. The ITO is then wet etched and the. I1I4ALIBEINMACflo08PJT -14remaining photoresist is stripped using a low phenol organic stripper such as Shipley 'Remover 1112A' leaving the data transparent electrode layer connected to the data metal layer.

Surface Layers Referring now to Fig. 19, the surface layers can then be applied. This includes the sputtering of 0.1 lm of a tantalum pentoxide insulator, the application of 0.l/Am of silicon titanium oxide, the spin coating of 0.02A/m of polyamide which is then post baked and the surface rubbed. for the proper liquid crystal molecule alignment. Top Glass Substrate Referring initially to Fig. 8, the manufacture of the top glass substrate will now be described. The formation of the top glass substrate 103 occurs in the same manner as the bottom glass substrate hoWever, the top substrate does not include a colour filter layer. After the surface of the top substrate has been thoroughly cleaned, the common metal layer, the common dielectric layer, the common transparent electrode layer and the various surface layers are 'id down in the same manner as set out for the corresponding data level layers, with the common metal mask shown in Fig. 24, the common dielectric mask being shown in Fig. 25, and the common electrode mask is shown in Fig. 26.

Final Construction Referring again to Fig. 8, the final construction of the FLCD panel requires the placement of the silicon spacer spheres 149 between the panels. These can be sprayed on the data level substrate to a density of approximately 100 spheres per square millimetre.

Similarly, the adhisive droplets 150 are sprayed on the common substrate. An edge bonding adhesive (not shown) can then be applied to the perimeter of the panel before 25 they are joined together.

The adhesives can then be cured and the panel can be partially evacuated before being filled with helium. The helium can then be removed before the panel is filled with a ferro-electric liquid crystal material 104. The helium flushes out all other gases in the area between the two glass substrates and having a low* molecular weight, it is itself highly mobile,. Hence, when the panel is filled with liquid crystal material, the helium can be easily removed from the opposite end of the panel. Additionally, helium's low Y molecular weight allows portions of it to diffuse out all portions of the panel, leaving the space behind it filled with liquid crystal.

The final panel can then be tested to see if it is operational.

TAB Edge Connections Each pixel of the preferred embodiment includes 6 drive lines (2 for each colour) and 3 common metal lines. In a display having 1,280 pixels per line by 1,024 lines there will be (1,280 x 6) (1,024x 3) 10, 752 connections along the edges of a panel. These connections are implemented by the use of a tape automated' bonding '(TAB) INA\LIBEIMACROO PJT ~I II I:7L I 1 process whereby the driver chips can be connected to the substrate using ansiotropic connectors. Given that the number of connections is static for each panel and the size of each panel can be varied, the pitch required for each connection will vary with panel size. Referring now to Fig. 27 there is shown a graph of variation in TAB connection pitch versus panel size, with the required pitch decreasing with a decreasing size panel.

Referring now to Fig. 28, a particular advantage of the preferred embodiment is its improved contrast ratio which is provided without complicating the design of the panel.

Assuming that light 158 is projected through the panel substantially perpendicular to the substrates of the display 101, then all portions of the light are controlled by the display.

Portions are either blocked 164 by the various metal portions of the common level layer, or they are transmitted 165 through the liquid crystal 104 under the control of the liquid crystal bistable polarisation state which is in turn created by the relevant voltages on the bottom and top transparent electrode layers. As a result a high contrast ratio is maintained in the construction of the preferred embodiment.

Referring now to Fig. 29 there is shown a portion of the bottom substrate of Fig. 8 in magnification. It dan be seen from observation of the relevant masks for the data level layer that, on completion of the transparent data electrode layer, there is a '6000 gap between the ITO 122 of one portion of one of a data column and the ITO portion 2 123 of an adjacent column. Additionally, the ITO portion 122 is electrically insulated 20 from the common metal layer 117 of the neighbouring data column. The near overlay of a portion of the transparent electrode layer 154 and its neighbouring metal layer 117 is

•SO*

significant in controlling the light through the display to achieve a high contrast ratio.

The transparent electrode is insulated from the adjacent metal portion 117 by means of a ,2 i polyamide dielectric layer 155. However, the construction of the FLCD device may not be perfect in that the polyamide layer may have pinhole defects in an area 166 allowing the transparent ITO electrode 122 to come in contact with the neighbouring metal portions 117, thereby causing a short circuit between the two layers. Normally, this would result in the display being discarded as defective, however, by applyinga low ••impedance voltage between all the adjacent pairs of metal lines on each substrate the 30 portion of the ITO electrode in the pinhole defect area. 166, can be subjected to an excessive current and thereby 'evaporated', resulting in a breaking of the electrical connection, as, if there is a short circuit between adjacent lines, the current will be concentrated in the small region of ITO within the pinhole. This ITO is likely to be melted by such a high current concentration and separate from electrical contact with its adjacent neighbouring metal layer thereby hopefully eliminating this problem.

Alternative Embodiment Referring now to Fig. 30 there is shown a portion 174 of a display constructed in accordance with a second embodiment. The dimensions of a single pixel 175 are as shown in Fig: 31. In this alternative embodiment the size of each pixel 175 is definedto -16be 240/zm by 2 4 0Am. It will be evident from examination of Fig. 30 and Fig. 31 that the alteration of the layout for the alternative embodiment comprises removal of one blue segment or data drive lines (120 of Fig. The elimination of the blue drive line results in a reduced number of blue levels possible with a display constructed in accordance with the alternative pixel layout of Fig. 31. Referring now to Fig. 32, there is shown the four different possible levels of blue intensity.

The elimination of one blue drive line in the alternative embodinent has the advantage of increasing the transparent electrode area of each pixel 175, thereby increasing the overall possible luminance of the display. Additionally, the elimination of one data drive line also simplifies the construction of the display, reducing the probability of occurrence of errors rendering the whole display unusable. However, as a consequence of removing one of the blue drive lines, the number of possible blue levels has been substantially reduced. It has been found that a reduced number of blue levels does not substantially affect the quality of a colour image displayed using such a display.

This is thought as a result of the human eye's low luminance perception of blue.

The deletion of'one of the blue data drive lines requires various alterations in the masks used to create each pixel. The elimination of the blue data drive further line results in the introduction of asymmetrical patterns in the pixel layout which results in the display losing its relative substrate movement properties. The new masks are shown in Fig. 35 to Fig. 41. These masks are very similar to those used in the preferred embodiment, however the following aspects should be noted: e• The colour filter mask (Fig. 33) is of a different size for the blue filter (not shown).

The data level metal (Fig. 34), data level dielectric (Fig. 35) and data level S 25 electrode masks (Fig. 36) rs in only five data drive lines.

The common metal mask (Fig. 37), common dielectric mask (Fig. 38) and S_ •common electrode mask (Fig. 39) account for the reduction in the number of blue transparent areas.

The foregoing describes several embodiments of the present invention.

30 Modifications, obvious to those skilled in the art, can be made thereto without departing from the scope of the invention. In particular, application of the present invention to other forms of flat panel displays such as thin-film transistor displays, thin-film electroluminescent displays or plasma displays should be obvious to those skilled in the art on manufacture of such displays.

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Claims (19)

1. A flat panel display substrate, said substrate including: a multiplicity of opaque conductive areas laid out in a first predetermined pattern in a first plane; a transparent insulating layer positioned over said first plane and insulating areas of said opaque conductive layer from adjacent areas of said opaque conductive layer; and a transparent electrode layer overlying said insulating layer and including electrode portions laid out in a second predetermined pattern, each of said portions being connected to a predetermined part of a corresponding one of said opaque conductive areas and extending away from said first plane and in a direction towards an adjacent opaque conductive area, while remaining electrically isolated from said adjacent opaque conductive area by mer 3. of said transparent insulating layer, said transparent electrode portions extending in said direction to, or beyond, a predetermined part of said adjacent opaque conductive areas, wherein said first and second patterns edge abut when viewed in the display direction whilst being electrically insulated from each other.

2. A flat panel display as claimed in claim 1, further comprising a colour fiter layer formed so as to create a multicoloured display device.

3. A flat panel display device comprising a plurality of substrates, each substrate including a multiplicity of parallel conductive strip pairs, each of said conductive strip pairs comprising an opaque strip electrically connected to a transparent conductive strip, said device having at least a pair of said substrates formed in accordance with claim 1, one of which overlies the other and which are orientated to have said strip pairs substantially mutually perpendicular whereby said overlying perpendicular strip pairs define a rectangular pixel area defining grid for said display, and wherein the area of said pixel areas is substantially independent of any translational movement of said substrates.

4. A flat panel display device as claimed in claim 3, wherein a plurality of colour filter strips are provided on one of said substrates, with each colour filter strip overlying and being substantially co-extensive with a corresponding transparent strip portion.

A flat panel display device as claimed in claim 3, wherein said parallel conductive strips abut or substantially overlap adjacent parallel portions while being electrically isolated therefrom.

6. A flat panel display device as claimed in claim 3, wherein said parallel conductive strips substantially cover the whole area of the plane of their corresponding substrate.

7. A flat panel display substrate as claimed in claim 1, wherein the depth of said transparent insulating layer comprises a substantial extent of the expected depth of said opaque conductive areas or the location of any hillock formed thereon. IN IIWOVIMACROOAI Pjr -18-

8. A flat panel display substrate as claimed in claim 7, wherein the thickness of said insulating layer is substantially greater than the thickness of said opaque conductive areas.

9. A flat panel display substrate as claimed in claim 8, wherein said transparent insulating layer includes planarised portions on the top edges thereof, portions of said transparent electrode layer substantially covering said planarised portions of said insulating layer.

A method of manufacture of a liquid crystal display comprising: providing a first substrate and a second substrate, creating an opaque conductive layer on each of said substrates in a predetermined pattern, creating a transparent insulating layer over portions of said opaque conductive layer on said substrate, said transparent insulating layer having a number of apertures defined therein, creating a transparent electrode layer on said transparent insulating layer and connected to portions* of said opaque conductive layer through said apertures of said .transparent insulating layer.

11. A method of manufacture as claimed in claim 10, wherein said transparent insulating layer and said opaque conductive layer together substantially cover the plane of said substrate.

12. A method of manufacture as claimed in claim 10, wherein the depth of said transparent insulating layer comprises a substantial extent of the expected depth of said opaque conductive layer or the location of any expected hillock thereon.

13. A method of manufacture as claimed in claim 10, wherein the thickness of said insulation layer is substantially greater than said opaque conductive layer.

14. A method of manufacture as claimed in claim 10, further comprising applying a voltage between adjacent opaque conductive areas whereby any localised short circuit between said adjacent opaque conductive areas carries a localised current sufficient to eliminate said short circuit and render said short circuit non-conductive.

15. A method as claimed in claim 13, wherein.said voltage is from a low impedance voltage supply.

16. A method as claimed in claim 10, wherein said transparent insulating layer is formed from Indium Tin Oxide.

17. A method as claimed in claim 10, wherein said insulating layer comprises substantially 2pim polyamide.

18. A method of manufacture of the flat panel display substantially as hereinbefore described with reference to the accompanying drawings.

19. A flat panel display, substantially as hereinbefore described with reference to the accompanying drawings. INWa1UMACROM8PJT 19- DATED this EIGHTH day of MARCH 1995 Car~r) o k bush; Yi Vo Zv~ Canon- InfoGrmation Systems Researeh Australia PtyLt 11-TST Patent Attorneys for the Applicant SPRUSON FERGUSON sees :06*S a.. S .S10 ate a S 0 Of.. Abstract A Manufacturing Method and Apparatus for High Quality Discrete Level Displays A method is disclosed for the creation of flat panel discrete level displays (101) and, in particular for the creation of a ferroelectric liquid crystal display device, wherein each pixel (112, 175) includes multiple areas 124) which can be independently illuminated. The display device disclosed has an improved contrast as all areas of illumination 124) are strictly controlled to be in an on or off state. The display construction disclosed also includes a construction which reduces the effects of aluminium hillock formation (180) and the method of construction includes the elimination of short circuits between electrodes on the same substrate. V 6* O IN:\LIBEIMACROOB:PJT lllau~rsl~ r lyi