AU700380B2 - Method and apparatus for the enlargement of the range of the transmission channel between functional groups of an ISDN-user interface - Google Patents
Method and apparatus for the enlargement of the range of the transmission channel between functional groups of an ISDN-user interface Download PDFInfo
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- AU700380B2 AU700380B2 AU19449/95A AU1944995A AU700380B2 AU 700380 B2 AU700380 B2 AU 700380B2 AU 19449/95 A AU19449/95 A AU 19449/95A AU 1944995 A AU1944995 A AU 1944995A AU 700380 B2 AU700380 B2 AU 700380B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0435—Details
- H04Q11/0471—Terminal access circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/094—Range extender
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13034—A/D conversion, code compression/expansion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13094—Range extender
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13176—Common channel signaling, CCS7
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13202—Network termination [NT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13209—ISDN
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13298—Local loop systems, access network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13299—Bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1332—Logic circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13322—Integrated circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13333—Earth satellites
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1336—Synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13383—Hierarchy of switches, main and subexchange, e.g. satellite exchange
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/202—Network termination [NT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/205—Primary rate access
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/214—Phase shifted impulses; Clock signals; Timing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
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- H04Q2213/36—Synchronisation
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- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/381—Pair gain system
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- Computer Networks & Wireless Communication (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Telephonic Communication Services (AREA)
- Interface Circuits In Exchanges (AREA)
- Small-Scale Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Description
f 2 NT2, network termination 2: if present, the exchange or concentration function in the realization of a PBX (private branch exchange).
TE1, terminal equipment type 1: corresponds to the ISDN interfaces and works directly with NT1, or NT2.
TE2, terminal equipment type 2: is a conventional end apparatus with an analog interface.
For the feeding from the ISDN a TA (terminal adaptor), is necessary to establish the access to the ISDN.
This use reference configuration defines the necessary functions independently of technical details and establishes their relative position to one another. Between these functional groups, certain reference points are defined, which separate the functional groups from one another.
The reference point V is located between the exchange point and connection termination, the II.. 15 reference point U is located between the line termination and network termination, the reference point T is located between network termination 1 and 2, the reference point S is located between network termination and an end system type 1 and the reference point R is located between the terminal adaptor TA and an end system type 2. For the reference point U national standards exist and for the reference points S and T there are international standards.
S 20 At the interfaces of the ISDN participant connections a number of functions are to be performed. An So-interface, for example, must fulfil the following functions: 2 lines (copper) for each transmission direction; S• A gross transmission rate of the AMI coded signals in each direction of 192 Kbit/s; A net data rate (2B channels plus iD channel) of 144 Kbit/s (48 Kbits for synchronization and control); Step timing: derived from the bit stream which occurs at 192 Kbit/s; Octet timing: derived from 192 Kbit/s, equals 8kHz (for speech coding); Frame synchronization (realized through deliberate code violations for the purpose of recovery of the time division channels); D/echo channel: supports the orderly attachment of the TE device to the D channel; Activation and de-activation (the changeover between utilization and rest conditions).
Frame build-up and coding of the transmitted bytes are subject to a defined rule. In accordance with the rules of the HDLC, the information to be transported is built into one or more frames which always begin and end with a special bit sequence. According to rules established, procedures such as frame synchronization, super frame control, connection control, remote feed, and activation and de-activation are realized.
Regardless of a net side connection of ISDN terminal equipment or network terminations it is advantageous to extend the range of the transmission channel between functional groups of the ISDN participant connection (with reference to one or more ISDN basic connections So, or other interfaces) so that the information from a net can be transmitted over a longer distance.
However, the range achievable with conventional apparatus is significantly restricted because of the electrical properties of the ISDN interfaces and connection paths. For example, up to now, it has not been possible to operate an So interface over more than 1000m (point to point connection) or an Uk interface without inserting amplifiers, over more than 6 kilometers.
That means that the range of the transmission channel between functional groups of the ISDN participant connection with reference to one or more ISDN interfaces is limited.
eeoc In accordance with GB-A-2249927 a process is known to convert information of a lower data density into information of a higher data density. In accordance with this process the conventional pulse code modulation process according to ISDN is utilized and data of several 20 channels are transmitted in a bundled form through a primary multiplex process. The ISDN typical timing relationships are maintained. When extended transmission distances are required, the establishment of connections will break off and no communications will arise.
From ICC '84, LINKS FOR THE FUTURE, vol. 2, Amsterdam 1984, it is known to transfer from a U interface to several different S interfaces. The transfer function requires a corre- 4 25 sponding address scheme and the active utilization of the D channel and hence interference into the layer 2 information. All transfer functions are based on the typical ISDN data structure but the time multiplex process utilized is not suitable for long transmission distances.
In accordance with standard CCITT 1.400 the signal travel (signal delay) time, for example ubetween the functional units NT and TE, and back, is defined to be between 10 microseconds minimum and 14 microseconds maximum. This is primarily caused by the 2-bit frame shift which is necessary for time recovery (frame shift equals code violation as a signal for the beginning of a frame).
To detect a collision, the frame beginning (2 bits) must be detected within 70% of the signal travel time period: For 2 bits this equals 10.416666 microseconds and, with reply, equals 3.6458331 microseconds.
On the assumption of a wave attenuation of 7.6 dB per kilometer (for copper), the signal transfer time delay T 9 microseconds per km. From the following relationship t roundf/2 3. 6jis/2 I R =0.2km T 9pis/km one can determine the maximum range of the So connection. This calculation is valid for the case ofpoint-to-multipoint configurations. The calculation for the point-to-point configuration (no collision recognition) analogously yields 1 kilometer.
15 The time conditions for the transmission over a satellite channel do not change with respect to S the collision recognition. However, the signal transit time over a connection via a geostationary satellite (approximately 36,000 kilometers) changes. The signal transit time is 220 ms in one direction, and with reply, 440 ms. These time conditions show that a direct extension of the range of the transmission channels between functional groups of the ISDN 20 user interface starting from a basic interface So is impossible.
An object of the invention is to create a process and apparatus which allow the extension of o the range of the transmission channel between functional groups of the ISDN user network ooo f maintaining all ISDN typical characteristics, such as: maintenance of the network timing multiple access to the interface bus activation and deactivation of the interface.
In accordance with the invention there is provided process for the enlargement of the range of the transmission channel between functional groups of the ISDN user interface with reference to one or more similar ISDN interfaces including: a) providing for data transmission from the net side by converting the ISDN-specific coded data arriving at the respective ISDN interface into a binary coded data form, separated in accordance with B and D channel information, prior to transmission from the net side.
b) grouping (by way of a buffer arrangement) the arriving binary coded data, supplemented with an address designation for the respective interface, of the B and D channels into blocks and delivering the data blocks to a transmission means sequentially with a timing derived from the ISDN-specific timing of a particular ISDN interface and transmitting by the transmission means to the receiver side with a bit timing derived either from an independently produced timing or a bit timing derived from an ISDN-specific timing.
c) deriving, at the terminal side, the ISDN-specific timing required for communication between transmitter and receiver either through the arrival sequence of the received data blocks or the arrival sequence of the transmitted data bits, and o d) storing the received data blocks in accordance with their addresses in a buffer, and sequentially transmitting the data to the designated ISDN interface and subsequently 20 furnishing the B channel information in accordance with the derived timing, and the D channel information, if any, to a code converter which changes the binary coded data into ISDN-specific coded data, and e) transmitting the data from the terminal side in a fashion analogous to steps a) and b) wherein the ISDN-specific timing mentioned in step b) is the one derived in accordance with process step and f) allocating and transmitting the data blocks received on the net side in accordance with their address to a buffer of the respective ISDN interface where a conversion of the binary coded data into ISDN-specific coded data occurs in accordance with the ISDN-specific timing of the interface of the net side.
The invention also provides apparatus for the enlargement of the range of the transmission channel between functional groups of the ISDN network, with reference to one or more similar ISDN interfaces, wherein, equipment is located both at the net and terminal side including means for protocol conversion and appropriate transmission equipment and S-transmission medium, and wherein the equipment for protocol conversion communicate with one another over the appropriate channel, wherein the equipment for protocol conversion includes, for each of the interface to be connected, an interface module a microcomputer an interface module for transmission channel X, a timing generation module a PIO a power supply as well as the corresponding electrical connections and a bus o: for the address and data exchange, whereby the interface module is adapted to convert ISDN-specific coded data into binary coded data as well as converting binary coded data into
S
20 ISDN coded data, wherein the microcomputer (66) is connected via a bus with the ISDN S interface module and the parallel input/output PIO (92) as well as with the interface module and is adapted for connection with the transmission channel X and which is also adapted to form blocks from the binary coded data arriving at the interface module and, over a connection with the PIO to exchange data with the interface module and which is also adapted to receive data blocks from interface module in combination with the PIO (92) and to transmit these to the interface module and wherein the timing generation module is connected with interface modules and the interface module (2) for connection to the transmission channel X as well as with the PIO (92) connected to the microcomputer (66) over the bus and adapted to regenerate the ISDN-specific timing from the sequential arrival of the received data blocks or the sequential arrival of the data bits so that communication between sender and receiver can occur.
*5 Preferably, the block formation in accordance with step b) of the process occurs in such a manner that the blocks have equal lengths and the B and the D channel data exhibit a partition which corresponds to the capacities of the B and the D channels of the ISDN interface.
For those times in which the D channel carries no information, blocks of equal lengths are formed without D channel data.
For those times in which the ISDN interface n is not active, block formation occurs in such a fashion that equal length blocks of a fixed length are formed. These blocks carry no relevant information as they serve only for the maintenance of the communication ability between the net and terminal side.
An active intervention in the D channel signalization occurs for those cases in which the signal delay of the D channel signalization is too large for the utilized transmission channel.
In these cases, the activating participant is signaled that the connection has not been established.
The length of the blocks built in accordance with process step b) is dependent on the capacity 15 of the processing units required for the coding, transmission, and uncoding of the ISDN interface information as well as the ISDN-specific channel capacities.
tThe formed blocks are bit timed either with an independently produced timing signal or with a timing signal derived from the ISDN-specific timing for transmission over satellite or other transmission channels to the receiver side.
U
20 During the block transmission, in accordance with CCITT 1.400, to ensure the accurate distinction of the flags (01111110) from the information bytes in the blocks, a is inserted S in the bit stream wherever more than 5 "ones" follow successively. As a result, the actually U1 Snecessary bit rate increases. To reduce the probability of this occurrence, preferably the blocks are connected with an exclusive OR before and after transmission. For this purpose, predefined bytes with alternating bit value are used.
Timing revovery in accordance with step c) of the process, if the transmission system itself determines the transmission timing, occurs in such a form that a comparison timing is derived from the time-spaced arrival of the received data blocks, from which, in accordance with known principles, a base timing is produced in a phase locked loop (PLL) from which the timing for the ISDN interfaces n is provided on the terminal side.
If the bit timing for the transmission system can be provided with a process in accordance to the invention, this base timing for the ISDN interfaces is preferably derived from the bit transmission rate by way of a PLL.
Both the terminal and net side code conversion of the ISDN-specific coded data into binary form occurs through known principles by way of a code converter, preferably an ISDN subscriber access controller.
In accordance with the invention, the realization of the process for the enlargement of the range of the transmission channel between functional groups of several ISDN participant connections occurs through an arrangement which comprises on both terminal and net sides a facility for protocol conversion and an appropriate transmission channel.
The transmission channel comprises transmission arrangements which are actually known and means utilized for the transmission, for example a satellite channel with the appropriate transmission and receiving arrangements as well as the required modems.
The arrangements for protocol conversion communicate with one another over the particular transmission channel. The arrangements for protocol conversion are preferably structured identical and can function both in master mode and in slave mode with the protocol conversi- 20.; on arrangement connected to the terminal side functioning in master mode and the protocol conversion arrangement connected to the net side functioning in slave mode. But it is also possible to achieve the arrangement of a protocol converter exclusively in master or slave S• mode wherein an arrangement on the net side must function in master mode and the arrange- Sment on the terminal side must function in slave mode.
The assembly for protocol conversion consists essentially of: A number of interface modules corresponding to the number n of the ISDN interfaces to be connected 8 A microcomputer (66), An interface module for the transmission channel X, A timing generation module One PIO (92), A mode switch A power supply as well as the corresponding electrical connections and a bus for the adress and data exchange.
The microcomputer (66) is connected over a bus with the ISDN interface modules and over the bus with the parallel input-output-building block PIO (92) as well as with the interface module for the connection to the transmission channel The timing generation module is connected, via bus to the interface modules and to the interface module for the connection to the transmission channel as well as through the PIO block (92) to the microcomputer (66).
The switch for the mode setting (master/slave) acts on power supply on the interface module and on the timing generation module 3.
The power supply energizes the circuit and produces the supply voltage for mainsindependent terminal equipment when the protocol converter works in slave mode.
l: Every ISDN interface module converts the ISDN interface into a binary coded form and S: 20 vice versa. The binary data as well as the required control information are exchanged, via bus between the interface module the microcomputer the PIO (92) and the interface module The interface module is comprised of an ISDN interface and a circuit for the conversion of the ISDN-specific coded data into binary data, for example an ISDN-subscriber access controller (ISAC circuit). The interface module for the transmission on the (X) channel comprises an interface and a serial input/output module SIO.
The microcomputer (66) comprises a microprocessor, a ROM for the storage of the program code, a RAM as main memory and a bus The microcomputer (66) is connected to the parallel input/output module PIO to the ISAC circuits in interface modules as well as to the serial input/output module SIO in interface module over the bus The processor of the microcomputer (66) controls the function of the modules PIO the ISAC circuit in interface module and SIO in interface module in a known manner through appropriate adjustment of the registers provided therefore in these modules.
In case of the realization of the arrangements for protocol conversion exclusively in slave or in master mode, these elements consist of almost the same modules as described above. The switch for mode selection is eliminated. The other building blocks are switched so that they achieve the functions in slave, or, master mode as described above.
On the net side the system for protocol conversion functions in master mode as follows: In the interface module within the ISDN interface the signal levels of the ISDN interface are reciprocally converted into the signal levels required by the ISAC module.
The mode switch switches the ISAC building blocks in all interface modules into the TE mode (terminal mode). In this mode the ISAC produces a timing signal of 512kHz at the output DCL. When the ISDN interface is active, the timing signal of 512kHz is synchronously S 15 derived from the bit timing of the ISDN interface.
The timing signal of 512kHz of every interface module is transmitted to the timing generation module The processor of the microprocessor (66) determines the interface module (1) Swith the lowest logical address whose ISDN interface is active. The timing signal of 512kHz of the ISAC circuit of exactly this ISDN interface is used in the timing generation module 20 controlled by the processor in microcomputer to produce by division a symmetrical S. timing signal. Such timing signal is provided to a port of the PIO (92) of the microcomputer (66).
:The ISAC circuit in the particular interface module converts the ternary-coded B and D channel signals of the ISDN interface n, if it is active, into binary coded signals and stores these, byte by byte, in its registers. Conversely, the module converts the binary coded B and D channel data from the processor into ternary signals and transmits these data to the interface of the corresponding interface module for transmission through the ISDN interface n.
The ISAC circuit signals, through a register, that it is prepared for the reception of one new B 1 and B2 channel byte each and, simultaneously, one complete B 1 and B2 channel byte each is ready to be accepted by the microcomputer The processor in microcomputer (66) periodically interrogates the signal register of the ISAC circuit and accepts the completed B channel bytes in its main memory, or transmits the B channel bytes.
Through another register, the ISAC circuit signals when a D channel frame from a particular ISDN interface has been received. The processor in microcomputer (66) also interrogates this signal byte periodically and receives, in the appropriate case, the D channel frame in its main memory.
When the processor in microcomputer (66) has received a D channel frame, it, in turn, transmits these bytes to the ISAC circuit for further delivery to the ISDN interface.
From the bytes transmitted from the ISAC circuit the processor forms blocks and temporarily stores them in the RAM of microcomputer (66).
The processor in microcomputer (66) will always receive an interrupt signal from the PIO (92) when the signal level changes on the timing signal input of the PIO At every such signal, the first part of a new block is delivered to the SIO in the interface module and a control register is set in the SIO to make this component commence the transmission of this Sblock. The SIO designates in its register, when the next portion of the block has to be delivered so that the delivery is not interrupted. The processor in microcomputer (66) 20 interrogates this register periodically and correspondingly delivers to the SIO in interface module the further portions of the block.
The processor successively delivers to the SIO in interface module data blocks corre- 0: sponding to the cyclically repeated logical addresses of the ISDN interfaces n. All ISDN interfaces operate synchronously on the basis of the central system timing of the ISDN so that the blocks are also produced synchronously.
In the reverse direction, the SIO in the interface module receives bit-serial data over the interface in interface module When the first portion of a new block or further portions of a block is received in the S/O, appropriate signalization bits are set in a register in the SIO. The processor of the microcomputer (66) periodically interrogates this register. When the receipt of a block is indicated, the processor receives this block in its main memory RAM. The blocks are buffered in accordance with the logical address stored in the control bytes. Several recently received blocks are buffered per logical address.
Internal registers within the SIO in interface module signal that a B channel byte is to be delivered to the ISAC circuit for transmission to the ISDN interface n. The processor of the microcomputer (66) interrogates these registers of all ISAC circuits periodically and delivers the corresponding B bytes to the relevant ISAC circuit.
The D channel bytes of the blocks received in interface module are delivered to the known D channel registers of the ISAC circuit in interface module On the terminal side, the arrangement for protocol conversion in slave mode functions as follows: In the interface module the reciprocal conversion occurs at the interface from the signal levels of the respective ISDN interface n to the signal levels required by the ISAC circuits.
15 The ISAC circuit in the interface modules is switched to the NT mode (network terminal mode) by the mode switch In such mode, the ISAC circuit requires synchronous timing signals at its inputs DCL of 512kHz, and of 8kHz at FSC 1 and FSC 2. From these signals, the ISAC circuit derives the frame synchronization and bit synchronization timing signals for the ISDN interface.
Timing generation module derives a timing signal from the arrival times of the blocks from the master apparatus. From this timing signal, module produces with the help of a PLL, working in accordance with well known principles, a timing signal of 512kr z, and therefrom, through division, a timing signal of 8kHz. These timing signals are delivered to the corresponding inputs of the ISAC circuits of all interface modules From the 8kHz signal a further symmetrical timing signal is generated in module and delivered to an input of PIO (92).
Microcomputer ISAC circuit in interface module and the SIO in interface module function together in a similar manner as in the master apparatus in the further transfer of the B and D channel data between the ISDN interface and the X channel.
Advantageously, arrangements for protocol conversion can be constructed from discrete elements using one interface module as well as several interface modules A mode switch then supplies an additional switching function for the autonomous operation of individual arrangements for protocol conversion, or the allocation and common operation of selected arrangements for protocol conversion.
In accordance with the process and apparatus of the invention it is possible to transmit the varied services of the ISDN through the appropriate interfaces parallel in accordance with the ISDN channels, over long distances without transfer to another net. Thus it is possible to remain in the utilized ISDN net whereby the quality of the transfer services is not affected.
Exemplary embodiments of the invention are illustrated in the attached drawings. Thereby are shown: 15 Fig. 1 shows a functional block diagram of an arrangement for protocol conversion.
o4e :Fig. 2 shows an arrangement for the enlargement of the range of the transmission channel between functional groups of an ISDN user interface.
9ll Fig. 1 shows a block diagramm of an arrangement for protocol conversion.
Microcomputer (66) is comprised of a microprocessor (realized as an N80C188XL-20), a 20 ROM for the storage of the program code, a RAM as main memory and a bus.
The microcomputer is connected with an SIO circuit (configured as a SAB 82532) in interface module with a PIO building element functionally created within SAB 82532, as well as with an ISAC circuit (realized as a PEB 2086) within interface module The processor in microcomputer (66) controls the circuits PIO 92, PEB 2086 and SAB 82532 through appropriate setting of the registers provided for these purposes in these building elements. Also 13 through registers of these components, the processor interrogates the status of them and exchanges data.
The activation/deactivation of the ISDN interface is controlled through PEB 2086 in the interface module The status of each ISDN interface can be read from the registers of PEB 2086. The processor in microcomputer (66) periodically interrogates the registers of PEB 2086 to note the status of the respective ISDN interface.
The arrangement in Figure 1 functions in master mode on the net side as follows: Interface modules convert, in either direction, the signal levels of the ISDN interface to the levels required by component PEB 2086.
By way of the mode switch the modules PEB 2086 of all interface modules are switched into the terminal mode. In this mode, PEB 2086 produces a timing signal of 512kHz at its output DCL. When the ISDN interface is active, the timing signal of 512kHz is derived synchronously from the bit timing of the ISDN interface.
The timing signal of 512kHz of every interface module is provided to the timing generation module The processor of microcomputer (66) determines the interface module with the lowest logical address of the ISDN interface being active. The timing signal 512kHz from the PEB 2086 of exactly this ISDN interface is utilized, controlled by the microcompressor, in
I
the timing generation module to generate, through division, a symmetrical timing signal of 500Hz.
*p #9 The 500Hz signal is delivered on a port of PIO (92) to microcomputer (66).
PEB 2086 in interface module converts the ternary coded B and D channel signals of the ISDN interface (if it is active), into binary coded signals and buffers these, byte by byte, in its registers. In the reverse direction, PEB 2086 converts the incoming binary coded B and D channel signals from microcomputer (66) into ternary signals and transmits these data to the interface of the interface module for delivery to the appropriate ISDN interface.
14 Through a register PEB 2086 indicates that it is ready to accept a new B 1 and B2 channel byte each and simultaneously, a complete B 1 and B2 channel byte each is ready to be accepted by the processor. The processor of microcomputer (66) periodically interrogates the signaling register of PEB 2086 and either takes the finished B channel bytes in its main register, or transmits the B channel bytes, respectively.
Through a further register, PEB 2086 signals when a D channel frame has been received from the ISDN interface. The processor periodically interrogates this signaling byte too and accepts the D channel frame in its main memory.
If the processor has received a D channel frame from the distant station, it transmits these bytes to PEB 2086 for further delivery to the ISDN interface.
The processor of microcomputer (66) builds blocks from the bytes received from PEB 2086 and stores these in its main memory RAM.
The processor in microcomputer (66) will always receive an interrupt signal from PIO (92) when the timing input 500 Hz of PIO (92) changes its signal value. With every such signal, S 15 the first part of a new block is transmitted to the SAB 82532 in interface module and then a control register in SAB 82532 is set whereby this building element is directed to begin the transfer of this block. SAB 82532 indicates in the known register when the next parts of the block must be transmitted so that the transmission does not break off. The processor periodically interrogates this register and delivers the further sections of the block to SAB 82532.
p.
20 The processor in microcomputer (66) transmits to SAB 82532 in interface module blocks in a continuing sequence corresponding to the cyclically repeated logical addresses of the o= ISDN interface. All active ISDN interface operate synchronously on the basis of the central timing of the ISDN so that the blocks are also produced synchronously.
o When the ISDN interface is not active, the processor in microcomputer 66 builds equal length blocks of fixed length and transmits these instead of the data blocks.
In the opposite direction, SAB 82532 in interface module receives bit-serial data over the interface in interface module When the first portion of a new block, or further portions of a block are received in SAB 82532, appropriate signaling bits are set in a register of SAB 82532.
The processor of microcomputer (66) periodically interrogates this register. When the reception of a block is indicated, the processor accepts this block in sections in its working RAM. The blocks are ordered and stored in accordance with the logical address coded in the control bytes. The two most recently received blocks are temporarily stored per logical address.
The B channel bytes from the stored blocks are delivered with an average delay of (2 x n x 16) bytes, with reference to the time of their arrival, to the PEB 2086 in interface module (1) according to corresponding logical addresses of the blocks and interface modules.
PEB 2086 in interface module signals over internal registers that a B channel byte is ready for transfer to PEB 2086 for transmission to the ISDN interface. The processor of microcomputer (66) periodically interrogates these registers of all PEB 2086 units and then transfers the corresponding B-bytes to PEB 2086.
The D channel bytes of the blocks received by interface module are transferred to the known D channel registers of PEB 2086 in interface module 4% 0 When the D channel frame is complete or a section of 32 D channel bytes has been transferred, the processor arranges the transfer of the bytes through PEB 2086 to the ISDN interface by setting a known register in PEB 2086.
20 On the terminal side the arrangement of Figure 1 operates in slave mode as follows: The conversion in either direction of the signal levels from the ISDN interface to the signal levels needed by module PEB 2086 occurs in the interface module at the ISDN interface.
The mode switch switches module PEB 2086 in interface module into the network terminal mode. In this mode, PEB 2086 requires synchronous timing signals at the input DCL of 512kHz, and of 8kHz on FSC 1 and FSC 2. From these, PEB 2086 delivers the frame and bit synchronization signals for the ISDN interface.
Timing generation module derives a timing signal of lkHz from the sequence of arrival of the blocks from the master unit. From this timing signal, module working in accordance with known principles of a phase locked loop, produces a timing signal of 512 kHz and therefrom, by division, a timing signal of 8kHz. These timing signals are delivered to the corresponding inputs of the PEB 2086 of all interface modules From the 8kHz signal module further delivers a timing signal of 500Hz and delivers it to one of the inputs of PIO (92).
Microcomputer PEB 2086 in the interface module and SAB 82532 in the interface module function together in similar ways as in the master unit in the further transfer of the B and D channel data between the ISDN interface and the X channel.
The power supply for the apparatus produces for a connected TE without its own power supply a DC voltage of 40 volts which is transferred over the ISDN interface to the TE.
The blocks formed by the processor in microcomputer (66) have the following structure: In the arrangement for protocol conversion every interface module utilizes a circuit PEB 15 2086 for the coupling between the ISDN interface (S/T-reference point) and bus At every active ISDN interface there are sent, as well as received, four frames of 48 bits per millisecond at a bit transmission rate of 192kHz. Four frames contain: 9t 64 bits channel BI1 •C o 64 bits channel B2 20 16 bits channel D.
These data are stored in PEB 2086 in the interface module byte by byte and sorted in accordance with the channels, in corresponding internal registers that can be read by microcomputer (66) over the bus On the D channel of the ISDN, HDLC frames are transmitted. PEB 2086 stores only those D channel bytes which have been received within a D channel frame.
For transmission over the X channel, microcomputer (66) forms a block in n milliseconds in parallel (time multiplex) for every interface module and stores these blocks in the working register (RAM). Per millisecond, a block is created of 8 B1 bytes and 8 B2 bytes.
For example: B1.1 B2.1|B1.21B2.2B 1.31B2.31B1.41B2.41B1.51B2.51 B1.61B2.61B1.71B2.71B1.81B2.8 These blocks (hereafter characterized as GB) are sequentially arranged in accordance with the number n of the utilized interface modules and enhanced, if existing, by 2 x n D bytes.
Preceding is a control byte S in which the logical channel and the possible beginning of a D channel frame are encoded.
Block structure: SIGB1 GB21GB3...IGBnD1 IDijDi+l Dj The number i j of the D bytes is maximally 2 x n and greater than 0, when D frames are to *be transmitted. S is a controlling byte, in which the logical address of the interface module 15 as well as the value i, are encoded so that it shows that Di is the last byte of the preceding S D frame and Di 1 the first byte of a following new D frame.
Flags (at least one flag) is transmitted between the blocks as separators. Thus, the X channel must have a transmission rate in both directions of at least 18 x n x 8 kBits/s.
p p In the arrangement connected to the net side every PEB 2086 is programed in the TE mode and thus delivers a timing signal of 512kHz which is derived synchronously from the bit transmission timing of the ISDN interface and, thus, synchronously with the system timing of the ISDN. From one of these timing signals the control module derives a synchronous timing signal of 1kHz and n x 160kHz.
The data blocks are delivered on the X channel to the unit connected on the participant's side synchronously with the 1kHz timing signal.
The transmission can occur either a) with a bit timing signal from the transmission arrangement or b) with a timing signal ofn x 160kHz arranged in the unit. This can be selected by a switch.
In the arrangement on the participant's side for the protocol conversion, every PEB 2086 is programed in the NT mode and thus requires synchronous timing signals of 512kHz and 8kHz. These timing signals can be derived either from the time spaced succession of the blocks or, if the bit transmission timing in accordance with is used, derived from the received bit timing by way of a PLL. These timing signals are synchronous with the 512kHz timing signals in the arrangement connected to the net side. PEB 2086 forms from these signals the ISDN frame timing signal of 4kHz at a bit timing of 192kHz. Thus, the synchronicity of the ISDN units on the participant's side with the ISDN is assured.
0* The data blocks of the above described structure are transmitted on the modem channel in 15 both directions in accordance with the sequence of their formation. The received blocks are stored in the main memory. The B and D channel bytes of the blocks are transmitted in S" accordance with the logical number of the blocks from the storage to the register provided therefore in PEB 2086 of the appropriate interface module PEB 2086 transfers these data to the ISDN interface in accordance with the timing and frame structure.
20 When the ISDN interface is not active, the processor in microcomputer (66) forms equal length blocks of a fixed length with the following structure: S-Byte (Channel) ISAC-S-Condition Byte|ISAC-S-Condition The S-Byte signifies only the logical channel. The status byte is delivered from the circuit of PEB 2086 and indicates the status of the ISDN interface. The status byte is repeated in the 19 example and the block is filled out with 9 bytes. The 6 bytes for filling do not carry any relevant information.
To assure the reliable differentiation of the flages (01111110), during block transfer, from the information bytes, a is inserted in the bit stream when more than five follow one another. This results in an increase in the real required bit rate. To reduce the probability of this occurrence the blocks are connected, prior to transmission, through an exclusive OR with the bytes sequence 0 x 55, 0 x Figure 2 shows an arrangement for the enlargement of the range between functional groups of ISDN user connections, with reference to an So interface. Emitting from an ISDN network, over an interface Uko to a network termination NT, a protocol converter is arranged on the net side at the So interface which communicates over the transmission channel with an arrangement for protocol conversion on the terminal side and which provides the interface So on the terminal side. On the terminal side one can drive an NT 2 unit or TE units directly.
The apparatus connected to the S, interface on the net side functions in master mode and the apparatus connected to S, interface on the terminal side functions in slave mode. The unit operating in master mode behaves, with respect to the ISDN net, like a terminal equipment TE and the unit %urking in slave mode behaves like an SNT network termination.
Between the two units connected over the transmission channel for protocol conversion (PW), the data exchange proceeds by way of bit serial synchronous transmission of data blocks of 16B channel bytes plus, at most, 2 D channel bytes.
The arrangement for protocol conversion PW in master mode activates the S 0 interface always when it is not active. It transmits blocks only when the S, interface is active.
The arrangement for protocol conversion PW in slave mode activates the S 0 interface anew when this interface is not active and the unit receives, at the same time, data blocks from the master unit. The arrangement de-activates the So interface when no blocks have been received from the master unit for one second.
I
The claims defining the invention are as follows: 1. Process for the enlargement of the range of the transmission channel between functional groups of the ISDN user interface with reference to one or more similar ISDN interfaces including: a) providing for data transmission from the net side by converting the ISDN-specific coded data arriving at the respective ISDN interface into a binary coded data form, separated in accordance with B and D channel information, prior to transmission from the net side.
b) grouping (by way of a buffer arrangement) the arriving binary coded data, supplemented with an address designation for the respective interface, of the B and D channels into blocks and delivering the data blocks to a transmission means sequentially with a timing derived from the ISDN-specific timing of a particular ISDN interface and transmitting by the transmission means to the receiver side with a bit timing derived either from an independently produced timing or a bit timing derived from an ISDN-specific timing.
c) deriving, at the terminal side, the ISDN-specific timing required for o:o••3 communication between transmitter and receiver either through the arrival sequence of the *received data blocks or the arrival sequence of the transmitted data bits, and storing the received data blocks in accordance with their addresses in a buffer, 20 and sequentially transmitting the data to the designated ISDN interface and subsequently furnishing the B channel information in accordance with the derived timing, and the D channel information, if any, to a code converter which changes the binary coded data into ISDN-specific coded data, and
Claims (14)
- 2. Process according to claim 1, wherein the block formation in accordance with step b) of the process is performed in such a manner that the formed blocks have equal lengths and that the B and the D channel data exhibits a partition that is related to the capacities of the B and D channels.
- 3. Process according to claim 1, wherein for step b) of the process equal length blocks are formed without D channel data in those time periods where the D channel carries no 15 information.
- 4. Process according to claim 1, wherein for step b) the block formation, during those times in which the ISDN interface n is not active, equal length blocks of fixed length are formed.
- 5. Process according to any one of claims 1 to 4, wherein the blocks formed in 20 accordance with step b) are associated with a byte of alternating bit value through an exclusive OR.
- 6. Process according to any one of the preceding claims, wherein the timing recovery in accordance with step c) of the process, in the case where the transmission means determines the transmission timing, occurs through a comparison timing derived from the sequential 4o a oo o* a oooo a I a ao a. a a.e ooa. arrival of the received data blocks from which, in accordance with known principles, a base timing is produced from which the timing for the ISDN interface on the terminal side is derived.
- 7. Process according to any one of claims 1 to 5, wherein the timing recovery in accordance with step c) of the process follows from the bit transmission timing when the bit timing is furnished by an apparatus to practice the process.
- 8. Process according to any one of the preceding claims, wherein when the transmission delay because of the transmission means is in excess of the ISDN standardised signal delay of the D-channel signalisation, the activating user is advised that the connection has not yet been established.
- 9. Apparatus for the enlargement of the range of the transmission channel between functional groups of the ISDN network, with reference to one or more similar ISDN interfaces, wherein, equipment is located both at the net and terminal side including means 15 for protocol conversion and appropriate transmission equipment and transmission medium, and wherein the equipment for protocol conversion communicate with one another over the appropriate channel, wherein the equipment for protocol conversion includes, for each of the interface to be connected, an interface module a microcomputer an interface o°: module for transmission channel X, a timing generation module a PIO a power a" 20 supply as well as the corresponding electrical connections and a bus for the address and data exchange, whereby the interface module is adapted to convert ISDN-specific coded data into binary coded data as well as converting binary coded data into ISDN coded data, wherein the microcomputer (66) is connected via a bus with the ISDN interface module (1) and the parallel input/output PIO (92) as well as with the interface module and is adapted a C, I 23 for connection with the transmission channel X and which is also adapted to form blocks from the binary coded data arriving at the interface module and, over a connection with the PIO to exchange data with the interface module and which is also adapted to receive data blocks from interface module in combination with the PIO (92) and to transmit these to the interface module and wherein the timing generation module is connected with interface modules and the interface module for connection to the transmission channel X as well as with the PIO (92) connected to the microcomputer (66) over the bus and adapted to regenerate the ISDN-specific timing from the sequential arrival of the received data blocks or the sequential arrival of the data bits so that communication between sender and receiver can occur. Apparatus according to claim 9, wherein the apparatus for protocol conversion can function in master as well as slave mode, or in master, or in slave mode, wherein the .apparatus for protocol conversion connected to the net side functions in master mode and the 15 apparatus for code conversion on the terminal side functions in slave mode. o
- 11. Apparatus according to claims 9 or 10, wherein the apparatus for protocol conversion S includes a mode switch for adjusting the master/slave condition connected with a power :s supply the interface modules and the timing generation module and in which the power supply supplies the apparatus with voltage and supplies the voltage for the r 20 mains-independent terminals when the apparatus for protocol conversion functions in the Sslave mode.
- 12. Apparatus according to claim 9, 10 or 11 wherein the apparatus for protocol conversion includes apparatus connected with one or more interface modules and wherein the mode switch possesses an additional function for the autonomous operation of individual protocol converters or for the supply and the common operation of selected apparatus for code conversion.
- 13. Apparatus according to any one of claims 9 through 12, wherein the interface module includes an interface and a circuit for the conversion of ISDN-specific coded data into binary coded data.
- 14. Apparatus according to any one of claims 9 through 12, wherein the interface module includes an SIO circuit and an interface. Apparatus according to any one of claims 9 through 12, wherein the timing generation module includes a PLL circuit.
- 16. Process for the enlargement of the range of the transmission channel substantially as hereinbefore described with reference to the drawings.
- 17. Apparatus for the enlargement of the range of the transmission channel substantially as S. hereinbefore described with reference to the drawings. Dated this 21st day of October 1998 PATENT ATTORNEY SERVICES Attorneys for DTM DATA TELEMARK GMBH 1 o PROCESS AND DEVICE FOR INCREASING THE WORKING RANGE OF THE TRANSMISSION PATH BETWEEN FUNCTIONAL UNITS OF AN ISDN SUBSCRIBER CONNECTION Abstract of the Disclosure A process and device are disclosed for increasing the working range of the transmission path between functional units of an ISDN subscriber terminal, in relation to one or several ISDN-interfaces. Manifold ISDN-services may thus be transmitted over large distances. The device consists of protocol converters connected to the ISDN-interfaces at the terminals and network and of a transmission channel associated therewith composed of a transmission device and of a transmission medium.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19944407214 DE4407214C1 (en) | 1994-03-06 | 1994-03-06 | Extending transmission path between ISDN subscriber functional gps. |
| DE4407214 | 1994-03-06 | ||
| DE19506906 | 1995-03-01 | ||
| DE19506906A DE19506906A1 (en) | 1994-03-06 | 1995-03-01 | Method and device for increasing the range of the transmission path between functional units of the ISDN subscriber line |
| PCT/DE1995/000268 WO1995024811A1 (en) | 1994-03-06 | 1995-03-02 | Process and device for increasing the working range of the transmission path between functional units of an isdn subscriber connection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU1944995A AU1944995A (en) | 1995-09-25 |
| AU700380B2 true AU700380B2 (en) | 1999-01-07 |
Family
ID=25934375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU19449/95A Ceased AU700380B2 (en) | 1994-03-06 | 1995-03-02 | Method and apparatus for the enlargement of the range of the transmission channel between functional groups of an ISDN-user interface |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0749669B1 (en) |
| JP (1) | JP2958121B2 (en) |
| AU (1) | AU700380B2 (en) |
| CA (1) | CA2184984A1 (en) |
| DE (2) | DE19506906A1 (en) |
| ES (1) | ES2112049T3 (en) |
| NO (1) | NO963522L (en) |
| WO (1) | WO1995024811A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL121739A (en) * | 1996-09-13 | 2001-01-11 | Dica Technologies Ag | Method and apparatus for the enlargement of the range of the transmission channel between functional groups of the isdn-user interface with a minimized bandwidth |
| DE19920383A1 (en) * | 1999-05-04 | 2000-11-09 | Deutsche Telekom Ag | Interface converters added in front of measuring instrument for measuring error rate at various interfaces has clock synchronization equipment for synchronizing the interface converter |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB249927A (en) * | 1925-01-02 | 1926-04-06 | John Christie Adam | Improvements in or relating to water jackets or water jacketed parts |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157656A (en) * | 1990-07-31 | 1992-10-20 | Northern Telecom Limited | Nyblet time switch |
| JP2603893B2 (en) * | 1992-07-16 | 1997-04-23 | 住友電設株式会社 | ISDN concentrator |
-
1995
- 1995-03-01 DE DE19506906A patent/DE19506906A1/en not_active Ceased
- 1995-03-02 AU AU19449/95A patent/AU700380B2/en not_active Ceased
- 1995-03-02 CA CA002184984A patent/CA2184984A1/en not_active Abandoned
- 1995-03-02 DE DE59501015T patent/DE59501015D1/en not_active Expired - Fee Related
- 1995-03-02 ES ES95912120T patent/ES2112049T3/en not_active Expired - Lifetime
- 1995-03-02 JP JP7523146A patent/JP2958121B2/en not_active Expired - Lifetime
- 1995-03-02 WO PCT/DE1995/000268 patent/WO1995024811A1/en not_active Ceased
- 1995-03-02 EP EP95912120A patent/EP0749669B1/en not_active Expired - Lifetime
-
1996
- 1996-08-23 NO NO963522A patent/NO963522L/en unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB249927A (en) * | 1925-01-02 | 1926-04-06 | John Christie Adam | Improvements in or relating to water jackets or water jacketed parts |
Non-Patent Citations (1)
| Title |
|---|
| INT. CONF. ON COMM INC. SUPERCOMM, APRIL 15-19 1990 VOL 4, IEEE PP 1637-1642 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2184984A1 (en) | 1995-09-14 |
| DE59501015D1 (en) | 1998-01-02 |
| EP0749669B1 (en) | 1997-11-19 |
| NO963522L (en) | 1996-10-15 |
| ES2112049T3 (en) | 1998-03-16 |
| JPH09510838A (en) | 1997-10-28 |
| EP0749669A1 (en) | 1996-12-27 |
| NO963522D0 (en) | 1996-08-23 |
| JP2958121B2 (en) | 1999-10-06 |
| WO1995024811A1 (en) | 1995-09-14 |
| DE19506906A1 (en) | 1996-09-05 |
| AU1944995A (en) | 1995-09-25 |
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Owner name: DICA TECHNOLOGIES AG Free format text: FORMER OWNER WAS: DTM DATA TELEMARK GMBH |
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| MK14 | Patent ceased section 143(a) (annual fees not paid) or expired |