AU703989B2

AU703989B2 - A system for acquiring and playing back a sequence of animated video images in real time

Info

Publication number: AU703989B2
Application number: AU16665/97A
Authority: AU
Inventors: Eric Bigonneau; Jean-Etienne Bouedec; Jerome Lenoble; Christophe Sidawy
Original assignee: Francaise des Jeux SA
Current assignee: Francaise des Jeux SA
Priority date: 1992-10-26
Filing date: 1997-04-02
Publication date: 1999-04-01
Anticipated expiration: 2013-10-07
Also published as: MX9306621A; RU2140668C1; DK0595700T3; BR9304344A; DE69307459D1; EP0595700B1; GR3023137T3; DE69307459T2; JPH06215120A; FR2697360A1; CA2108921A1; ES2100494T3; AU4884893A; CN1086913A; FR2697360B1; ATE147879T1; CN1050208C; KR940010042A; ZA937663B; EP0595700A1

Abstract

System for acquisition and reproduction of a video image sequence with real time animation, of the type comprising at least one stage (2) for acquisition of data corresponding to the image sequence and a stage (3) for reproduction (3) of this image sequence in graphics form on a screen (E). The acquisition stage (2) comprises at least two independent memory units (M1, M2) which are associated respectively with at least two image or screen controllers (CRTC1, CRTC2), in such a way as to allocate a memory unit (M1 or M2) and its associated controller (CRTC1 or CRTC2) alternately to the data acquisition stage (2) in order to carry out management operations on the recorded data or to record in the memory unit, and the other memory unit (M2 or M1) and its associated controller (CRTC2 or CRTC1) to the reproduction stage (3) in order to reproduce image sequences recorded in this other memory unit. <IMAGE>

Description

AUSTRALIA

Patents Act 1990 COMPLETE SPECIFICATION STANDARD PATENT *o 0* V. Applicant: LA FRANCAISE DES JEUX

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o V Invention Title: A SYSTEM FOR ACQUIRING AND PLAYING BACK A SEQUENCE OF ANIMATED VIDEO IMAGES IN REAL TIME The following statement is a full description of this invention, including the best method of performing it known to me/us: A SYSTEM FOR ACQUIRING AND PLAYING BACK A SEQUENCE OF ANIMATED VIDEO IMAGES IN REAL TIME The present invention relates to a system for acquiring and playing back an animated image sequence in real time, the system being of the type comprising at least one data acquisition stage constituted by a memory block and a read/write stage formed by a screen or image controller driven by a central processor unit for reading and writing digital data in the memory block corresponding to at least one image sequence, and a data playback stage.

In general, it is desirable for such a system to be capable, in particular, of acquiring, of locally storing, and of playing back in real time a large quantity of high t 15 quality images, it being understood: that an image is made up of a set of image points or "pixels", each pixel being encoded on 16 to 32 bits; and that the term "real time" is used to mean that it is possible to switch complete images 25 or 30 times a 20 second in the field frequency of an electronic image.

To make this possible, such a system must be fitted with a large volume of memory, so as to satisfy the large storage capacity requirements of this type of data.

In an acquisition and playback system of the above- 25 specified type, the read/write device which is formed by a screen controller in the data acquisition stage takes account of macro commands delivered by the processing central unit in order to handle data in the memory block, in particular by performing read, write, and refresh operations. In parallel, the playback stage must also be able to access the memory block to read therefrom the digital data corresponding to at least one sequence of images, and subsequently to play this sequence back on the screen in analog form.

The acquisition stage and the playback stage must therefore both be capable of accessing the memory block, even though they cannot do so simultaneously, in practice. At present, no memory technology is capable of allowing simultaneous access, such that various solutions have been applied to managing the problem raised by accessing blocks of memory.

A first solution consists in fitting the system with an arbitration device of the sequencer type which allocates a fraction of the passband of the memory block the total number of bits that can be read or written per unit time) to the operations of reading, writing, and refreshing that are performed by the screen controller of the acquisition stage, and which allocates the remaining fraction of the passband to the playback stage to enable it to read a sequence of images and display it on the screen.

15 A more recent, second solution consists in using a memory block formed by dynamic video RAM having the special feature of including a shift register that acts as an interface between the memory block and the playback stage. In other words, all information interchanged 20 between the memory block and the playback stage passes through said register. In such a system, loading and/or unloading of the shift register takes place during the line scan flyback time of the screen, such that a larger fraction of the passband of the memory block is allocated 25 to management of the data in said memory block by the screen controller.

Thus, both of the above-mentioned solutions solve the problem of dual access to the memory block by alternating between accesses.required for managing the data in the memory block and accesses required for graphically playing back the data recorded in said memory block.

Nevertheless, such solutions lead to systems where performance in terms of display power on the screen is limited, i.e. the possibility of animating images on the screen is restricted. In such systems, access time in read mode or in write mode for managing recorded data or 3 data to be recorded in the memory block is relatively long, and as a result operations concerning the recording of data concerning new image sequences in the memory block take place at a frequency that is less than the frequency at which image points are displayed on the screen (the "pixel" frequency). In practice, such systems operate at a rate of about 3,000,000 to 4,000,000 pixels per second, thus greatly restricting the possibilities of animated playback in real time.

Furthermore, video RAM technology is still very expensive compared with standard mass-produced dynamic memory.

The object of the invention is to provide a solution that is novel and original to the problem of dual access to a block of memory, thereby achieving a system that provides greater performance in terms of display power, at a cost that is considerably reduced compared with existing systems.

To this end, the invention provides a system for mo ~20 acquiring and playing back an animated image sequence in Oo S" real time, the system including at least one data acquisition stage constituted by a memory block and read/write stage formed by a screen or image controller driven by a central processor unit for reading and writing S" 25 digital data in the memory block corresponding to at least one image sequence, and a data playback stage, wherein the data acquisition stage includes at least two self-contained S"memory blocks respectively associated with at least two screen or image controllers, in such a manner as to i allocate one of the memory blocks and its associated controller to the data acquisition stage to perform 0 management operations on data recorded is or to be recorded in the memory block in alternation with at least one other memory block and its associated controller being allocated to the playback stage for reproducing image sequences recorded in said other memory block.

Thus, the playback system can proceed with 'I o 3a displaying sequences of images in the memory block associated with one of the controllers while new sequences of images are simultaneously recorded in the memory block associated with the other controller, and 0 *S 00 .00.I vice versa. The playback system can thus work in alternation and at high speed with both controllers, i.e.

problems of alternating access to a block of memory controlled by a single controller are avoided.

According to one embodiment of the invention, each memory block is implemented using standard DRAM type memory that may be synchronous or asynchronous.

In a particular embodiment of the invention, each controller is interposed between the memory block with which it is associated and the central control unit.

In a preferred embodiment of a system of the invention, each controller is also connected to a transmission bus enabling it to receive directly data resulting from the compression of image sequences to be

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played back, which data is recorded in an auxiliary memory of the FIFO or SRAM type, or in a hard disk unit, S. for example.

Such a configuration results in each controller constituting a crosspoint or a switching device with respect to reading and writing relative to the four distinct operational blocks situated peripherally to the controller, namely: a block of DRAM type memory; 25 the central processor unit; C. an auxiliary memory unit of the FIFO or SRAM type, or a hard disk unit; and the ADC/DAC converter circuits of the playback stage.

30 The acquisition and playback system of the invention presents numerous advantages both with respect to graphics animation and with respect to cost.

Such a system makes it possible to implement quality animation over substantially all of the screen at a rate of about 12,000,000 pixels per second, where such graphics animation can represent movements of parts of images or of multiple graphics objects alonq the axes of

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the image plane relative to a background that may be stationary or animated.

In addition, the system of the invention has made it possible to find an alternative to using video memories of low capacity and above all of high cost, implemented with standard video memories and without giving rise to special hardware constraints.

According to another advantage of the invention, it is possible to fit the system with a memory having a minimum capacity of 256 megabytes which memory may be installed, in particular, on an electronics card equivalent to the maximum area available on a plug-in card for a microcomputer, for example, e.g. in compliance with the ISA, MCA, EISA or NUBUS standards.

3.5 Other advantages, characteristics, and details of the invention appear more clearly from the following explanatory description given with reference to the accompanying drawings that are provided purely by way of example, and in which: 20 Figure 1 is a simplified block diagram of a prior art system for acquiring and playing back sequences of images; Figure 2 is a simplified block diagram of a system constituting an embodiment of the invention for acquiring and playing back sequences of images; and Figure 3 Is a simplified block diagram of a variant embodiment of the invention.

A prior system for acquiring and playing bac:k an animated sequence of images as shown diagrammatically in Figure 1 comprises a stage 2 for acquiring digital data and a stage 3 for graphically playing back said data.

The data acquisition stage 2 comprises a memory block M and a read/write device formed by a scre .i controller CRTC driven by a central control unit CPU.

The memory block M is implemented by video random access memory VRAM associated with a shift register RG. The screen controller CRTC communicates with the memory block

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M via a bus bl for performing read/write operations in the VRAM memory, and with the central control unit CPU via a bus b2 and an I/O interface connected to the bus b2 to provide a connection with peripherals (not shown).

The playback stage 3 comprises a converter device 4 comprising a digital-to-analog converter DAC and an analog-to-digital converter ADC. The converter device 4 is connected by a bus b3 to the shift register RG of the memory block M and by a bus b4 to a television type scanned screen E.

As mentioned in the introduction, such a system allocates the memory block M in alternation to the data S, acquisition stage 2 and to the stage 3 for playing back said data, with all of the drawbacks that result from 15 such alternation.

The system of the invention for acquiring and playing back an animated image sequence in real time and as shown diagrammatically in Figure 2 likewise comprises a stage 2 for acquiring data in digital form and a stage 20 3 for graphically playing back said data.

The data acquisition stage 2 comprises a memory M that is split into at least two self-contained memory blocks Ml and M2, each of which is constituted by standard dynamic random access memory DRAM that may be of 25 the synchronous type or of the asynchronous type. Each of the memory blocks Ml and M2 is associated with a read/write device constituted by a screen or image controller CRTC1 or CRTC2. The two controllers are driven by a central control unit CPU. Each memory block Ml and M2 is connected by a respective bus blO to the associated controller CRTC1 or CRTC2. The central control unit CPU is connected by a bus bll to both of the controllers CRTC1 and CRTC2.

The playback stage 3 is in the present example of the same general type as that described with reference to Figure 1, i.e. it comprises a converter device 4 of the digital-to-analog type DAC and/or of the analog-todigital type ADC, together with a screen E. The converter device 4 is connected by a bus b12 to both of the controllers CRTC1 and CRTC2. The converter device 4 is used, for example, ati least to transform digital data taken from the memory block and corresponding to a sequence of images into an analog or digital television standard.

In addition, the two controllers CRTC1 and CRTC2 are connected via a bus b15 to a peripheral member such as an auxiliary memory MO for the purpose of directly receiving data that results from compressing sequences of images to be played back.

Thus, in operation, it is possible to allocate one of the memory blocks, e.g. the block M1 and its 15 associated controller CRTC1 to the data acquisition stage 2 for the purpose of performing management operations on data that has been recorded or that is to be recorded in the memory block M1 in alternation with the other memory block M2 and its associated controller CRTC2 being 20 allocated to the playback stage 3 for graphically reproducing on the screen E sequences of images that are recorded in the memory block M2.

~When operating in this way, the playback stage 3 can thus have permanent access to one or other of the memory 25 blocks Ml or M2 without access to a single memory block alternating from time to time between the acquisition stage 2 and th playback stage 3. Thus, while sequences of images are being displayed and animated on the screen E on the basis of digital data taken from one of the memory blocks, new image sequences can be being recorded in the other memory block prior to being displayed and animated, thus making it possible to ensure perfect continuity in the animation on the screen.

A variant embodiment is shown in Figure 3 to show a practical extension of the possibilities of the system of the invention.

8 In this variant, each of the controllers CRTC1 and CRTC2 is connected: to the processor unit CPU by means of an auxiliary or buffer memory M10 that is 16 bits or 32 bits wide with two go-and-return flow controlling bits, for example, in order to increase processing speeds; and to an auxiliary or buffer memory MO, the two memories MO being connected by a bus b13 to a coder/decoder CODEC, in turn connected to a hard disk D, e.g. with an interposed auxiliary or buffer memory Mil.

Thus, for operations of compressing and/or decompressing sequences of images using an interfield method in compliance with a standard MPEG I, MPEG II, or CCITT H.261), the coder/decoder CODEC is used 15 which is required simultaneously to handle at least three data streams so as to process an image i+l on the basis :of a previously processed image i.

In image sequence compression mode, the coder/decoder CODEC handles the following: 20 a first input stream of video signals that are digitized and stored in a memory plane of memory block Ml by the controller CRTC1, said input stream coming from an external source, such as a camera for example; a s".cond input stream of reference signals that are 25 digitized and stored in memory block M2 by the controller CRTC2, said signals corresponding to the preceding image i; and a third output stream of digitized signals that have been compressed and processed by the coder/decoder and that enable image i+l to be reconstiructed on the basis of image i, said signals being sent to the hard disk D.

In image decompression mode, the coder/decoder CODEC handles: a first input stream corresponding to a stream of compressed digitized signals taken from the hard disk D; a second input stream corresponding to the digitized signals that have been decompressed in a preceding step and that are taken from one of the memory blocks Ml or M2 and are delivered to the coder/decoder via the screen controller associated with that memory block Ml or M2; and a third output stream of processed decompressed digitized signals corresponding to image i+l, said signals being seat to the other stream controller for display on the screen.

These signal compression and decompression operations are greatly facilitated by the presence of two controllers CRTC1 and CRTC2.

In general, the operation of the apparatus can be inverted, in that graphics images are not played back but images are captured from the screen E for recording in 15 the memory blocks Ml and M2 and for subsequently storing in an auxiliary memory, for example.

Thus, the playback stage 3 can acquire data corresponding to a sequence of images and can store that data alternately in memory block Ml or M2 via the 20 associated controller CRTC1 or CRTC2, and the acquisition stage 3 can read said data alternately from the other memory block M2 or Ml via its associated controller CRTC2 or CRTC1 and store that data in an auxiliary memory or in a hard disk unit.

25 Facilities for real time animation of images on a television screen can be used, in particular in consumer type interactive games, for example.

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Claims

1. A system for acquiring and playing back an animated image secquence in real time, the system including at least one data acquisition stage constituted by a memory block and read/write stage formed by a screen or image controller driven by a central processor unit for reading and writing digital data in the memory block corresponding to at least one image sequence, and a data playback stage, 1C wherein the data acquisition stage includes at least two self-contained memory blocks respectively associated with at least two screen or image controllers, in such a manner as to allocate one of the memory blocks and its associated controller to the data acquisition stage to perform management operations on data recorded in or to be recorded in the memory block in alternation with at least one other memory block and its associated controller being allocated to the playback stage for reproducing image sequences recorded in said other memory block.

2. A system according to claim 1, wherein the playback stage includes at least one converter device at least four converting digital data taken from a memory block and corresponding to an image sequence into an analog 25 or digital television standard.

3. A system according to claim 1 or 2, wherein each *memory block is constituted by standard dynamic random access memories of the synchronous or the asynchronous type. C.

4. A system according to any one of claims 1 to 3, wherein each controller is interposed h .ween the memory block with which it is associated and the central control unit, and is connected to the converter device. AJRF??.

5. A system according to any one of claims 1 to 4, ii K 1 I 11 wherein the controllers are directly connected to a peripheral such as an auxiliary memory or a hard disk unit, for the purpose of directly receiving data that results from compressing or performing any other processing on the images to be played back on the graphics screen.

6. A system according to any one of claims 1 to wherein the playback stage acquires data corresponding to an image sequence and stores said data alternatively in a memory block via its associated controller, while the acquisition stage reads said data alternately from the other memory block via the associated controller and stores said data in an auxiliary memory or in a hard disk unit.

7. A system for acquiring and playing back an animated image sequence in real time, substantially as o* herein described with reference to the accompanying drawings. e 20 Dated this day of a LA FRANCAISE DES JEUX By their Patent Attorneys GRIFFITH HACK Fellows Institute of Patent and e 25 Trade Mark Attorneys of Australia 4 0 ABSTRACT A system for acquiring and playing back an animated sequence of images in real time, the system being of the type comprising at least one data acquisition stage (2) for acquiring data corresponding to the sequence of images and a playback stage for playing back said sequence of images in graphics form on a screen The acquisition stage comprises at least two self- contained memory blocks (Ml, M2) respectively associated with at least two screen or image controllers (CRTC1, CRTC2) so as to enable one of the memory blocks (Ml or M2) and its associated controller (CRTC1 or CRTC2) to be allocated to the data acquisition stage for performing management operations on data recorded or in to be recorded in said memory block in alternation with the other memory block (M2 or Ml) and its associated controller (CRTC2 or CRTC1) being allocated to the playback stage for reproducing image sequenccs recorded in said other memory block.