CN101005349B - A clock synchronization method and system - Google Patents

Abstract

The invention belongs to the technical field of communication, and discloses a clock synchronization method and system. Using the synchronization system, the following method is adopted: on the multi-service transmission platform MSTP equipment side, the synchronous transmission module STM-N line clock is generated through a phase-locked loop The operating clock of the MSTP device side Ethernet physical layer interface PHY chip; the MSTP device side Ethernet PHY chip transmits the operating clock of the MSTP device side Ethernet PHY chip to the receiving device side first Ethernet PHY through the Ethernet physical layer interface chip; the first Ethernet PHY chip on the receiving device side extracts the working clock of the Ethernet PHY chip on the MSTP device side; tracks and processes the working clock extracted by the first Ethernet PHY chip on the receiving device side, and generates a receiving device The system clock is used as the reference clock. Therefore, low-cost and high-precision clock synchronization in the IP network transmission mode is realized.

Description

A clock synchronization method and system

technical field

The invention belongs to the technical field of communication, and in particular relates to a clock synchronization method and system.

Background technique

As we all know, good network synchronization performance has a great impact on telecommunication services. The synchronization network built to ensure the performance of communication services has constituted the three major support networks for telecommunication services together with the signaling network and the telecommunication management network. Poor network synchronization often brings a series of problems, especially in wireless networks, poor synchronization often leads to poor voice quality, high call drop rate, low handover success rate, inability to access and many other problems.

From the perspective of actual networking, due to the small number of general core network and base station controller equipment, relatively high-cost GPS (Global Position System, Global Positioning System) or BITS (Building Integrated Timing Supply System, comprehensive building timing supply system) can be used System) as a synchronization reference source, so it is relatively easy to obtain a good clock synchronization reference source, and the wireless base station equipment is at the end of the wireless network, the specific access methods vary widely, and the number of base stations is relatively large, considering the cost limitation of realizing synchronization , it is not suitable to use GPS or BITS as the clock reference source. If a common OCXO (Oven Control Crystal Oscillator, constant temperature crystal oscillator) device is used, although the cost is lower compared to GPS or BITS, the air interface carrier of the wireless base station equipment has higher requirements on the stability of the clock. According to the 3GPP agreement, An accuracy of 0.05ppm is required. In order to meet the high-precision clock requirements required by wireless base stations, it is necessary to track GPS or BITS or perform regular calibration, and the overall cost is still relatively high. So relatively speaking, the clock synchronization of the base station is the most difficult part to solve in the whole wireless network.

With the continuous evolution of 3G (3rd Generation, third-generation mobile communication technology) standards, its corresponding transmission network is also constantly evolving. Initially, TDM (Time Division Multiplex, time division multiplexing), ATM (Asynchronous Transfer Mode, asynchronous transmission mode) extracts the synchronous clock signal for the base station from the service code stream through the physical bearer, and now the transmission network has gradually developed into an IP (Internet Protocol, Internet Protocol) network. Since the IP network was originally used to solve the mutual communication between computers and ensure the reliable transmission of data, it does not care about the delay and jitter of the network during transmission, and there is no common clock synchronization relationship between network elements. Therefore, the original TDM The low-cost solution under the transmission mode of ATM and ATM becomes more and more difficult under the IP transmission mode that utilizes Ethernet to bear the weight of.

MSTP (Multi-Service Transport platform, multi-service transmission platform) technology originated from SDH (Synchronous Digital Hierarchy, synchronous digital system), after several years of continuous development, it has included SDH, PDH (Pseudo-SDH, quasi-synchronous digital system) , POS (Packet Over SDH/SONET, packet transmission based on synchronous digital system/synchronous optical network), Ethernet, ATM, RPR (Resilient Packet Ring, resilient packet ring), SHDSL (Symmetrical High-bit-rate Digital Subscriber Line, symmetrical high Bit rate digital subscriber loop), DDN (Digital Date Network, digital data network) and other technologies, it can not only realize the comprehensive transmission of services through multi-service convergence, but also realize the service integration through its own adaptability to multiple types of services Access and processing have adapted to the development trend of the integration of various technologies and become a relatively complete technical system. Judging from the current form, it is a better choice to adopt MSTP networking for wireless base station access.

In the case of adopting MSTP networking as the wireless base station access network, the 2048kHz external synchronization port provided by the MSTP access device can be used to provide clock reference for the base station. However, the existing base station equipment does not have an interface matching the 2048kHz external synchronization port, and the distance of the 2048kHz external synchronization port is limited, which is not suitable for the environment where the base station is connected through optical fiber. Moreover, within the limited extended distance, work such as lightning protection and outdoor protection needs to be done, resulting in relatively high complexity and cost of the project.

To sum up, in the current transmission network where the IP network is dominant, there is no good low-cost and high-precision clock synchronization solution.

Contents of the invention

The technical problem to be solved by the present invention is to provide a clock synchronization method and system to realize low-cost and high-precision clock synchronization in the IP network transmission mode.

In order to solve the problems of the technologies described above, the purpose of the present invention is achieved through the following technical solutions:

First, the present invention provides a clock synchronization method, including:

On the MSTP equipment side of the multi-service transmission platform, the synchronous transmission module STM-N line clock is generated through the phase-locked loop to generate the working clock of the Ethernet physical layer interface PHY chip on the MSTP equipment side;

The MSTP device side Ethernet PHY chip transmits the working clock of the MSTP device side Ethernet PHY chip to the receiving device side first Ethernet PHY chip through the Ethernet physical layer interface;

The first Ethernet PHY chip on the receiving device side extracts the working clock of the Ethernet PHY chip on the MSTP device side;

Track and process the working clock extracted by the first Ethernet PHY chip on the receiving device side, and generate the system clock of the receiving device as a reference clock.

Optionally, before tracking and processing the working clock extracted by the first Ethernet PHY chip on the receiving device side, the working clock extracted by the first Ethernet PHY chip on the receiving device side is further passed through a phase-locked loop Generates the clock to be tracked and processed by the receiving device reference clock.

Optionally, after generating the system clock of the receiving device, further include:

The receiving device generates the working clock of the second Ethernet PHY chip on the receiving device side through a phase-locked loop for the system clock of the receiving device;

The second Ethernet PHY chip on the receiving device side transmits the working clock of the second PHY chip on the receiving device side to the Ethernet PHY chip on the lower-level cascading device side through the Ethernet physical layer interface;

The Ethernet PHY chip on the side of the cascaded device extracts the working clock;

The working clock extracted by the Ethernet PHY chip on the side of the cascaded device is tracked and processed to generate a system clock of the cascaded device.

Preferably, the synchronization state information SSM of the STM-N line clock is sent to the receiving device side through the network layer, the medium access control sublayer MAC layer, the Ethernet physical layer or through the MAC layer and the Ethernet physical layer, and the receiving device receives the The SSM judges whether the reference clock is invalid, and if so, maintains the clock frequency before the failure as the reference clock.

Preferably, the tracking and processing of the operating clock extracted by the first Ethernet PHY chip at the receiving device side is performed through a software phase-locked loop.

Preferably, the phase-locked loop for processing the STM-N line clock on the MSTP device side and/or the system clock of the receiving device is a phase-locked loop with a voltage-controlled crystal oscillator.

At the same time, the present invention provides a clock synchronization system, including: MSTP equipment side phase-locked loop unit, MSTP equipment side Ethernet PHY chip, receiving equipment side first Ethernet PHY chip, receiving equipment system clock unit, wherein:

The phase-locked loop unit on the MSTP device side processes the STM-N line clock to generate the working clock of the Ethernet PHY chip on the MSTP device side;

The MSTP device side Ethernet PHY chip transmits the working clock of the MSTP device side Ethernet PHY chip to the receiving device side first Ethernet PHY chip through the Ethernet physical layer interface;

The first Ethernet PHY chip on the receiving device side extracts the received clock;

The system clock unit of the receiving device is configured to track and process the clock extracted by the first Ethernet PHY chip on the receiving device side to generate a system clock of the receiving device.

Optionally, a phase-locked loop unit on the receiving device side is also included, configured to process the clock extracted by the first Ethernet PHY chip on the receiving device side to generate a clock to be tracked and processed by the system clock unit of the receiving device.

Optionally, it also includes: a second phase-locked loop unit on the receiving device side, a second Ethernet PHY chip on the receiving device side, an Ethernet PHY chip on the cascading device side, and a system clock unit on the cascading device, wherein:

The second phase-locked loop unit on the receiving device side is configured to process the system clock of the receiving device to generate the working clock of the second Ethernet PHY chip on the receiving device side;

The second Ethernet PHY chip on the receiving device side is used to transfer the working clock of the second Ethernet PHY chip on the receiving device to the Ethernet PHY chip on the cascaded device side;

The Ethernet PHY chip on the cascaded device side is used to extract the received working clock;

The system clock unit of the cascaded device is configured to track and process the clock extracted by the Ethernet PHY chip on the side of the cascaded device, and generate a system clock of the cascaded device.

Preferably, the clock synchronization system also includes an SSM transmission unit, and the system clock unit also includes a clock holding unit, wherein:

The SSM transmission unit includes a MAC layer and an Ethernet physical layer, and is used to transfer the synchronization state information SSM of the STM-N line clock to the clock holding unit of the receiving device;

The clock holding unit is configured to use the clock stored before the failure as the reference clock when the received SSM shows that the reference clock is invalid.

In the above clock synchronization system, the phase-locked loop unit on the MSTP device side and/or the second phase-locked loop unit on the receiving device side include: a phase detector, a filter, and an oscillator, wherein:

a phase detector, configured to judge the phase difference between the input STM-N line clock and the clock frequency output by the oscillator, and generate a control signal corresponding to the phase difference;

a filter, configured to filter the control signal output by the phase detector to generate a control signal for controlling the oscillator;

The oscillator adjusts its own oscillation frequency under the control signal output from the filter.

Preferably, the oscillator is a voltage-controlled crystal oscillator.

It can be seen from the above technical solutions that, compared with the method of using clock reference sources such as GPS or BITS on the receiving device side, the present invention uses a simple and easy-to-obtain phase-locked loop unit and an Ethernet PHY chip inherent in the transmission network to realize clock synchronization , the implementation cost is lower; at the same time, compared with the method of using 2048kHz as the external synchronization reference source, the present invention transmits the STM-N line clock signal through the Ethernet physical layer, the present invention does not require special maintenance, and the maintenance cost is low, so , generally speaking, the cost of the present invention is relatively low.

At the same time, the present invention uses the STM-N line clock with good synchronization performance as the synchronization clock reference source on the receiving device side, which is not affected by pointer adjustment, and the phase-locked loop has good clock recovery performance, and directly through the Ethernet physical The layer transmits the clock to the receiving device side, and the clock delay is small. Therefore, the present invention can meet the requirement of high clock precision for wireless base stations and other devices.

Further, the receiving device tracks and processes the clock extracted by the Ethernet PHY chip on the receiving device side through the software phase-locked loop unit, so that the generated system clock is more stable.

In addition, the present invention does not need to transmit the clock through the IP layer or the MAC layer, and does not occupy additional transmission bandwidth.

Description of drawings

FIG. 1 is a functional block diagram of a clock synchronization system according to Embodiment 1 of the present invention;

FIG. 2 is a functional block diagram of a clock synchronization system according to Embodiment 2 of the present invention;

FIG. 3 is a functional block diagram of a clock synchronization system according to Embodiment 3 of the present invention;

FIG. 4 is a functional block diagram of a clock synchronization system according to Embodiment 4 of the present invention.

Detailed ways

In order to make the advantages and features of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and examples.

MSTP technology is developed on the basis of SDH and can integrate multi-service access. The main transmission and bearer mode of MSTP network is still based on SDH, and SDH network generally undergoes good synchronization planning. Among them, the SDH signal is composed of one or more synchronous transmission module STM-N signals of different orders, where N is a positive integer. For the SDH optical cable access system, at present, N=1, 4 or 16, the bit rate of the basic module STM-1 signal is 155.52Mbit/s, and the bit rate of the STM-N signal is N×155.520Mbit/s. The STM-N signal can be formed by interleaving bytes of N basic modules STM-1. Regardless of the value of N, the frame repetition period of STM-N is 125μs, 8000 frames per second. The STM-N line clock is not affected by pointer adjustments and can be used as a good synchronization reference source.

On the MSTP device side, the STM-N line clock is generated by the phase-locked loop unit to generate the working clock of the Ethernet physical layer interface PHY chip on the MSTP device side, and the Ethernet PHY chip transmits the working clock to the receiving device side through the Ethernet physical layer The first Ethernet PHY chip extracts the clock through the first Ethernet PHY chip on the receiving device side, and tracks and processes the extracted clock to obtain the system clock of the receiving device. The system clock of the receiving device is synchronized with the STM-N line clock on the MSTP device side.

Currently, Ethernet has four transmission rates supported by optical fiber and twisted pair media, namely: 10Mbps standard Ethernet, 100Mbps Fast Ethernet FE, 1000Mbps Gigabit Ethernet GE and 10GE Ethernet. The following embodiments are described using FE and GE which are commonly used in synchronization networks.

The implementation of clock synchronization of base station equipment is taken as an example to describe in detail.

Embodiment 1. The MSTP device transmits the STM-N line clock to the base station side through the Ethernet physical layer. Referring to FIG. 1 , the details will be described below.

Step 11: The MSTP device generates the working clock of the PHY chip of the Ethernet physical layer interface on the side of the MSTP device through the phase-locked loop unit.

The phase-locked loop unit generally includes a phase detector, a filter and an oscillator, wherein the phase detector generates a control signal by comparing the phase difference between the input STM-N line clock and the output frequency of the oscillator; The signal output by the phaser is filtered and smoothed to eliminate jitter; the oscillator adjusts its own oscillation frequency according to the control signal output by the filter, and moves closer to the frequency of the input signal until the error is eliminated and locked.

The physical layer interface is the part of the protocol that deals with the physical/electrical characteristics of the signal, also known as the PHY.

Since the operating clock frequency of the PHY chip may be different from the STM-N line clock frequency, in the phase-locked loop circuit, the oscillator frequency can be divided or multiplied first, and the input STM-N line clock frequency can be divided or multiplied at the same time , so as to generate the working clock of the Ethernet PHY chip.

Step 12: The Ethernet PHY chip on the MSTP device side sends a data stream through the FE/GE interface to transmit the working clock to the first Ethernet PHY chip on the base station side.

Wherein, the data flow generated by the MSTP device side includes data and clock information at the same time, and the clock is transmitted to the first Ethernet PHY chip at the base station side together with the data.

Step 13: the first Ethernet PHY chip at the base station side extracts the clock from the data stream.

Step 14: The base station system clock unit tracks and processes the clock extracted by the base station Ethernet PHY chip, thereby generating a base station system clock, which is synchronized with the STM-N line clock.

Step 15: The service processing unit performs service processing under the control of the base station system clock, for example, the service processing unit performs codec, modulation and demodulation.

In order to better meet the clock jitter performance requirements of the Ethernet PHY chip, the oscillator in the phase-locked loop used to generate the working clock required by the Ethernet PHY chip on the MSTP device side can use a VCXO (Voltage Control Crystal Oscillator, voltage-controlled crystal oscillator).

In addition, a software phase-locked loop can be added to the system clock unit of the base station. The software phase-locked loop can better eliminate signal jitter, so that a more stable system clock can be generated. The software phase-locked loop has incomparable advantages over the hardware phase-locked loop. For example, the flexible processing capability of the CPU can be used to realize optimal filtering or adaptive filtering, and the integral value can be forcibly changed to achieve fast locking.

Embodiment 1 realizes the synchronization between the base station system clock and the STM-N line clock on the MSTP equipment side. In order to ensure the good performance of the clock synchronization system, Embodiment 2 is used to illustrate that the system clock can still be used when the reference clock generated by the system clock unit of the base station fails. There is only a small frequency deviation from the reference clock for a period of time, see Figure 2.

The same as Embodiment 1 includes: the clock frequency required by the MSTP device side Ethernet PHY chip is still generated by the phase-locked loop unit on the MSTP device side, and the MSTP device side Ethernet PHY chip sends the data stream through the FE/GE interface to transfer the clock frequency Passed to the first Ethernet PHY chip on the base station side, the first Ethernet PHY chip on the base station side extracts the clock from the received data stream, and the system clock unit of the base station tracks and processes the extracted clock to generate the system clock of the base station, which is The service processing unit in the base station provides a reference clock, for example, as a reference clock for post-stage codec, modem, and intermediate radio frequency.

The difference is that if the MSTP network is a two-layer network, the MSTP device will also pass the received SSM (Synchronization Status Message, synchronization status information) through the MAC (Media Access Control, media access control sublayer) layer, physical The first Ethernet PHY chip on the base station side sends the SSM message to the The system clock unit indicates the performance of the reference clock generated by the system clock of the base station.

If the MSTP network is a three-layer network, the MSTP device needs to send the received SSM to the Ethernet PHY chip on the MSTP device side through the IP layer, MAC layer, and physical layer in sequence, and the Ethernet PHY chip on the MSTP device side sends the SSM to The first Ethernet PHY chip on the base station side, the first Ethernet PHY chip on the base station side sends the SSM message to the base station system clock unit through the physical layer, MAC layer, and IP layer in sequence, indicating the performance of the reference clock generated by the system clock.

The system clock unit can sample the clock frequency used, calculate the average value and store it. When the SSM shows that the reference clock generated by the base station system clock unit cannot meet the quality requirements of the base station system clock, the reference clock fails, and the base station system clock no longer tracks, but uses the clock frequency stored before the base station system reference clock fails as its reference The clock works, and the base station system clock unit works in hold mode.

SSM can only indicate the quality level of the current reference clock, and cannot be set artificially. For example, according to the ITU-T standard, four different quality levels are adopted: the reference master clock is mainly cesium clock, and the clock level is G.811; the slave clock of the transfer office is mainly rubidium clock, which is generally provided by BITS. The clock level is G.812T; the slave clock of the end office is used for the local digital synchronization network, and the clock level standard is G.812L; the equipment timing source is provided by the device, and the clock level standard is G.813.

Referring to SSM, it can be described by the synchronization status byte S1 of the multiplex section overhead in the STM-N signal, for example, the 5th to 8th bits of S1 are used to indicate the synchronization status information indication. 0010 means G.811, 0100 means G.812T, 0111 means G.812L, and 1111 means different from clock synchronization.

When the STM-N line clock fails, the MSTP device can detect it. For example, the LOS signal indicates that the input signal is lost. The base station system clock works with the clock frequency stored before the reference clock fails as its reference clock.

It can be seen that the SSM is sent to the receiving device such as the base station as a performance indicator of the reference clock. When the reference clock fails, the system clock on the receiving device side maintains the clock frequency before the failure as the reference clock, thereby avoiding the clock frequency when the clock fails under abnormal conditions. The local clock continues to track with large errors.

On the basis of the above two embodiments, a phase-locked loop can be added behind the Ethernet PHY chip at the base station side to generate the base station system clock, and the software phase-locked loop in the system clock unit of the base station is specially used to eliminate the jitter of the clock signal. As shown in FIG. 3 , this optimization scheme is described as Embodiment 3.

Embodiment 3, same as the previous two examples, this implementation scheme also requires the MSTP device to generate the working clock of the Ethernet PHY chip through the phase-locked loop and transmit it to the first Ethernet PHY chip at the base station side, and the chip extracts the clock.

At the same time, the MSTP device sends the SSM generated by the device to the base station side through the IP layer, MAC layer, physical layer and through the Ethernet PHY chip. The first Ethernet PHY chip on the base station side extracts the SSM and transmits it through the MAC layer and IP layer. To the base station system clock unit, indicating the performance of the base station system clock, if the base station system clock fails, the base station system clock unit enters the hold mode, and uses the clock frequency stored before the failure as its reference clock to work.

The difference is that the first Ethernet PHY chip on the base station side does not directly send the clock to the base station system clock unit after extracting the clock, but sends it to the phase-locked loop unit, and the phase-locked loop unit performs frequency multiplication or frequency division to generate The system clock of the base station is used as the reference clock, and the base station system clock unit tracks and processes it to obtain a base station system clock that meets the quality requirements, which is used as a reference clock for subsequent codec, modulation and demodulation, and medium radio frequency services.

In addition, in the case of cascading multiple base stations, the base station equipment can provide a clock reference for the lower cascaded base stations through the output cascaded Ethernet. Referring to FIG. 4 , this solution is taken as the fourth embodiment.

Embodiment 4, as described in Embodiment 3, a base station is synchronized with the STM-N line clock on the MSTP equipment side, if another base station is cascaded with this base station, then the system clock of this base station can be used as another The clock reference source of the base station equipment, as shown in Figure 4, the base station 1 obtains the synchronous clock reference source (not shown in Figure 4) from the MSTP device through the Ethernet, and the base station 2 obtains the synchronous clock reference source from the base station 1 through the Ethernet. The following only describes clock synchronization between cascaded base stations.

As shown in Figure 4, the phase-locked loop unit generates the working clock required by the second Ethernet PHY chip on the base station 1 side, and the second Ethernet PHY clock on the base station 1 side transmits the working clock to the second Ethernet PHY chip on the base station 2 side through the FE/GE interface. An Ethernet PHY chip. Since the data stream sent by the base station 1 side contains other data besides the clock information, the first Ethernet PHY chip on the base station 2 side first extracts the clock from the data stream. Then, the jitter is eliminated by the phase-locked loop unit. If necessary, the input frequency can also be adjusted to generate the system clock of base station 2. The system clock unit of base station 2 can further eliminate the jitter of the clock signal through the software phase-locked loop, thereby generating Base clock for quality requirements.

At the same time, base station 1 sends the SSM of this device to the second Ethernet PHY chip on the side of base station 1 through the IP layer, MAC layer, and Ethernet physical layer, and the chip is transmitted to the first Ethernet PHY chip on the side of base station 2 through the FE/GE interface. PHY chip. The first Ethernet PHY chip on the base station 2 side sequentially transmits the SSM to the system clock unit of the base station 2 through the Ethernet physical layer, the MAC layer, and the IP layer, as a performance indication of the reference clock generated by the system clock unit of the base station 2.

In this way, when the SSM shows that the clock quality meets the quality requirements, the system clock of base station 2 tracks the system clock of base station 1 processed by the phase-locked loop and the Ethernet PHY chip, and provides a reference clock for the service processing unit of base station 2, such as The reference clock for subsequent codec and modulation and demodulation services.

The system clock unit of the base station 2 can sample the used clock frequency, calculate the average value and store it. When the SSM indicates that the clock reference source fails, the system clock of the base station 2 is in a holding state, and the clock frequency stored before the reference clock fails is used as the reference clock to work.

The same is true for the clock synchronization of cascaded base stations below the cascaded base stations. The clock information generated from the Ethernet from the upper base station is used as the reference source of the system clock unit to process the system clock of the base station. The physical layer is passed to the lower-level cascaded base station as a clock reference source. Since the base station controller equipment is less, the number of base stations is large. This method directly keeps synchronization between a small number of base stations and the base station controller, and it is particularly beneficial to keep the clock synchronization of the entire network under the layout of cascaded base stations under these few base stations.

It can be seen that the base station transmits the local clock to the lower-level base stations cascaded with it through the Ethernet physical layer. The cascaded base stations at all levels can use the system clock of the upper-level cascaded base station as a synchronization reference source, so that the clock synchronization of the entire network can be realized.

Of course, if the cascaded base stations communicate through TDM or ATM networks instead of Ethernet, the cascaded base stations can also implement clock synchronization by extracting clocks from service code streams, which will not be described in detail here.

In the above embodiments, the synchronous clock is transmitted through the FE or GE Ethernet in the MSTP networking mode. Of course, other types of Ethernet can also be used, and will not be listed one by one.

The method for implementing clock synchronization has been described in detail through the embodiments above, and the system for implementing clock synchronization will be illustrated below with an example.

The clock synchronization system shown in Figure 1 includes: MSTP device side PLL unit 11, Ethernet PHY chip 12, base station side first Ethernet PHY chip 13 and base station system clock unit 14, the functions of each unit are described in detail below :

MSTP equipment side PLL unit 11 generates the operating clock of MSTP equipment side Ethernet PHY chip 12 by processing the STM-N line clock;

The Ethernet PHY chip 12 on the MSTP device side transmits the working clock to the first Ethernet PHY chip 13 on the base station side through the FE/GE interface;

The first Ethernet PHY chip 13 on the base station side extracts the received clock;

The base station system clock unit 14 tracks and processes the clock extracted by the first Ethernet PHY chip 13 on the base station side to generate a system clock of the base station equipment.

The above system realizes the synchronization of the base station system clock and the STM-N line clock of the MSTP access equipment.

In this way, at the base station side, the base station system clock unit 14 can provide the base station service processing unit 15 with a reference clock. The base station service processing unit 15 performs codec, modulation and demodulation, and intermediate radio frequency under the control of the base station system clock unit.

In the above-mentioned clock synchronization system, the phase-locked loop unit 11 on the MSTP device side is used to process the STM-N line clock to generate the working clock of the Ethernet PHY chip on the MSTP device side, and at least includes a phase detector 11, a filter 12, an oscillator 13, of which:

The phase detector 11 is used to judge the phase difference between the input STM-N line clock frequency and the frequency output by the oscillator 13, and generate a control signal corresponding to the phase difference between the two signals and input it to the filter 12;

The filter 12 is used to filter the input control signal, eliminate jitter, and output the control signal to control the oscillator 13;

The oscillator 13 is used to adjust its own frequency under the action of the control signal, so that the frequency of the oscillator is gradually approached to the frequency of the input signal, and the frequency difference is gradually eliminated to lock.

If the operating clock of the MSTP device side Ethernet PHY chip 12 is different from the STM-N line clock, a frequency divider or a frequency multiplier is also included in the phase locked loop unit 11 for generating the MSTP device side Ethernet The working clock of the network PHY chip 12.

The PLL unit can be a discrete device, or a chip integrated with the PLL unit.

Wherein, the oscillator 12 may be a VCXO, so that the jitter performance of the clock generated by the phase-locked loop 11 on the MSTP side can better meet the clock jitter performance requirements of the Ethernet PHY chip on the MSTP side.

In addition, the base station system clock unit 14 may also include a software phase-locked loop unit. The software phase-locked loop unit is used to track the clock extracted by the Ethernet PHY chip, eliminate jitter, and generate the system clock of the base station.

The clock synchronization system in Figure 1 is further optimized, and SSM is added to indicate the performance of the base station's reference clock, as shown in Figure 2 .

On the basis of the clock synchronization system in Fig. 1, a MAC layer is added to transmit the SSM to the Ethernet PHY chip 12 on the MSTP device side, and to transmit the SSM sent by the first Ethernet PHY chip 13 on the base station side to the base station system clock unit 14. As shown in Figure 2, on the MSTP device side, the MAC layer transmits the SSM to the MSTP device side Ethernet PHY chip 12; on the base station side, the MAC layer transmits the SSM sent by the first Ethernet PHY chip 13 on the base station side to the base station service processing unit 14.

The MSTP network shown in Figure 2 is a two-layer network. If the MSTP network is a three-layer network, an IP layer and a MAC layer need to be added on the basis of the clock synchronization system shown in Figure 1. Now, on the MSTP equipment side, the IP layer delivers the SSM to the MAC layer, and the MAC layer then transmits the SSM to the Ethernet PHY chip 12 on the MSTP equipment side; on the base station side, the MAC layer sends the first Ethernet PHY chip 13 on the base station side The SSM is delivered to the IP layer, and the IP layer is then delivered to the system clock unit 14 of the base station.

The system clock unit of the base station also includes a clock holding unit, which can sample the clock frequency used, calculate the average value and store it. If the SSM shows that the quality of the reference clock cannot meet the quality of service requirements or is invalid, the clock holding unit works in the hold mode, using the clock frequency stored before the failure as the reference clock.

It can be seen that the SSM is sent to the receiving device such as the base station as a performance indicator of the reference clock. When the reference clock fails, the system clock on the receiving device side maintains the clock frequency before the failure as the reference clock, thereby avoiding the clock frequency when the clock fails under abnormal conditions. The local clock continues to track with large errors.

The clock synchronization system shown in FIG. 2 is further optimized. As shown in FIG. 3, a phase-locked loop unit 31 is added on the base station side to generate the base station system clock unit 14 according to the clock extracted by the first Ethernet PHY chip 13 on the base station side The system clock is used as the clock reference. The PLL unit 31 can further improve the jitter performance of the system, and provide a reference clock with better performance for the system clock unit 14 .

If the clock frequency extracted by the first Ethernet PHY chip 13 on the base station side is different from the clock frequency of the base station system clock unit, the phase-locked loop unit 31 also includes a frequency modulation unit, so that the output of the first Ethernet PHY chip on the base station side The clock frequency is equal to the clock frequency required by the base station system.

The clock synchronization system described in the embodiment of the present invention can also be used to realize the synchronization between the base station and its subordinate base station that have synchronized the STM-N line clock. The clock synchronization system shown in Figure 4 includes: STM-N as the clock reference The system clock unit 14 of the base station 1 of the source, the phase-locked loop unit 41, the second Ethernet PHY chip 42 on the base station 1 side, and the first Ethernet PHY chip 43 on the base station 2 side, the phase-locked loop unit 44, and the system of the base station 2 A clock unit 45, a service processing unit 46 of base station 1, a service processing unit 46 of base station 2, and MAC layers 47 and 48 required for SSM transmission.

The following describes the functions of each component of the system:

The system clock unit 14 of the base station 1 keeps synchronization with the STM-N line clock, and transmits the clock of the system to the phase-locked loop unit 41;

The phase-locked loop unit 41 generates the working clock of the second Ethernet PHY chip 42 at the base station 1 side according to the clock of the system clock unit 14;

The second Ethernet PHY chip 42 on the base station 1 side transmits the working clock to the first Ethernet PHY chip 43 on the base station 2 side through the FE/GE interface;

The first Ethernet PHY chip 43 on the base station 2 side extracts the received clock;

The phase-locked loop unit 44 processes the clock extracted by the first Ethernet PHY chip 43 on the base station 2 side, and transmits it to the system clock unit 45 of the base station 2;

The system clock unit 45 of the base station 2 tracks the clock generated by the phase-locked loop unit 44 to generate the system clock of the base station 2; under the instruction of the SSM, it provides a reference clock for the service processing unit 46 of the base station 2.

The MAC layers 47 and 48 are used as SSM transmission units for transferring the SSM generated by the base station 1 to the system clock unit of the base station 2 .

The same is true for the clock synchronization of cascaded base stations below the cascaded base stations. The clock information generated from the Ethernet from the upper base station is used as the reference source of the system clock unit to process the system clock of the base station. The physical layer is passed to the lower-level cascaded base station as a clock reference source. Since the base station controller equipment is less, the number of base stations is large. This method directly keeps synchronization between a small number of base stations and the base station controller, and it is particularly beneficial to keep the clock synchronization of the entire network under the layout of cascaded base stations under these few base stations.

It can be seen that the base station transmits the local clock to the lower-level base stations cascaded with it through the Ethernet physical layer. The cascaded base stations at all levels can use the system clock of the upper-level cascaded base station as a synchronization reference source, so that the clock synchronization of the entire network can be realized.

Of course, if the cascaded base station equipment communicates not through Ethernet, but through TDM or ATM network, the equipment cascaded with it can also adopt the solution of extracting the clock from the service code stream to achieve clock synchronization, which will not be described in detail here .

In the above embodiments, the synchronous clock is transmitted through the FE or GE type of Ethernet physical layer in the MSTP networking mode. Of course, other types of Ethernet physical layers can also be used, and will not be listed one by one.

A clock synchronization method and system provided by the present invention has been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the method of the present invention. and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. For example, the embodiment of the present invention is not limited to only transmitting the clock for the base station , using the STM-N line clock using MSTP equipment to provide clocks for other equipment through the physical layer is also included in the protection of the present invention. In summary, the content of this specification should not be construed as limiting the present invention.

Claims (10)

1. a clock synchronizing method is characterized in that, comprising:

Synchronous Transport Module level-N STM-N line clock is generated the work clock of MSTP equipment side ethernet physical layer interface PHY chip at multiservice transport platform MSTP equipment side by phase-locked loop;

MSTP equipment side Ethernet PHY chip is delivered to the receiving equipment side first Ethernet PHY chip by the ethernet physical layer interface with the work clock of described MSTP equipment side Ethernet PHY chip;

The receiving equipment side first Ethernet PHY chip extracts the work clock of described MSTP equipment side Ethernet PHY chip;

The work clock that the described receiving equipment side first Ethernet PHY chip is extracted is followed the tracks of and handled, and the system clock that generates receiving equipment is as reference clock;

Receiving equipment generates the work clock of the receiving equipment side second Ethernet PHY chip by phase-locked loop to the system clock of receiving equipment;

The receiving equipment side second Ethernet PHY chip is delivered to the cascade device side Ethernet PHY of subordinate chip by the ethernet physical layer interface with the work clock of described receiving equipment side the 2nd PHY chip;

Cascade device side Ethernet PHY chip extracts work clock;

The work clock that described cascade device side Ethernet PHY chip is extracted is followed the tracks of and handled, generate the system clock of cascade device.

2. clock synchronizing method as claimed in claim 1, it is characterized in that, before the described work clock that the described receiving equipment side first Ethernet PHY chip is extracted was followed the tracks of and handled, further the work clock that the described receiving equipment side first Ethernet PHY chip is extracted generated the clock that the receiving equipment reference clock will be followed the tracks of and handle by phase-locked loop.

3. as claim 1 or 2 each described clock synchronizing methods, it is characterized in that, further comprise:

By network layer, MAC sublayer MAC layer, ethernet physical layer or by MAC layer, ethernet physical layer the Synchronization Status Message SSM of STM-N line clock is sent to the receiving equipment side, whether receiving equipment lost efficacy according to the SSM judgment standard clock that receives, if the clock frequency before then keeping losing efficacy is a reference clock.

4. as claim 1 or 2 each described clock synchronizing methods, it is characterized in that the described work clock that the receiving equipment side first Ethernet PHY chip is extracted is followed the tracks of and handled by software phase-lock loop and undertaken.

5. as claim 1 or 2 each described clock synchronizing methods, it is characterized in that,

The oscillator that the MSTP equipment side is used for the phase-locked loop of the work clock of STM-N line clock generation MSTP equipment side ethernet physical layer interface PHY chip is a VCXO.

6. clock system, it is characterized in that, comprise: MSTP equipment side phase locked-loop unit, MSTP equipment side Ethernet PHY chip, the receiving equipment side first Ethernet PHY chip, receiving equipment system clock unit, receiving equipment side second phase locked-loop unit, the receiving equipment side second Ethernet PHY chip, cascade device side Ethernet PHY chip and cascade device system clock unit, wherein:

MSTP equipment side phase locked-loop unit is handled the work clock that generates MSTP equipment side Ethernet PHY chip to the STM-N line clock;

MSTP equipment side Ethernet PHY chip is delivered to the receiving equipment side first Ethernet PHY chip by the ethernet physical layer interface with the work clock of described MSTP equipment side Ethernet PHY chip;

The receiving equipment side first Ethernet PHY chip extracts the clock that receives;

The receiving equipment system clock unit is used for the clock that the described receiving equipment side first Ethernet PHY chip extracts is followed the tracks of and handled, and generates the system clock of receiving equipment;

Receiving equipment side second phase locked-loop unit is used for described receiving equipment system clock is handled the work clock that generates the receiving equipment side second Ethernet PHY chip;

The receiving equipment side second Ethernet PHY chip is used for the work clock of the described receiving equipment second Ethernet PHY chip is delivered to cascade device side Ethernet PHY chip;

Cascade device side Ethernet PHY chip is used to extract the described work clock that receives;

The cascade device system clock unit is used for the clock that described cascade device side Ethernet PHY chip extracts is followed the tracks of and handled, and generates the system clock of cascade device.

7. clock system as claimed in claim 6, it is characterized in that, also comprise receiving equipment side chain phase ring element, be used for the clock that the receiving equipment side first Ethernet PHY chip is extracted is handled the clock that generation receiving equipment system clock unit will follow the tracks of and handle.

8. as claim 6 or 7 each described clock systems, it is characterized in that clock system also comprises the SSM transmission unit, system clock unit also comprises the clock holding unit, wherein:

The SSM transmission unit comprises MAC layer, ethernet physical layer, is used for the Synchronization Status Message SSM of STM-N line clock is delivered to the clock holding unit of receiving equipment;

The clock holding unit is used for when the SSM that receives shows that reference clock lost efficacy, with the clock that stored before losing efficacy as reference clock.

9. as claim 6 or 7 each described clock systems, it is characterized in that described MSTP equipment side phase locked-loop unit and/or receiving equipment side second phase locked-loop unit comprise: phase discriminator, filter, oscillator, wherein:

Phase discriminator is used to judge the STM-N line clock of input and the phase difference of the clock frequency that described oscillator is exported, and produces corresponding to the control signal that differs;

Filter, the control signal that is used for phase discriminator is exported is carried out filtering, produces the control signal that is used for control generator;

Oscillator is regulated self frequency of oscillation under the control signal of the output of filter.

10. clock system as claimed in claim 9 is characterized in that, described oscillator is a VCXO.

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