CN101661925A - Chip package - Google Patents

Abstract

The invention provides a chip package, which comprises a circuit substrate, a first chip, a plurality of first bonding wires, an element, a first adhesive layer and a packaging colloid. The first chip is provided with a first active surface, a first back surface and a plurality of first welding pads, the first back surface is adhered to the circuit substrate, and the first chip is electrically connected to the circuit substrate. The first bonding wires are electrically connected to the circuit substrate and the first bonding pads of the first chip. The element is configured above the first active surface of the first chip. The first adhesive layer is adhered between the first active surface and the element and does not cover the first welding pad. The first adhesive layer comprises a first B-stage adhesive layer adhered to part of the first active surface of the first chip and a second B-stage adhesive layer adhered between the first B-stage adhesive layer and the element.

Description

chip packaging

technical field

The present invention relates to a chip package, and more particularly to a chip package capable of improving reliability and reducing production cost.

Background technique

In recent years, chip packages with multiple stacked chips have gradually been developed. Chip packaging is to stack multiple chips on top of a carrier and electrically connect to the carrier through bonding wires or bumps, where the bumps are gold bumps. bump), copper bump (copper bump), polymer bump (polymer bump) or solder bump (solder bump), and the carrier is, for example, a printed circuit board (print circuit board) or a lead-frame (lead-frame ). Generally, each chip stacked on a carrier can be adhered to other chips or carriers by glue such as tape or liquid adhesive. In particular, when using adhesive tape as an adhesive for a die-bonding process or a chip-stacking process, an adhesive tape of appropriate size and stickiness is attached to the die or carrier. When the liquid adhesive is used as the glue in the chip bonding process or the chip stacking process, the liquid adhesive is firstly disposed on the chip or the carrier, and the liquid adhesive is cured when the chip is bonded to the carrier or afterward. The adhesive tape used here is not suitable for mass production because the adhesive tape must be cut to an appropriate size before the die bonding process or chip stacking process. In addition, the reliability of chip packaging will be affected due to the difficulty in controlling the thickness of the liquid adhesive. Therefore, how to improve the reliability of chip packaging and reduce the production cost of chip packaging is an urgent problem to be solved.

Contents of the invention

The invention provides a chip package, which can improve reliability and reduce production cost.

The present invention provides a chip package, which includes a circuit substrate, a first chip, a plurality of first bonding wires, a component, a first adhesive layer and a packaging compound. The first chip has a first active surface, a first back surface opposite to the first active surface, and a plurality of first bonding pads arranged on the first active surface, wherein the first back surface of the first chip is adhered to on the circuit substrate, and the first chip is electrically connected to the circuit substrate. The first bonding wire is electrically connected to the circuit substrate and the first bonding pad of the first chip. The element is arranged above the first active surface of the first chip. The first adhesive layer is adhered between the first active surface of the first chip and the component, and does not cover the first welding pad. The first adhesive layer includes a first B-stage adhesive layer and a second B-stage adhesive layer. The first B-stage adhesive layer adheres to a part of the first active surface of the first chip. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the component. The encapsulant is disposed on the circuit substrate and covers the first chip, the component, the first adhesive layer and the first bonding wire.

In an embodiment of the present invention, the above-mentioned circuit substrate has a plurality of first connection pads. The first connection pad is electrically connected to the first pad through the first bonding wire.

In an embodiment of the present invention, the above-mentioned element is a second chip. The second chip has a second back surface and a second active surface opposite to the second back surface. The second back surface of the second chip is adhered to the first active surface of the first chip through the first adhesive layer.

In an embodiment of the present invention, the above-mentioned chip package further includes a plurality of second bonding wires. The second bonding wire is electrically connected to the second chip and the circuit substrate.

In an embodiment of the present invention, the above-mentioned second chip has a plurality of second bonding pads, and the circuit substrate has a plurality of second connection pads. The second connection pad is electrically connected to the second pad through the second bonding wire.

In an embodiment of the present invention, the above-mentioned element is a heat sink.

In an embodiment of the present invention, the above-mentioned chip package further includes a second adhesive layer. The second adhesive layer is adhered between the first back surface of the first chip and the circuit substrate.

In an embodiment of the present invention, the above-mentioned second adhesive layer includes a third B-stage adhesive layer and a fourth B-stage adhesive layer. A third B-stage adhesive layer is adhered to the first backside of the first chip. The fourth B-stage adhesive layer is adhered between the third B-stage adhesive layer and the circuit substrate.

In an embodiment of the present invention, the edge of the above-mentioned first chip is aligned with the edge of the device.

In an embodiment of the present invention, the edge of the above-mentioned first chip is not aligned with the edge of the device.

Based on the above, since the first adhesive layer used in the present invention has a first B-stage adhesive layer and a second B-stage adhesive layer in a semi-solid state, the thickness of the first adhesive layer is easy to control. In addition, since the first adhesive layer can be directly formed on the active surface of the wafer, it is beneficial to mass production.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic cross-sectional view of a chip package according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a chip package according to a second embodiment of the present invention.

3 and 4 are schematic cross-sectional views of a chip package according to a third embodiment of the present invention.

Description of main component symbols:

100, 200, 300, 400: chip package

110: circuit substrate

112: first connection pad

114: Second connection pad

120: first chip

120a: first active surface

120b: first back

122: The first welding pad

130: first welding wire

140: Elements

140a: second active surface

140b: second back

142: Second welding pad

150: first adhesive layer

150a: First B-stage adhesive layer

150b: second B-stage adhesive layer

160: encapsulation colloid

170: second adhesive layer

170a: third B-stage adhesion layer

170b: Fourth B-stage adhesion layer

180: Second welding wire

Detailed ways

FIG. 1 is a schematic cross-sectional view of a chip package according to a first embodiment of the present invention. Please refer to FIG. 1 , in this embodiment, the chip package 100 includes a circuit substrate 110 , a first chip 120 , a plurality of first bonding wires 130 , a component 140 , a first adhesive layer 150 and an encapsulant 160 . The first chip 120 has a first active surface 120a, a first back surface 120b opposite to the first active surface 120a, and a plurality of first bonding pads 122 disposed on the first active surface 120a, wherein the first chip The first back surface 120 b of the chip 120 is adhered on the circuit substrate 110 , and the first chip 120 is electrically connected to the circuit substrate 110 . The first bonding wires 130 are electrically connected to the circuit substrate 110 and the first bonding pads 122 of the first chip 120 . The element 140 is disposed above the first active surface 120 a of the first chip 120 . The first adhesive layer 150 is adhered between the first active surface 120 a of the first chip 120 and the device 140 , and does not cover the first bonding pad 122 . The first adhesive layer 150 includes a first B-stage adhesive layer 150a and a second B-stage adhesive layer 150b. The first B-stage adhesive layer 150 a is adhered on a part of the first active surface 120 a of the first chip 120 . The second B-stage adhesive layer 150b is adhered between the first B-stage adhesive layer 150a and the component 140 . The encapsulant 160 is disposed on the circuit substrate 110 and covers the first chip 120 , the component 140 , the first adhesive layer 150 and the first bonding wires 130 . For example, the circuit substrate 110 can be a circuit board, such as FR-4 substrate, FR-5 substrate, BT substrate or other suitable substrates.

Referring to FIG. 1 again, the circuit substrate 110 has a plurality of first connection pads 112 , and these first connection pads 112 are disposed on a surface of the circuit substrate 110 . The first connection pads 112 are electrically connected to the first pads 122 through the first bonding wires 130 respectively. In this embodiment, the first bonding wire 130 is a gold wire formed by a wire bonding process.

In this embodiment, the element 140 is a heat sink. In order to improve the heat dissipation effect, the encapsulant 160 may only cover part of the device 140 (heat sink), in other words, part of the surface of the device 140 (heat sink) is exposed to the outside of the encapsulant 160 . In other embodiments, the encapsulant 160 can also completely cover the device 140 (heat sink). Please refer to FIG. 1 again, the encapsulant 160 can protect the first bonding wires 130 from being damaged.

In this embodiment, a first adhesive layer 150 disposed on the first active surface 120a of the first chip 120 can be fabricated through the following steps. Firstly, a wafer is provided, and the wafer has a plurality of first chips 120 arranged in an array. Next, a first two-stage adhesive layer is formed on the first active surface 120a of the first chip 120, and the first two-stage adhesive layer is partially cured by heating or ultraviolet radiation to form a first B-stage adhesive layer 150a . After that, a second double-stage adhesive layer is formed on the first B-stage adhesive layer 150a. Finally, the second double-stage adhesive layer is partially cured by heating or ultraviolet radiation to form the second B-stage adhesive layer 150b. At this time, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b are formed on the active surface of the wafer. After the wafer is cut (singulated), the first chip 120 with the first adhesive layer 150 formed on the first active surface 120a can be obtained. Therefore, the first adhesive layer 150 having the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b is beneficial to mass production. In addition, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b may be formed by spin coating, printing or other suitable methods.

While the second B-stage adhesive layer 150b is partially cured, the first B-stage adhesive layer 150a can also be further cured to have better mechanical strength, so as to maintain the distance between the first chip 120 and the device 140 ( gap). At this time, the first B-stage adhesive layer 150a can be partially cured or fully cured to provide sufficient supporting force, while the second B-stage adhesive layer 150b can be in a soft and sticky state.

In this embodiment, after the device 140 is adhered to the first chip 120 or the encapsulant 160 covers the device 140, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b are fully cured. For example, the first B-stage adhesive layer 150 a and the second B-stage adhesive layer 150 b can be 8008 or 8008HT of ABLESTIK, and the glass transition temperature thereof is approximately between 80 degrees Celsius and 300 degrees Celsius. In addition, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b can also be 6200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 provided by HITACHI Chemical CO., Ltd., and Its glass transition temperature is approximately between minus 40°C and 150°C. The glass transition temperature of the first B-stage adhesive layer 150a may be greater than, equal to, or less than the glass transition temperature of the second B-stage adhesive layer 150b. In addition, for example, some conductive particles (such as silver particles, copper particles and gold particles) can be doped into the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b to increase the conductivity.

Please refer to FIG. 1 again, the chip package 100 may further include a second adhesive layer 170 attached between the first back surface 120 b of the first chip 120 and the circuit substrate 110 . In other words, the first chip 120 is attached to the circuit substrate 110 through the second adhesive layer 170 . In this embodiment, the size of the first chip 120 is substantially the same as the size of the component 140 (heat sink). Furthermore, the edge of the first chip 120 is aligned with the edge of the component 140 (heat sink).

FIG. 2 is a schematic cross-sectional view of a chip package according to a second embodiment of the present invention. Please refer to FIG. 2 and FIG. 1 at the same time. In this embodiment, the chip package 200 in FIG. 2 is similar to the chip package 100 in FIG. 170 includes a third B-stage adhesive layer 170a adhered to the first back surface 120b of the first chip 120 and a fourth B-stage adhesive layer 170b adhered between the third B-stage adhesive layer 170a and the circuit substrate 110 . It must be noted here that the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b can be formed on the first back surface 120b of the first chip 120 by spin coating, printing or other suitable methods or on the circuit substrate 110.

In this embodiment, the size of the first chip 120 is substantially the same as the size of the component 140 (heat sink). Furthermore, the edge of the first chip 120 is not aligned with the edge of the component 140 (heat sink).

In this embodiment, after the first chip 120 is attached to the circuit substrate 110 or the encapsulant 160 covers the first chip 120, the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b will be completely cured. The third B-stage adhesive layer 170 a and the fourth B-stage adhesive layer 170 b can be 8008 or 8008HT of ABLESTIK, and the glass transition temperature thereof is approximately between 80 degrees Celsius and 300 degrees Celsius. In addition, the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b can also be 6200, 6201, 6202C of ABLESTIK or SA-200-6, SA-200-10 provided by HITACHI Chemical CO., Ltd., and Its glass transition temperature is approximately between minus 40°C and 150°C. The glass transition temperature of the third B-stage adhesive layer 170a may be greater than, equal to, or less than the glass transition temperature of the fourth B-stage adhesive layer 170b. In addition, for example, some conductive particles (such as silver particles, copper particles and gold particles) can be doped into the third B-stage adhesive layer 170a and the fourth B-stage adhesive layer 170b to increase the conductivity.

3 and 4 are schematic cross-sectional views of a chip package according to a third embodiment of the present invention. Please refer to FIG. 3 and FIG. 1 at the same time. In this embodiment, the chip package 300 in FIG. 3 is similar to the chip package 100 in FIG. 1 . The main difference between them is that the component 140 in FIG. 3 is a second chip. In addition, please refer to FIG. 4 and FIG. 2 at the same time. In this embodiment, the chip package 400 in FIG. 4 is similar to the chip package 200 in FIG. .

Please refer to FIG. 3 and FIG. 4 at the same time, the circuit substrate 110 has a plurality of first connection pads 112 and a plurality of second connection pads 114, wherein the first connection pads 112 and the second connection pads 114 are arranged on the same side of the circuit substrate 110. surface. The device 140 (second chip) has a second back surface 140b and a second active surface 140a opposite to the second back surface 140b. The second back surface 140b of the device 140 (the second chip) is attached to the first active surface 120a of the first chip 120 through the first adhesive layer 150 . The component 140 (second chip) includes a plurality of second bonding pads 142 disposed on the second active surface 140a. In addition, the chip package 300 further includes a plurality of second bonding wires 180 , and these second bonding wires 180 are electrically connected to the second bonding pads 142 of the component 140 (second chip) and the second connection pads 114 of the circuit substrate 110 . In this embodiment, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b may be formed on the backside of the wafer having the device 140 (the second chip). After the wafer is cut (singulated), the device 140 (second chip) with the first adhesive layer 150 formed on the second back surface 140b can be obtained. Therefore, the first adhesive layer 150 having the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b is beneficial to mass production. In addition, the first B-stage adhesive layer 150a and the second B-stage adhesive layer 150b may be formed by spin coating, printing or other suitable methods. It should be noted here that the element 140 can also be a passive element, such as a capacitor, a resistor or an inductor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (10)

1. A chip package, comprising: a circuit substrate; A first chip has a first active surface, a first back surface opposite to the first active surface, and a plurality of first bonding pads arranged on the first active surface, wherein the first chip of the first chip the first back is adhered to the circuit substrate, and the first chip is electrically connected to the circuit substrate; a plurality of first bonding wires electrically connected to the circuit substrate and the first bonding pads of the first chip; an element configured above the first active surface of the first chip; A first adhesive layer, adhered between the first active surface of the first chip and the element, and does not cover the first pads, wherein the first adhesive layer includes: a first B-stage adhesive layer adhered to a portion of the first active surface of the first chip; and a second B-stage adhesive layer adhered between the first B-stage adhesive layer and the component; and An encapsulant is disposed on the circuit substrate and covers the first chip, the component, the first adhesive layer and the first bonding wires. 2 . The chip package according to claim 1 , wherein the circuit substrate has a plurality of first connection pads electrically connected to the first pads through the first bonding wires. 3. The chip package according to claim 1, wherein the element is a second chip having a second back surface and a second active surface opposite to the second back surface, the second chip of the second chip The second back is adhered to the first active surface of the first chip through the first adhesive layer. 4. The chip package as claimed in claim 3, further comprising a plurality of second bonding wires electrically connected to the second chip and the circuit substrate. 5. The chip package according to claim 4, wherein the second chip has a plurality of second bonding pads, and the circuit substrate has a plurality of second connection pads, and the second connection pads pass through the The second bonding wires are electrically connected to the second bonding pads. 6. The chip package as claimed in claim 1, wherein the component is a heat sink. 7. The chip package as claimed in claim 1, further comprising a second adhesive layer adhered between the first back surface of the first chip and the circuit substrate. 8. The chip package according to claim 7, wherein the second adhesive layer comprises: a third B-stage adhesive layer adhered to the first backside of the first chip; and A fourth B-stage adhesive layer adhered between the third B-stage adhesive layer and the circuit substrate. 9. The chip package of claim 1, wherein an edge of the first chip is aligned with an edge of the component. 10. The chip package of claim 1, wherein an edge of the first chip is not aligned with an edge of the component.

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