CN102710109B - Current limiting circuit for DC/DC (Direct Current/Direct Current) converter - Google Patents

Abstract

The invention discloses a current limiting circuit of a DC/DC converter, comprising: a power switch tube connected to the DC/DC converter, a sampling resistor connected to the power switch tube, a current-voltage conversion circuit connected to the sampling resistor, and A reference current generation circuit connected to the current-voltage conversion circuit, and an operational amplifier connected to the power switch tube and the current-voltage conversion circuit. The invention detects the load current of the DC/DC converter by connecting a metal sampling resistor with a small resistance value in series in the current path, and the obtained detection voltage is compared with an accurate reference voltage with a small voltage value through a high-precision operational amplifier circuit. The value is amplified. When the load current exceeds the preset current threshold, the conduction degree of the power tube is controlled through the negative feedback of the loop to achieve current limitation, and the power consumption is small and the precision is high.

Description

A Current Limiting Circuit of DC/DC Converter

technical field

The invention belongs to the technical field of integrated circuit design, and in particular relates to a current limiting circuit of a DC/DC converter.

Background technique

In small and medium power DC/DC converters, especially DC/DC converters used in Power over Ethernet (PoE) (Power over Ethernet) systems, when abnormal conditions such as overload and short circuit occur in the load, the power flowing through the DC/DC converter The load current will be much higher than the current during normal operation. Working in such a high current state for a long time will cause power devices such as power tubes or Ethernet cables to overheat and burn out, or even damage the entire system. Therefore, for DC/DC converters, a current limiting circuit is required to set a current threshold for the load current, and limit the current flowing through the load when abnormal conditions such as load overload and short circuit occur in the system to prevent it from continuing to increase at this current limiting point. , so as to protect the system.

The current limiting point of the current limiting circuit is usually set according to the variation range of the load current and the safe working area of power devices such as power tubes. In a Power over Ethernet system, the transmitted power level determines the current limit point, which is usually clearly specified in the corresponding IEEE802.3af or IEEE802.3at standards, and the sensitivity of the Ethernet cable to heat requires the system to limit The flow point is very precise.

The traditional current limiting circuit detects the load current of the DC/DC converter by connecting a sampling resistor in series in the current path, compares the detected voltage signal with the threshold voltage of the transistor, and compares the conduction voltage of the power transistor in the load circuit. The pass degree is controlled to realize current limitation. The specific circuit principle is shown in Figure 1. In this circuit, the circuit part in the dotted line box is the current limiting circuit, mainly including the detection resistor R1, the power transistor M1 and the MOS transistor M2. The power transistor M1 in the figure is used to limit the load current I ₀ of the DC/DC converter, and the sampling The resistor R1 is used to detect the load current _I0 , and the gate voltage of the power transistor M1 is adjusted through the MOS transistor M2 to control its conduction degree to realize current limitation. During normal operation, the load current I ₀ is relatively small, and the voltage across the sampling resistor R1 is relatively small, which is not enough to turn on M2. At this time, the gate terminal of the power transistor M1 maintains a high level, and the current flows normally. When the load is overloaded or short-circuited and other abnormal conditions occur, the load current _I0 increases, and the voltage across the sampling resistor R1 also increases. When the voltage increases above the threshold voltage of the M2 tube, M2 is turned on, and the power tube M1 is pulled down. The voltage at the gate terminal controls the conduction degree of the power transistor M1, limits the current to the set current limit point, and prevents it from increasing further.

The approximate expression of the current limit point of the above-mentioned current limit circuit is I _CL =V _th /R1; wherein, V _th is the threshold voltage of M2, and is usually about 0.7V, which is relatively large. When the circuit works in the current limit state R1 will dissipate a lot of power. At the same time, the resistance values of V _th and resistor R1 vary greatly with the process angle. Resistor R1 is usually implemented with polysilicon resistors and has a positive temperature coefficient, while V _th has a negative temperature coefficient. It can be seen from the above expression , the current limit point of the current limit circuit is very imprecise, and it will change greatly when different process angles and temperature changes.

In order to reduce the power consumption of the current limiting circuit, at the same current level, the voltage of the sampling resistor should be reduced, that is, the compared reference voltage should be reduced. In order to achieve high-precision current limiting, the sampling resistor used and the reference voltage to be compared are required to be very accurate, and a high-precision operational amplifier is required to amplify the difference between the small detection voltage and the reference voltage. When the temperature changes, according to the temperature coefficient of the sampling resistor, the compared reference voltage should follow the change of the resistance value of the resistor, so that high-precision current limitation can be realized.

Contents of the invention

In view of the above-mentioned technical defects in the prior art, the present invention provides a current limiting circuit of a DC/DC converter, which has high precision and low power consumption.

A current limiting circuit of a DC/DC converter, comprising:

The power switch tube is used to control the load current of the DC/DC converter; the input end of the power switch tube is connected to the DC/DC converter, the output end is connected to a sampling resistor, and the other end of the sampling resistor is grounded ;

A reference current generating circuit, configured to generate a reference current signal;

A current-voltage conversion circuit, configured to convert the reference current signal into a reference voltage signal, collect the voltage of the sampling resistor at the same time, and convert the voltage into a detection voltage signal;

The operational amplifier circuit is used to amplify the difference between the reference voltage signal and the detection voltage signal, and output a switch control signal to control the power switch tube.

Preferably, the resistance value of the sampling resistor is 0.08Ω; the smaller the resistance value of the sampling resistor, the lower the power consumption of the current limiting circuit, the smaller the corresponding reference voltage needs to be, and the more difficult it is to achieve a high accuracy At the same time, it is more difficult for the operational amplifier used to accurately amplify the difference between the detection voltage and the reference voltage; therefore, the resistance value is based on factors such as the current limit point, power consumption requirements, and the convenience of resistor implementation. The optimal value.

Preferably, the reference current generating circuit is composed of three MOS transistors, four triodes and a resistor; wherein, the source of the MOS transistor _M1 is connected to the source of the MOS transistor _M2 and the source of the MOS transistor _M3 connected to the power supply voltage in parallel, the gate of MOS transistor _M1 is connected to the drain of MOS transistor _M2 , the gate of MOS transistor _M2 , the gate of MOS transistor _M3 and the collector of triode _Q4 , and the gate of MOS transistor _M3 The drain is the output end of the reference current generation circuit, the drain of the MOS transistor _M1 is connected to the collector of the transistor _Q3 , the base of the transistor _Q3 and the base of the transistor _Q4 , and the emitter of the transistor _Q3 is connected to the transistor _Q1 The collector of the transistor _Q2 is connected to the base of the transistor Q2, the emitter of the transistor QX is connected to the collector of the transistor _Q2 and the base of the transistor _Q1 , the emitter of the transistor _Q2 is connected to one end of the resistor _R1 , and the transistor _Q1 The emitter of the resistor _R1 is connected to the other end and grounded. Among them, the MOS transistors M ₁ ~ M ₃ are all PMOS transistors, and the transistors Q ₁ ~ Q ₄ are all NPN type transistors; the ratio of the emitter area of the transistor Q ₂ to the transistor Q ₁ is equal to the emitter area of the transistor Q ₃ and the transistor Q ₄ The ratio is m, the width-to-length ratio of MOS transistor _M1 and MOS transistor _M2 is the same, and the width-to-length ratio of MOS transistor _M3 is n times the width-to-length ratio of MOS transistor _M1 , and both m and n are natural numbers greater than 1 .

The reference current generation circuit structure can generate PTAT current that changes with temperature, so that the reference voltage changes accordingly, which can compensate the positive temperature coefficient of the sampling resistor to a certain extent, reduce the correlation between the current limit point and temperature, and improve the system performance. accuracy.

Preferably, the current-voltage conversion circuit is composed of two resistors; wherein, one end of the resistor _R2 is connected to the reference current generating circuit and the positive-phase input of the operational amplifier circuit, the other end of the resistor _R2 is grounded, and the resistor _R3 One end of R3 is connected to the sampling resistor, and the other end of the resistor _R3 is connected to the inverting input end of the operational amplifier circuit. The resistor R ₂ and the resistor R ₃ have the same resistance value, and are realized by resistors or resistor strings made of the same material, and are completely matched.

Connecting the voltage of the sampling resistor to the inverting input terminal of the operational amplifier circuit through the resistor _R3 can eliminate the influence of the input triode base current of the operational amplifier circuit on the accuracy of the system.

Preferably, the operational amplifier circuit is composed of twenty-seven MOS transistors and four triodes; wherein, the drain of the MOS transistor _N9 is connected to the source of the MOS transistor _N13 , the source of the MOS transistor _N14 , and the MOS transistor The source of _N15 , the source of MOS transistor _N19 , the source of MOS transistor _N20 , the source of MOS transistor _N23 and the source of MOS transistor _N24 are connected and connected to the power supply voltage, the gate of MOS transistor _N13 It is connected to the drain of MOS transistor _N13 , the source of MOS transistor _N16 , the gate of MOS transistor _N14 and the gate of MOS transistor _N15 , and the drain of MOS transistor _N14 is connected to the source of MOS transistor _N17 , the drain of MOS transistor _N15 is connected to the source of MOS transistor _N18 , the gate of MOS transistor _N16 is connected to the drain of MOS transistor _N16 , the drain of MOS transistor _N1 , the gate of MOS transistor _N17 and The gate of MOS transistor _N18 is connected, the drain of MOS transistor _N17 is connected to the gate of MOS transistor _N9 , the collector of transistor _T3 is connected to the drain of MOS transistor N10, and the drain of MOS transistor _N18 is connected to the gate of transistor _N9 . The collector of _T4 is connected to the source of MOS transistor _N27 , the base of triode _T3 is connected to the base of triode _T4 , the source of MOS transistor _N9 is connected to the drain of MOS transistor N2, and the drain of MOS transistor _N2 is connected to the base of triode _T3 . The emitter is connected to the emitter of the transistor _T1 , the emitter of the transistor _T4 is connected to the emitter of the transistor _T2 , the base of the transistor _T1 and the base of the transistor _T2 are respectively the positive-phase input terminal and the Inverting input terminal, the gate of MOS transistor _N27 is connected to the drain of MOS transistor _N27 , the drain of MOS transistor _N3 is connected to the gate of MOS transistor _N12 , the source of MOS transistor _N10 is connected to the drain of MOS transistor _N4 The drain of the MOS transistor _N10 is connected to the gate of the MOS transistor _N11 , the drain _of the MOS transistor _N11 is connected to the drain of the MOS transistor N21, and the source of the MOS transistor _N12 is connected to the gate of the MOS transistor _N7 The drain of the MOS transistor _N12 is connected to the drain of the MOS transistor _N25 and is the output terminal of the operational amplifier circuit, the gate of the MOS transistor _N19 is connected to the source of the MOS transistor _N22 , and the MOS transistor _N20 The gate of the MOS transistor _N20 is connected to the drain, the drain of the MOS transistor _N19 is connected to the source of the MOS transistor _N21 , the gate of the MOS transistor _N21 is connected to the drain of the MOS transistor _N5 , and the drain of the MOS transistor _N22 The gate of the MOS transistor _N22 is connected to the gate, the gate of the MOS transistor _N23 is connected to the source of the MOS transistor _N26 , the gate of the MOS transistor _N24 is connected to the drain of the MOS transistor _N24 , and the MOS transistor _N23 The drain of the MOS transistor _N25 is connected to the source, the gate of the MOS transistor _N25 is connected to the drain of the MOS transistor _N8 , the gate of the MOS transistor _N26 is connected to the drain of the MOS transistor _N26 , and the MOS transistor _N1 The gate of the MOS transistor _N2 , the gate of the MOS transistor _N3 , The gate of MOS transistor _N4 , the gate of MOS transistor _N5 , the gate of MOS transistor _N6 , the drain of MOS transistor _N6 , the gate of MOS transistor _N7 and the gate of MOS transistor _N8 are connected and receive A given reference current signal, the source of MOS transistor _N1 and the source of MOS transistor _N2 , the source of MOS transistor _N3 , the source of MOS transistor _N4 , the source of MOS transistor _N5 , the source of MOS transistor N ₆ , the source of MOS transistor _N7 , the source of MOS transistor _N8 , the source of MOS transistor _N11 , the collector of transistor _T1 and the collector of transistor _T2 are connected and grounded. Among them, the MOS transistors N ₁ to N ₁₂ are all NMOS transistors, the MOS transistors N ₁₃ to N ₂₇ are all PMOS transistors, the transistors T ₁ to T ₂ are all PNP transistors, and the transistors T ₃ to T ₄ are all NPN transistors.

The operational amplifier circuit uses a triode as the input stage, and the bias voltage is very small. At the same time, when the circuit is in the current-limiting state, the difference between the base current of the non-inverting input terminal and the inverting input terminal is eliminated, and the detection voltage and the reference voltage can be accurately measured. The difference is magnified.

The principle of the current limiting circuit of the present invention is to detect the load current of the DC/DC converter through a metal sampling resistor with a small resistance in series in the current path, and the obtained detection voltage and the accurate reference voltage with a small voltage value are passed through the high The precision operational amplifier circuit performs difference amplification. When the load current exceeds the preset current threshold, the conduction degree of the power tube is controlled through the negative feedback of the loop to achieve current limitation.

The above reference voltage is obtained by the PTAT current generated by the reference current generating circuit acting on the resistor. By adjusting the size of the PTAT current and the resistance, the positive temperature coefficient of the metal sampling resistor can be eliminated to a certain extent, and the current limit point and temperature can be reduced. The correlation; the high-precision operational amplifier circuit uses a triode as the input stage, and the bias voltage is very small. At the same time, when the circuit is in the current-limiting state, the difference between the base current of the non-inverting input terminal and the inverting input terminal can be eliminated, and the detection voltage and The difference of the reference voltage is amplified with high precision; the resistance value of the sampling resistor and the reference voltage are both small and accurate, and the reference voltage can compensate the correlation between the metal sampling resistor and the temperature to a certain extent, so the current limitation of the present invention The circuit has low power consumption and high precision.

Description of drawings

FIG. 1 is a schematic structural diagram of a conventional current limiting circuit.

FIG. 2 is a schematic structural diagram of the current limiting circuit of the present invention.

FIG. 3 is a schematic structural diagram of a reference current generating circuit.

FIG. 4 is a schematic structural diagram of a current-to-voltage conversion circuit.

FIG. 5 is a schematic structural diagram of an operational amplifier circuit.

Detailed ways

In order to describe the present invention more specifically, the technical solutions and related principles of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in FIG. 2 , a current limiting circuit of a DC/DC converter includes: a power switch tube M, a sampling resistor R, a reference current generation circuit, a current-voltage conversion circuit and an operational amplifier circuit.

The power switch tube M is used to control the load current _I0 of the DC/DC converter; its input end is connected to the DC/DC converter, its output end is connected to one end of the sampling resistor R, and the other end of the sampling resistor R is grounded; in this implementation In the mode, the resistance value of the sampling resistor R is 0.08Ω.

The reference current generation circuit is used to generate the reference current signal I _PTAT , which is connected to the current-voltage conversion circuit; in this embodiment, the reference current generation circuit consists of three MOS transistors M ₁ ~M ₃ , four transistors Q ₁ ~Q ₄ and Composed of a resistor _R1 , as shown in Figure 3; wherein, the source of the MOS transistor _M1 is connected to the source of the MOS transistor _M2 and the source of the MOS transistor _M3 and connected to the power supply voltage VDD, and the gate of the MOS transistor _M1 The pole is connected with the drain of MOS transistor _M2 , the gate of MOS transistor _M2 , the gate of MOS transistor _M3 and the collector of triode _Q4 , the drain of MOS transistor _M3 is the output end of the reference current generation circuit, and the MOS The drain of the tube _M1 is connected to the collector of the transistor _Q3 , the base of the transistor _Q3 and the base of the transistor _Q4 , and the emitter of the transistor _Q3 is connected to the collector of the transistor _Q1 and the base of the transistor _Q2 , the emitter of transistor _Q4 is connected to the collector of transistor _Q2 and the _base of transistor _Q1 , the emitter of transistor _Q2 is connected to one end of resistor R1, and the emitter of transistor _Q1 is connected to the other end of resistor _R1 connected and grounded.

MOS tubes M ₁ ~ M ₃ are all PMOS tubes, transistors Q ₁ ~ Q ₄ are all NPN type transistors, M ₁ and M ₂ have the same width-to-length ratio, and the emitter area ratio of Q ₂ and Q ₁ is equal to Q ₃ and Q ₄ The emitter area ratio is m, and the width-to-length ratio of M ₃ is n times the width-to-length ratio of M ₁ /M ₂ ; in this embodiment, m=8, n=4.

The current-voltage conversion circuit is used to convert the reference current signal I _PTAT into a reference voltage signal V _P , and at the same time collect the voltage V _SENSE of the sampling resistor R, and convert V _SENSE into a detection voltage signal V _N , V _SENSE =I ₀ R, I ₀ is the load current of the DC/DC converter; as shown in Figure 4, in this embodiment, the current-voltage conversion circuit is composed of two resistors _R2 ~ _R3 ; wherein, one end of the resistor _R2 is connected to the reference current generating circuit The output terminal is connected to the positive-phase input terminal of the operational amplifier circuit, the other end of the resistor _R2 is grounded, one end of the resistor _R3 is connected to one end of the sampling resistor R, and the other end of the resistor _R3 is connected to the inverting input terminal of the operational amplifier circuit; The resistor R ₂ and the resistor R ₃ have the same resistance value, and are realized by resistors or resistor strings made of the same material, and are completely matched.

The operational amplifier circuit is used to amplify the difference between the reference voltage signal V _P and the detection voltage signal V _N , and output the switch control signal GATE to control the power switch tube M, and its output terminal is connected to the control terminal of the power switch tube M; as shown in the figure 5, in this embodiment, the operational amplifier circuit is composed of twenty-seven MOS transistors N ₁ ~ N ₂₇ and four triodes T ₁ ~ T ₄ ; wherein, the drain of MOS transistor N ₉ is connected to the drain of MOS transistor N ₁₃ Source, the source of MOS transistor _N14 , the source of MOS transistor _N15 , the source of MOS transistor _N19 , the source of MOS transistor _N20 , the source of MOS transistor _N23 and the source of MOS transistor _N24 The gate of the MOS transistor _N13 is connected to the drain of the MOS transistor _N13 , the source of the MOS transistor _N16 , the gate of the MOS transistor _N14 and the gate of the MOS transistor _N15 . The drain of _N14 is connected to the source of MOS transistor _N17 , the drain of MOS transistor _N15 is connected to the source of MOS transistor _N18 , the gate of MOS transistor _N16 is connected to the drain of MOS transistor _N16 , the MOS transistor The drain of _N1 , the gate of MOS transistor _N17 are connected to the gate of MOS transistor _N18 , the drain of MOS transistor _N17 is connected to the gate of MOS transistor _N9 , the collector of triode _T3 and MOS transistor _N10 The drain of the MOS transistor _N18 is connected to the collector of the transistor _T4 and the source of the MOS transistor _N27 , the base of the transistor _T3 is connected to the base of the transistor _T4 and the source of the MOS transistor _N9 It is connected to the drain of the MOS transistor _N2 , the emitter of the transistor _T3 is connected to the emitter of the transistor _T1 , the emitter of the transistor _T4 is connected to the emitter of the transistor _T2 , the base of the transistor _T1 is connected to the emitter of the transistor _T2 The bases of the MOS transistor _N27 and the drain of _the MOS transistor N27, the drain of the MOS transistor _N3 and the gate of the MOS transistor _N12 are respectively the non-inverting and inverting input terminals of the operational amplifier circuit The source of MOS transistor _N10 is connected to the drain of MOS transistor _N4 , the gate of MOS transistor _N10 is connected to the gate of MOS transistor _N11 , the drain of MOS transistor _N11 and the drain of MOS transistor _N21 The source of MOS transistor _N12 is connected to the drain of MOS transistor _N7 , the drain of MOS transistor _N12 is connected to the drain of MOS transistor _N25 and is the output terminal of the operational amplifier circuit, and the gate of MOS transistor _N19 The pole is connected to the source of MOS transistor _N22 , _the gate of MOS transistor _N20 is connected to the drain of MOS transistor N20, the drain of MOS transistor _N19 is connected to the source of MOS transistor _N21 , and the gate of MOS transistor _N21 The pole is connected to the drain of MOS transistor _N5 , the gate of MOS transistor _N22 and the drain of MOS transistor _N22 , the gate of MOS transistor _N23 is connected to the source of MOS transistor _N26 , and the gate of MOS transistor _N24 Connected to the drain of MOS transistor N ₂₄ , MOS transistor N The drain of MOS transistor N ₂₃ is connected to the source of MOS transistor N ₂₅ , the gate of MOS transistor N ₂₅ is connected to the drain of MOS transistor N ₈ , the gate of MOS transistor N ₂₆ is connected to the drain of MOS transistor N 26, and the gate of MOS transistor N ₂₆ is connected. ₁ gate and the gate of MOS transistor _N2 , the gate of MOS transistor _N3 , the gate of MOS transistor _N4 , the gate of MOS transistor _N5 , the gate of MOS transistor _N6 , the gate of MOS transistor _N6 The drain, the gate of MOS transistor _N7 are connected to the gate of MOS transistor _N8 and receive a given reference current signal I _ref , the source of MOS transistor _N1 is connected to the source of MOS transistor _N2 , and the source of MOS transistor _N3 source of MOS transistor _N4 , source of MOS transistor _N5 , source of MOS transistor _N6 , source of MOS transistor _N7 , source of MOS transistor _N8 , source of MOS transistor _N11 electrode, the collector of the triode _T1 and the collector of the triode _T2 are connected and grounded; among them, the MOS transistors _N1 ~ _N12 are all NMOS transistors, the MOS transistors _N13 ~ _N27 are all PMOS transistors, and the triodes _T1 ~T ₂ are PNP transistors, and transistors T ₃ ~ T ₄ are NPN transistors.

In the reference current generating circuit, according to the connection relationship of the transistors, V _BE3 +V _BE2 +I ₂ R ₁ =V _BE4 +V _BE1 , M ₁ and M ₂ form a current mirror with the same width-to-length ratio, so V _BE4 =V _BE1 , V _BE3 =V _BE2 , it can be concluded that the expression of I ₂ is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; S</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; m</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}$

The generated reference current I _PTAT is a copy of I ₂ , and the copy ratio is 1:n (in this embodiment, n=4), and the specific expression is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; no</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; m</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}$

Among them: V _BE1 , V _BE2 , V _BE3 , V _BE4 are the base-emitter voltages of Q ₁ ~Q ₄ respectively, V _T is the thermal voltage (V _T =26mV at room temperature); I _S3 , I _S4 are Q ₃ and the reverse saturation current of Q ₄ , the ratio of the two is the emitter area ratio m of Q ₃ and Q ₄ (in this embodiment, m=8).

In the current-voltage conversion circuit, the reference current I _PTAT acts on R ₂ to generate a reference voltage V _P that is input to the non-inverting input terminal of the operational amplifier, and the voltage V _SENSE on the sampling resistor R is converted into a detection voltage V _N that is input to the operational amplifier. Inverting input. In order to reduce the bias voltage of the operational amplifier and realize the accurate amplification of the difference between the voltage signal V _P and V _N , the input stage of the operational amplifier uses a triode as the input tube, and the base current I _B+ and the input transistor of the operational amplifier need to be considered during voltage conversion. I _B- ; so the expressions of the voltage signals V _P and V _N are as follows:

V _P =I _PTAT R ₂ +I _B + R ₂

V _N =V _SENSE +I _B- R ₃

The operational amplifier amplifies the voltage signals V _P and V _N. When the load current I ₀ is relatively small and is lower than the current limit point, V _SENSE is very small. At this time, V _N <V _P and the difference is large, and the operational amplifier is the first The stage output voltage OUT1 is very small, so N ₂₇ is turned off. At this time, the switch control signal GATE output by the op amp is at a high level, which controls the power tube M to be turned on, and the load current I ₀ normally passes through M; when the load current I ₀ gradually increases When the voltage V _SENSE (V _N ) is large, the voltage V SENSE (V N ) also gradually increases. When the current I ₀ increases to a certain threshold, the output voltage OUT1 of the first stage of the operational amplifier increases to turn on N ₂₇ , and the pull-down effect of N ₁₂ makes the switch control The signal GATE decreases gradually, the conduction degree of the power transistor M decreases, and the load current _I0 is controlled to decrease and not allow it to continue to increase, so as to realize the current limit, and the above threshold is the current limit point.

The negative feedback loop composed of the current-voltage conversion circuit, the operational amplifier and the power tube clamps the voltage V _P and V _N of the two input terminals of the operational amplifier to be approximately equal. Therefore, the above-mentioned clamping accuracy can be improved, and the current limiting point current I _CL can be obtained to satisfy the following expression:

V _P =I _PTAT R ₂ +I _B+ R ₂ =V _N =I _CL R+I _B- R ₃

Wherein, the resistors R ₂ and R ₃ are implemented with exactly the same resistor, so R ₂ =R ₃ . Moreover, when the circuit works in the current-limiting state, the currents I ₁₁ and I ₁₀ flowing through the MOS transistors N ₂₇ and N ₁₀ are approximately the same, which are the currents obtained by copying the current mirror composed of N ₃ , N ₄ , and N ₆ , while N The currents I ₂ and I ₃ flowing through ₁₇ and N ₁₈ are equal, and then the emitter currents I _c1 and I _c2 of the triodes T ₁ and T ₂ are approximately equal, and the triodes T ₁ and T ₂ are identical triodes, which can be It is considered that I _B+ =I _B- within the required accuracy range; so the above formula can be simplified as: I _PTAT ·R ₂ =I _CL ·R.

Furthermore, the expression of the current limit current I _CL can be obtained as follows:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; CL</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}$

Since the operational amplifier uses a triode as the input tube, the bias voltage can be very small, and the two-stage cascode amplifier stage makes the loop gain very large, plus the branch composed of N ₂₇ and N ₃ and the branch composed of N ₁₀ and N ₄ When the circuit works in the current-limiting state, the same current can largely eliminate the difference between the base currents I _B+ and I _B- of the input transistors T ₁ and T ₂ , so the voltages V _P and V _N at the two input terminals of the op amp The closeness is very high, and the op amp can accurately amplify their difference. At the same time, the reference voltage V _P is realized by applying the PTAT current to the resistor, which can compensate the positive temperature coefficient of the metal sampling resistor R to a certain extent. It can be seen from the above formula that when the temperature changes, by adjusting the emitter area ratio m of the triode Q ₂ /Q ₃ and Q ₁ /Q ₄ in the reference current generating circuit, the width-to-length ratio of M3 and the width of M ₁ /M ₂ The ratio n of the length ratio and the ratio of the resistor R ₁ to the resistor R ₂ in the current-voltage conversion circuit can make the generated reference voltage V _P follow the detection voltage of the metal sampling resistor R, and obtain a high-precision current limiting point.

In this embodiment, the current at the current limit point is set to 450mA according to the requirements of the application standard IEEE802.3af, and the resistance value of the sampling resistor R is 0.08Ω, so the corresponding reference voltage V _P =36mV.

The current limiting level of this embodiment is between 441.7mA and 462.9mA, and the typical value is 450.3mA, so the present invention can realize high-precision current limiting.

Claims (7)

1. A current limiting circuit of a DC/DC converter, characterized in that, comprising: The power switch tube is used to control the load current of the DC/DC converter; the input end of the power switch tube is connected to the DC/DC converter, the output end is connected to a sampling resistor, and the other end of the sampling resistor is grounded ; A reference current generating circuit, configured to generate a reference current signal; A current-voltage conversion circuit, configured to convert the reference current signal into a reference voltage signal, collect the voltage of the sampling resistor at the same time, and convert the voltage into a detection voltage signal; An operational amplifier circuit, configured to amplify the difference between the reference voltage signal and the detection voltage signal, and output a switch control signal to control the power switch tube; The operational amplifier circuit is composed of twenty-seven MOS transistors and four triodes; wherein, the drain of MOS transistor _N9 is connected to the source of MOS transistor _N13 , the source of MOS transistor _N14 , and the source of MOS transistor _N15 . The source, the source of the MOS transistor _N19 , the source of the MOS transistor _N20 , the source of the MOS transistor _N23 and the source of the MOS transistor _N24 are connected and connected to the power supply voltage, the gate of the MOS transistor _N13 is connected to the MOS transistor The drain of _N13 , the source of MOS transistor _N16 , the gate of MOS transistor _N14 are connected to the gate of MOS transistor N15, the drain of MOS transistor _N14 is connected to the source of MOS transistor _N17 , and the gate of MOS transistor _N17 is connected. The drain of _N15 is connected to the source of MOS transistor _N18 , the gate of MOS transistor _N16 is connected to the drain of MOS transistor _N16 , the drain of MOS transistor _N1 , the gate of MOS transistor _N17 and the gate of MOS transistor N ₁₈ , the drain of MOS transistor _N17 is connected to the gate of MOS transistor _{N9 , the collector of transistor T3 is connected to the drain of MOS transistor N10, and the drain of MOS transistor N18 is connected} to the drain of transistor _T4 The collector is connected to the source of the MOS transistor _N27 , the base of the triode _T3 is connected to the base of the triode _T4 , the source of the MOS transistor _N9 is connected to the drain of the MOS transistor _N2 , and the emitter of the triode _T3 is connected to the drain of the MOS transistor N2. The emitter of the transistor _T1 is connected, the emitter of the transistor _T4 is connected with the emitter of the transistor _T2 , the base of the transistor _T1 and the base of the transistor _T2 are respectively the non-inverting input terminal and the inverting input of the operational amplifier circuit terminal, the gate of MOS transistor _N27 is connected to the drain of MOS transistor _N27 , the drain of MOS transistor _N3 is connected to the gate of MOS transistor _N12 , the source of MOS transistor _N10 is connected to the drain of MOS transistor _N4 The gate of MOS transistor _N10 is connected to the gate of MOS transistor _N11 , the drain of MOS transistor _N11 is connected to the drain of MOS transistor _N21 , the source of MOS transistor _N12 is connected to the drain of MOS transistor _N7 The drain of the MOS transistor _N12 is connected to the drain of the MOS transistor _N25 and is the output terminal of the operational amplifier circuit, the gate of the MOS transistor _N19 is connected to the source of the MOS transistor _N22 , and the gate of the MOS transistor _N20 It is connected to the drain of MOS transistor _N20 , the drain of MOS transistor _N19 is connected to the source of MOS transistor _N21 , the gate of MOS transistor _N21 is connected to the drain of MOS transistor _N5 , and the gate of MOS transistor _N22 It is connected to the drain of MOS transistor _N22 , the gate of MOS transistor _N23 is connected to the source of MOS transistor _N26 , the gate of MOS transistor _N24 is connected to the drain of MOS transistor _N24 , and the drain of MOS transistor _N23 It is connected to the source of MOS transistor _N25 , the gate of MOS transistor _N25 is connected to the drain of MOS transistor _N8 , the gate of MOS transistor _N26 is connected to the drain of MOS transistor _N26 , and the gate of MOS transistor _N1 and the gate of MOS transistor _N2 , the gate of MOS transistor _N3 , and the gate of MOS transistor The gate of _N4 , the gate of MOS transistor _N5 , the gate of MOS transistor _N6 , the drain of MOS transistor _N6 , the gate of MOS transistor _N7 and the gate of MOS transistor _N8 are connected and receive the given The reference current signal of MOS transistor _N1 , the source of MOS transistor _N2 , the source of MOS transistor _N3 , the source of MOS transistor _N4 , the source of MOS transistor _N5 , the source of MOS transistor _N6 The source, the source of MOS transistor _N7 , the source of MOS transistor _N8 , the source of MOS transistor _N11 , the collector of transistor _T1 and the collector of transistor _T2 are connected and grounded. 2. The current limiting circuit of the DC/DC converter according to claim 1, wherein the reference current generating circuit is composed of three MOS transistors, four triodes and a resistor; wherein, the MOS transistor M ₁ The source of the MOS transistor _M2 is connected to the source of the MOS transistor _M3 and connected to the power supply voltage, the gate of the MOS transistor _M1 is connected to the drain of the MOS transistor _M2 , the gate of the MOS transistor _M2 , the MOS The gate of the transistor _M3 is connected to the collector of the transistor _Q4 , the drain of the MOS transistor _M3 is the output end of the reference current generating circuit, the drain of the MOS transistor _M1 is connected to the collector of the transistor _Q3 , and the base of the transistor _Q3 The pole is connected with the base of transistor _Q4 , the emitter of transistor _Q3 is connected with the collector of transistor _Q1 and the base of transistor _Q2 , the emitter of transistor _Q4 is connected with the collector of transistor _Q2 and the base of transistor _Q1 The bases are connected, the emitter of the transistor _Q2 is connected to one end of the resistor _R1 , the emitter of the transistor _Q1 is connected to the other end of the resistor _R1 and grounded. 3. The current limiting circuit of the DC/DC converter according to claim 1, characterized in that: the current-voltage conversion circuit is composed of two resistors; wherein, one end of the resistor R ₂ is connected to the reference current generation circuit and the operation The non-inverting input of the amplifier circuit is connected, the other end of the resistor _R2 is grounded, one end of the resistor _R3 is connected to the sampling resistor, and the other end of the resistor _R3 is connected to the inverting input of the operational amplifier circuit. 4. The current limiting circuit of the DC/DC converter according to claim 3, characterized in that: said resistor _R2 and resistor _R3 have the same resistance value. 5. The current limiting circuit of the DC/DC converter according to claim 2, characterized in that: the ratio of the emitter area of the transistor _Q2 to the transistor _Q1 is equal to the emitter area of the transistor _Q3 to the transistor _Q4 The ratio is m, and m is a natural number greater than 1. 6. The current limiting circuit of the DC/DC converter according to claim 1, wherein the resistance value of the sampling resistor is 0.08Ω. 7. The current limiting circuit of the DC/DC converter according to claim 2, characterized in that: the width-to-length ratio of the MOS transistor _M1 and the MOS transistor _M2 is the same, and the width-to-length ratio of the MOS transistor _M3 is n times the width-to-length ratio of the MOS transistor _M1 , where n is a natural number greater than 1.

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