CN102868866B - Cmos image sensor row share 2 × 2 pixel cells and pel array - Google Patents
Cmos image sensor row share 2 × 2 pixel cells and pel array Download PDFInfo
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- CN102868866B CN102868866B CN201210359828.7A CN201210359828A CN102868866B CN 102868866 B CN102868866 B CN 102868866B CN 201210359828 A CN201210359828 A CN 201210359828A CN 102868866 B CN102868866 B CN 102868866B
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- 239000002184 metal Substances 0.000 claims abstract description 82
- 201000007094 prostatitis Diseases 0.000 claims abstract description 10
- 230000035945 sensitivity Effects 0.000 abstract description 7
- 230000003287 optical effect Effects 0.000 abstract description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000003491 array Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 2
- 101000695172 Agalychnis dacnicolor Plasticin-DA1 Proteins 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
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Abstract
The invention discloses a kind of cmos image sensor row and share 2 × 2 pixel cells and pel array, be arranged in 2 × 2 pel arrays as one group of pixel cell by 4 pixels; Two, prostatitis pixel and rank rear two pixels of often organizing pixel cell share selection transistor respectively in row, transistor, reset transistor and floating active area are followed in source; In cmos image sensor two-dimensional array, metal connecting line uses double layer of metal line to connect, the 0th layer of metal wire and the 1st layer of metal wire is only used to realize gathering image information function as the control line of device, do not use the 2nd layer or more high-rise metal wire as device control line, the medium level on photodiode Si surface can be reduced, more light is made to incide photodiode, use optical efficiency and the conversion gain of small size element sensor can be improved, thus raising sensitivity, effectively can improve the image quality of small size pixel image sensor.
Description
Technical field
The present invention relates to a kind of cmos image sensor, particularly relate to a kind of cmos image sensor row and share 2 × 2 pixel cells and pel array.
Background technology
Imageing sensor has been widely used in digital camera, cell phone, medicine equipment, automobile and other application scenarios.Particularly CMOS(CMOS (Complementary Metal Oxide Semiconductor)) fast development of imageing sensor, make people have higher requirement to low-power consumption small size high-resolution image sensors.
The arrangement mode that cmos image sensor row of the prior art share 2 × 2 pixel cell structures is shared for 4T2S(tetra-transistor two pixels), owing to depending on the architectural feature of pixel itself, its pel array generally needs the 1st layer of metal, 2nd layer of metal and the 3rd layer of metal, as device interconnection line, need multirow or multiple row the 1st layer of metal, the 2nd layer of metal or the 3rd layer of metal connecting line respectively between adjacent lines pixel or between adjacent column pixel; And it is larger that the metal capacitance parasitism that transistor gate is connected is followed in floating active area and source.
Above-mentioned prior art at least comprises following shortcoming:
Because the photosensitive area of small size element sensor is little, sensitivity is low, makes the information under transmission half-light clear not.Especially at use the 1st layer of metal, when the 2nd layer of metal and the 3rd layer of metal are as device interconnection line, photodiode Si(silicon) medium level on surface is higher, and metal wire blocks some light and incides in photodiode; Further, metal wire that transistor gate is connected is followed close to power Metal line in floating active area and source, and floating active area capacitive parasitic is large, causes signal electron to convert the amplitude (conversion gain) of signal voltage to little.
Summary of the invention
The object of this invention is to provide a kind of highly sensitive small size cmos image sensor row and share 2 × 2 pixel cells and pel array.
The object of the invention is to be achieved through the following technical solutions:
Cmos image sensor row of the present invention share 2 × 2 pixel cells, single pixel comprises photodiode, transistor, reset transistor, floating active area and metal connecting line are followed in charge pass transistor, selection transistor, source, is arranged in 2X2 pel array as one group of pixel cell by 4 pixels;
Two, prostatitis pixel and rank rear two pixels of often organizing pixel cell share selection transistor respectively in row, transistor, reset transistor and floating active area are followed in source;
The top that transistor is positioned at pixel cell is followed in the selection transistor that two, described prostatitis pixel is shared and source, and the bottom that transistor is positioned at pixel cell is followed in the selection transistor that described rank rear two pixels are shared and source.
Cmos image sensor pel array of the present invention, comprise the cmos image sensor row of many groups described in claim 1 or 2 and share 2 × 2 pixel cells, many groups pixel cell is arranged as two-dimensional array in the vertical and horizontal direction, in described two-dimensional array, metal connecting line uses double layer of metal line to connect, and comprises the 0th layer of metal wire and the 1st layer of metal wire.
From the technical scheme of the invention described above, cmos image sensor row of the present invention share 2 × 2 pixel cells and pel array, owing to being arranged in 2X2 pel array as one group of pixel cell by 4 pixels; Two, prostatitis pixel and rank rear two pixels of often organizing pixel cell share selection transistor respectively in row, transistor, reset transistor and floating active area are followed in source; In cmos image sensor two-dimensional array, metal connecting line uses double layer of metal line to connect, the 0th layer of metal wire and the 1st layer of metal wire is only used to realize gathering image information function as the control line of device, do not use the 2nd layer or more high-rise metal wire as device control line, the medium level on photodiode Si surface can be reduced, more light is made to incide photodiode, use optical efficiency and the conversion gain of small size element sensor can be improved, thus raising sensitivity, effectively can improve the image quality of small size pixel image sensor.
Accompanying drawing explanation
Fig. 1 is the 4T2S structural circuit schematic diagram that cmos image sensor of the present invention row share four pixel compositions in the specific embodiment one of 2 × 2 pixel cells;
Fig. 2 is the 4T2S structure domain schematic diagram that cmos image sensor of the present invention row share four pixel compositions in the specific embodiment one of 2 × 2 pixel cells;
Fig. 3 is 6x 4 pixel array circuit schematic diagram in the specific embodiment one of cmos image sensor array of the present invention;
Fig. 4 is 6x 4 pel array domain schematic diagram in the specific embodiment one of cmos image sensor array of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on embodiments of the invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to protection scope of the present invention.
The embodiment of the present invention uses the 0th layer of metal wire and the 1st layer of metal wire to be not realize the unique execution mode of the present invention, the 1st layer of metal wire and the 2nd layer of metal wire or other layer of metal wire also can be used to realize present invention pixel structural advantage in describing.
Cmos image sensor of the present invention row share 2 × 2 pixel cells, and preferably embodiment is as shown in Figure 1 and Figure 2 for it:
Single pixel comprises photodiode, transistor, reset transistor, floating active area and metal connecting line are followed in charge pass transistor, selection transistor, source, it is characterized in that:
2X2 pel array is arranged in as one group of pixel cell by 4 pixels;
Two, prostatitis pixel and rank rear two pixels of often organizing pixel cell share selection transistor respectively in row, transistor, reset transistor and floating active area are followed in source;
The top that transistor is positioned at pixel cell is followed in the selection transistor that two, described prostatitis pixel is shared and source, and the bottom that transistor is positioned at pixel cell is followed in the selection transistor that described rank rear two pixels are shared and source.
Described floating active area and source are followed transistor gate and are connected with the 1st layer of metal connecting line in a column direction, this metal connecting line and power Metal line non-conterminous.
Cmos image sensor pel array of the present invention, preferably embodiment is as shown in Figure 3, Figure 4 for it:
The cmos image sensor row comprising many groups above-mentioned share 2 × 2 pixel cells, many groups pixel cell is arranged as two-dimensional array in the vertical and horizontal direction, in described two-dimensional array, metal connecting line uses double layer of metal line to connect, and comprises the 0th layer of metal wire and the 1st layer of metal wire.
In described two-dimensional array, the power line in a column direction between same column pixel and column output line use the 1st layer of metal connecting line;
In described two-dimensional array, the transistor device control line of going together between pixel uses the 0th layer of metal connecting line in the row direction.
The present invention solves the low problem of conventional images transducer small size pixel sensitivity, the 0th layer of metal wire and the 1st layer of metal wire is only used to realize gathering image information function as the control line of device, do not use the 2nd layer or more high-rise metal wire as device control line, the medium level on photodiode Si surface can be reduced, make more light incide photodiode.The metal wire of transistor gate is followed away from power Metal line in connection source, floating active area, can reduce the parasitic capacitance of floating active area, thus improves the amplitude that signal electron is converted to signal voltage.Therefore, cmos image sensor row of the present invention share use optical efficiency and the conversion gain that 2 × 2 pixel cell structures can improve small size element sensor, thus improve sensitivity, so effectively can improve the image quality of small size pixel image sensor.
Embodiment one:
Circuit diagram as shown in Figure 1, cmos image sensor row are shared 2 × 2 pixel cells and are adopted 4T2S structure, comprise four pixels, pixel 11, pixel 12, pixel 21 and pixel 22.PD11, PD12, PD21 and PD22 are the photodiode of pixel 11, pixel 12, pixel 21 and pixel 22 respectively; TX11, TX12, TX21 and TX22 are the charge pass transistor of pixel 11, pixel 12, pixel 21 and pixel 22 respectively; RX1 and RX2 is reset transistor, SF1 and SF2 is that transistor is followed in source, SX1 and SX2 is for selecting transistor; Pixel 11 and pixel 21 share reset transistor RX1, transistor SF1 is followed in source, select transistor SX1, and pixel 12 and pixel 22 share reset transistor RX2, transistor SF2 is followed in source, select transistor SX2; SX1 and SF1 is positioned at the top of prostatitis pixel 11 and pixel 21, SX2 and SF2 is positioned at the bottom of rank rear pixel 12 and pixel 22.FD1 is the floating active area that pixel 11 and pixel 21 are shared, and FD2 is the floating active area that pixel 12 and pixel 22 are shared; SN1 and SN2 is column signal output line, and VC is power line.
Transistor controls line SV1 connects the grid selecting transistor SX1, control line TV1 connects the grid of charge pass transistor TX11 and TX12, control line RV connects the grid of reset transistor transistor RX1 and RX2, control line TV2 connects the grid of charge pass transistor TX21 and TX22, and control line SV2 connects the grid selecting transistor SX2; SN1 with SN2 is connected the source electrode that transistor is followed in source respectively, and VC connects the drain electrode of RX1, RX2, SX1 and SX2; The grid that transistor SF1 is followed in floating active area FD1 and source is connected, and the grid that transistor SF2 is followed in floating active area FD2 and source is connected.
Figure 2 shows that the domain schematic diagram that circuit diagram shown in Fig. 1 is corresponding.As shown in Figure 2, transistor device control line SV1, TV1, RV, TV2 and SV2 use the 0th layer of metal wire, and power control line VC and column signal output line SN1, SN2 use the 1st layer of metal wire; 0th layer of metal control wires SV1, TV1, RV, TV2 and SV2 are contacted with each other by contact hole 0 with the grid polycrystalline silicon of respective transistor respectively, and the 1st layer of metal control wires SN1, SN2 and VC to be contacted with each other by contact hole 1 with the source electrode of respective transistor and draining respectively; Use the 1st layer of metal wire to be contacted with each other by contact hole 1 between the grid polycrystalline silicon of floating active area FD1 and SF1, between the grid polycrystalline silicon of floating active area FD2 and SF2, use the 1st layer of metal wire to be contacted with each other by contact hole 1.Preferably, also can save in the present embodiment and select transistor SX1 and SX2, lack in embodiment and select transistor to affect normal operation of sensor, also can not affect the technical problem that the present invention solves.
Four pixels recited above are designated as one group of pixel cell, be arranged as two-dimensional array in the vertical and horizontal direction more, and illustrate for 6x4 pel array in the present embodiment by organizing pixel cell.High sensitivity small size cmos image sensor row of the present invention share 2 × 2 pixel cell structures and two-dimensional array structure includes but are not limited to: 6x4 pel array, and can adapt to other sizes pel arrays.
As shown in Figure 3, be 6X 4 pixel array circuit schematic diagram; Domain schematic diagram corresponding to the schematic diagram of pixel array circuit shown in Fig. 3 as shown in Figure 4.
In pel array shown in Fig. 3 and Fig. 4, PD11 ~ PD16 is the photodiode of the 1st row pixel, PD21 ~ PD26 is the photodiode of the 2nd row pixel, and PD31 ~ PD36 is the photodiode of the 3rd row pixel, and PD41 ~ PD46 is the photodiode of the 4th row pixel; Pixel device control line TV1 is connected with the grid polycrystalline silicon of the charge pass transistor TX11 ~ TX16 of the 1st row pixel, pixel device control line TV2 is connected with the grid polycrystalline silicon of the charge pass transistor TX21 ~ TX26 of the 2nd row pixel, pixel device control line TV3 is connected with the grid polycrystalline silicon of the charge pass transistor TX31 ~ TX36 of the 3rd row pixel, and pixel device control line TV4 is connected with the grid polycrystalline silicon of the charge pass transistor TX41 ~ TX46 of the 4th row pixel; Pixel device control line SV1 is connected with selecting the grid polycrystalline silicon of transistor SX11, SX13, SX15, pixel device control line SV3 is connected with selecting the grid polycrystalline silicon of transistor SX31, SX22, SX33, SX24, SX35, SX26, and pixel device control line SV5 is connected with selecting the grid polycrystalline silicon of transistor SX42, SX44, SX46; Pixel device control line RV1 is connected with the grid polycrystalline silicon of reset transistor RX11, RX22, RX13, RX24, RX15, RX26, and pixel device control line RV3 is connected with the grid polycrystalline silicon of reset transistor RX31, RX42, RX33, RX44, RX35, RX46.The source electrode that transistor SF11 with SF31 is followed in column signal output line SN1 in pel array and the source of the 1st row pixel is connected, the source electrode that column signal output line SN2 follows transistor SF22 with SF42 with the source of the 2nd row pixel is connected, the source electrode that column signal output line SN3 follows transistor SF13 with SF33 with the source of the 3rd row pixel is connected, the source electrode that column signal output line SN4 follows transistor SF24 with SF44 with the source of the 4th row pixel is connected, the source electrode that column signal output line SN5 follows transistor SF15 with SF35 with the source of the 5th row pixel is connected, the source electrode that column signal output line SN6 follows transistor SF26 with SF46 with the source of the 6th row pixel is connected, power control line VC is connected with the reset transistor drain electrode end respectively organizing pixel cell in pel array, is connected with the selection transistor drain end respectively organizing pixel cell in pel array, each group of pixel cell FD district in pel array follows transistor respectively grid with respective sources is connected.
In above-mentioned pel array, colleague's pixel device control line TV1 ~ TV4, SV1, SV3, SV5, RV1, RV3 use the 0th layer of metal wire; Same column pixel output line SN1 ~ SN6 uses the 1st layer of metal wire, and power line VC uses the 1st layer of metal wire, and the gate connection line that the FD of each group pixel cell and respective sources follow transistor uses the 1st layer of metal wire.It should be noted that, use the 0th layer of metal wire and the 1st layer of metal wire to be not realize the unique execution mode of the present invention, the 1st layer of metal wire and the 2nd layer of metal wire or other layer of metal wire also can be used to realize present invention pixel structural advantage.Use n-th layer and N+1 layer metal wire can determine according to concrete Pixel Design situation, all can realize the minimizing metal wire use number of plies that the present invention proposes, reduce medium level, the effect of raising optical efficiency.Because its core design method of dot structure and above-described embodiment of changing metal wire level duplicate, do not repeat at this.
Cmos image sensor row of the present invention are shared in 2 × 2 pixel cells and pel array, owing to have employed using 2X2 picture element array structure as one group of unit, the selection transistor that often in group unit, two, prostatitis pixel is shared and source are followed transistor and are positioned at top, the selection transistor that rank rear two pixels are shared and source are followed transistor and are positioned at bottom, and improve the connected mode of transistor and floating node in dot structure, metal connecting line only uses the 0th layer of metal wire and the 1st layer of metal wire to realize gathering image information function as the control line of device, there is no use the 2nd layer or more high-rise metal wire as device control line, effectively reduce the medium level on photodiode Si surface, more light is made to incide photodiode, raising optical efficiency.In addition, the metal wire of transistor gate is followed away from power Metal line in the connection source, floating active area of shared 2 × 2 pixel cells of cmos image sensor row of the present embodiment, reduce the parasitic capacitance of floating active area, thus improve the amplitude that signal electron is converted to signal voltage.
Therefore, cmos image sensor row of the present invention share use optical efficiency and the conversion gain that 2 × 2 pixel cell structures can improve small size element sensor, thus improve sensitivity, so effectively can improve the image quality of small size pixel image sensor.
The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (2)
1. a cmos image sensor pel array, is characterized in that, comprise many group cmos image sensor row and share 2 × 2 pixel cells, many group pixel cells are arranged as two-dimensional array in the vertical and horizontal direction;
Described cmos image sensor row are shared in 2 × 2 pixel cells, single pixel comprises photodiode, transistor, reset transistor, floating active area and metal connecting line are followed in charge pass transistor, selection transistor, source, is arranged in 2X2 pel array as one group of pixel cell by 4 pixels;
Two, prostatitis pixel and rank rear two pixels of often organizing pixel cell share selection transistor respectively in row, transistor, reset transistor and floating active area are followed in source;
The top that transistor is positioned at pixel cell is followed in the selection transistor that two, described prostatitis pixel is shared and source, and the bottom that transistor is positioned at pixel cell is followed in the selection transistor that described rank rear two pixels are shared and source;
In described two-dimensional array, metal connecting line uses double layer of metal line to connect, comprise the 0th layer of metal wire and the 1st layer of metal wire, power line in a column direction between same column pixel and column output line use the 1st layer of metal connecting line, and the transistor device control line of going together between pixel uses the 0th layer of metal connecting line in the row direction.
2. cmos image sensor pel array according to claim 1, is characterized in that, described floating active area and source are followed transistor gate and be connected with the 1st layer of metal connecting line in a column direction, this metal connecting line and power Metal line non-conterminous.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210359828.7A CN102868866B (en) | 2012-09-24 | 2012-09-24 | Cmos image sensor row share 2 × 2 pixel cells and pel array |
| JP2015532274A JP2015530749A (en) | 2012-09-24 | 2012-12-14 | CMOS image sensor column sharing 2 × 2 pixel unit and pixel array |
| KR1020157004569A KR20150060675A (en) | 2012-09-24 | 2012-12-14 | COLUMN SHARING 2x2 PIXEL UNIT AND PIXEL ARRAY OF CMOS IMAGE SENSOR |
| PCT/CN2012/086688 WO2014044004A1 (en) | 2012-09-24 | 2012-12-14 | Column sharing 2×2 pixel unit and pixel array of cmos image sensor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210359828.7A CN102868866B (en) | 2012-09-24 | 2012-09-24 | Cmos image sensor row share 2 × 2 pixel cells and pel array |
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| Publication Number | Publication Date |
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| CN102868866A CN102868866A (en) | 2013-01-09 |
| CN102868866B true CN102868866B (en) | 2015-09-16 |
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| Country | Link |
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| JP (1) | JP2015530749A (en) |
| KR (1) | KR20150060675A (en) |
| CN (1) | CN102868866B (en) |
| WO (1) | WO2014044004A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103165636B (en) * | 2013-03-21 | 2015-10-21 | 北京思比科微电子技术股份有限公司 | The pixel cell group of cmos image sensor and cmos image sensor |
| CN103137642B (en) * | 2013-03-21 | 2015-11-18 | 北京思比科微电子技术股份有限公司 | The pixel cell of cmos image sensor and cmos image sensor |
| CN103391408B (en) * | 2013-07-31 | 2017-02-15 | 北京思比科微电子技术股份有限公司 | Pixel structure of CMOS (complementary metal-oxide-semiconductor transistor) image sensor and image sensor |
| CN106098718A (en) * | 2016-08-08 | 2016-11-09 | 北京思比科微电子技术股份有限公司 | A kind of image sensor pixel structure of transporting holes |
| CN110661990B (en) * | 2018-06-29 | 2022-07-15 | 格科微电子（上海）有限公司 | Design method of pixel output signal blocking capacitor |
| CN112563293A (en) * | 2019-09-10 | 2021-03-26 | 格科微电子（上海）有限公司 | Pixel structure of CMOS image sensor |
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| CN1490878A (en) * | 2002-09-02 | 2004-04-21 | ��ʿͨ��ʽ���� | Solid-state image sensor and image reading method |
| CN1835245A (en) * | 2005-03-17 | 2006-09-20 | 富士通株式会社 | Image sensor with embedded photodiode region and fabrication method thereof |
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| CN102158663A (en) * | 2011-04-15 | 2011-08-17 | 北京思比科微电子技术股份有限公司 | CMOS (Complementary Metal Oxide Semiconductor) image sensor pixel and control time sequence thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2006025079A1 (en) * | 2004-07-20 | 2006-03-09 | Fujitsu Limited | Cmos imaging element |
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- 2012-09-24 CN CN201210359828.7A patent/CN102868866B/en not_active Expired - Fee Related
- 2012-12-14 WO PCT/CN2012/086688 patent/WO2014044004A1/en not_active Ceased
- 2012-12-14 KR KR1020157004569A patent/KR20150060675A/en not_active Ceased
- 2012-12-14 JP JP2015532274A patent/JP2015530749A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490878A (en) * | 2002-09-02 | 2004-04-21 | ��ʿͨ��ʽ���� | Solid-state image sensor and image reading method |
| CN1835245A (en) * | 2005-03-17 | 2006-09-20 | 富士通株式会社 | Image sensor with embedded photodiode region and fabrication method thereof |
| CN101742131A (en) * | 2008-11-25 | 2010-06-16 | 上海华虹Nec电子有限公司 | Photoelectric converter of Complementary Metal-Oxide-Semiconductor (CMOS) image sensor |
| CN102158663A (en) * | 2011-04-15 | 2011-08-17 | 北京思比科微电子技术股份有限公司 | CMOS (Complementary Metal Oxide Semiconductor) image sensor pixel and control time sequence thereof |
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| JP2015530749A (en) | 2015-10-15 |
| CN102868866A (en) | 2013-01-09 |
| KR20150060675A (en) | 2015-06-03 |
| WO2014044004A1 (en) | 2014-03-27 |
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