CN103078618A - voltage switch circuit - Google Patents

Abstract

A voltage switch circuit is provided, in which a low Doped (Lightly Doped) PMOS transistor is used to bear high voltage stress, so that an NMOS transistor can not bear high voltage stress.

Description

voltage switch circuit

technical field

The present invention relates to a voltage switch circuit, and more particularly to a voltage switch circuit utilizing PMOS transistors to withstand high voltage stress.

Background technique

Please refer to FIG. 1 , which is a schematic diagram of a decoding circuit module in a known memory. The decoding circuit module includes an HV decode switch system (HV decode switch system) 110 and a low voltage decode switch system (LV decode switch system) 150.

The high voltage decoding switching system 110 includes a voltage switching circuit 120 , a first voltage switching circuit group 130 , and a decoding unit 140 . The voltage switch circuit 120 selectively outputs the first voltage (HV) or the second voltage (MV) as the input voltage (VPP) of the decoding unit 140 according to the control signal (EN).

Furthermore, the first voltage switch circuit group 130 includes N voltage switch circuits, the circuit structure of which is the same as that of the above voltage switch circuit 120 . The first voltage switch circuit group 130 is controlled by an N-bit address signal A<N-1:0>, and generates an N-bit high-voltage decoding signal HVDEC<N-bit according to the N-bit address signal A<N-1:0> N-1:0> and input to the decoding unit 140 .

For example, assuming that the address signal A[N-1] of the N-1th bit is low level (L), the high-voltage decoding signal HVDEC[N-1] of the N-1th bit is the first voltage ( HV); On the contrary, assuming that the address signal A[N-1] of the N-1th bit is high level (H), the high-voltage decoding signal HVDEC[N-1] of the N-1th bit is the second voltage (MV). Similarly, the operating principles of the other voltage switches in the first voltage switch circuit group 130 are the same, and will not be repeated here.

After the decoding unit 140 receives the input voltage (VPP) and the N-bit high-voltage decoding signal HVDEC<N-1:0>, it will generate different states on the 2 ^N array bus signal lines Array_bus<2 ^N -1:0> , that is, the open state (ON) or the closed state (OFF). Basically, the operation principle of the decoding unit 140 is not the focus of the present invention, so its internal circuit and operation principle will be omitted.

Furthermore, the low-voltage decoding switching system 150 includes a second voltage switching circuit group 160 . The second voltage switch circuit group 160 includes 2 ^N voltage switch circuits, the output terminals of which are respectively connected to 2 ^N array bus signal lines Array_bus<2 ^N −1:0>. And the second voltage switch circuit group 160 is controlled by the N-bit address signal A<N−1:0> and the read signal Read. Its operating principle is introduced as follows:

Taking the (2 ^N -1)th array bus signal line Array_bus[2 ^N -1] as an example, when the decoding unit 140 controls the (2 ^N -1)th array bus signal line Array_bus[2 ^N -1] to be in the on state (ON), the voltage on the (2 ^N -1)th array bus signal line Array_bus[2 ^N -1] is the input voltage (VPP), and at this moment the second voltage switch circuit group 160 will provide a floating state ( floating) to the (2 ^N -1)th array bus signal line Array_bus[2 ^N -1]. Furthermore, when the decoding unit 140 controls the (2 ^N -1)th array bus signal line Array_bus[2 ^N -1] to be in the OFF state (OFF), the (2 ^N -1)th array bus signal line Array_bus[2 The voltage on ^N -1] will be provided by the second voltage switch circuit group 160, which may be in the (2 ^N -1)th array according to the address signal A<N-1:0> and the read signal (read). 0V or read voltage (VR) is provided on the bus signal line Array_bus[2 ^N −1]. Similarly, the operation principles of other array bus signal lines are the same, and will not be repeated here.

In the process field of logic circuits, a voltage that is 2 to 3 times higher than the logic potential can be regarded as a high voltage. For example, if the logic level is 2.5V, the voltage higher than 7V can be regarded as high voltage; when the logic level is 3.3V, the voltage higher than 9V can be regarded as high voltage; the logic level When it is 5V, the voltage higher than 18V can be regarded as high voltage.

Taking the decoding circuit module in the memory in FIG. 1 as an example, its logic level is 5V, the first voltage (HV) is 18V, and the second voltage (MV) is 10V. That is to say, in the high voltage decoding switching system 110, the voltage switch circuit 120 and the first switch circuit group 130 are connected to the high voltage (first voltage HV); similarly, the voltage switches in the second voltage switch circuit group 160 When the circuit is in a specific state, it also receives a high voltage (the first voltage HV).

Generally speaking, when the logic circuit receives high voltage (HV) during operation, the logic circuit will not be compatible with the traditional logic circuit process, and needs to be completed with a special circuit process, so the logic circuit design will be more complicated And the production cost will increase. In other words, the voltage switch circuit in FIG. 1 cannot be completed by using existing logic circuit manufacturing process, and it needs special circuit manufacturing process to be completed, thus increasing the manufacturing cost.

Therefore, it is the purpose of the present invention to manufacture the voltage switch circuit by using a process compatible with the logic circuit.

Contents of the invention

The object of the present invention is to propose a voltage switch circuit in which a lightly doped (Lightly Doped) PMOS transistor is used to withstand high voltage stress, and the lightly doped (Lightly Doped) PMOS transistor is compatible with the logic circuit process, so the voltage The switch circuit can be completed in the process of logic circuit.

The present invention relates to a voltage switch circuit, comprising: an output circuit including a first PMOS transistor, the source and body of which are connected to a high voltage source, and the drain connected to the inverting output terminal of the voltage switch circuit, the gate is connected to the output terminal of the voltage switch circuit; and, a second PMOS transistor, the source and the body are connected to the high voltage source, the drain is connected to the output terminal of the voltage switch circuit, and the gate is connected to the voltage The inverting output terminal of the switch circuit; a first voltage drop control circuit, including a third PMOS transistor, the body is connected to the high voltage source, the source is connected to the inverting output terminal, and the drain is connected to a node e, the gate is connected to a reference voltage source; and, a fourth PMOS transistor, the body is connected to the high voltage source, the source is connected to the output terminal, the drain is connected to a node f, and the gate is connected to the reference voltage source ; A second voltage drop control circuit, including a first NMOS transistor, a second NMOS transistor, a first bias control circuit and a second bias control circuit; wherein, the drain of the first NMOS transistor is connected to The node e is connected to the control terminal of the first bias control circuit, the gate is connected to the output terminal of the first bias control circuit, the body and the source are connected to a node c; and, the second NMOS transistor has a drain The pole is connected to the node f and the control terminal of the second bias control circuit, the gate is connected to the output terminal of the second bias control circuit, the body and the source are connected to a node d; a third voltage drop control A circuit comprising a third NMOS transistor with a drain connected to the node c, a gate connected to a logic voltage source, a body and a source connected to a node a; and a fourth NMOS transistor with a drain connected to the node d, gate connected to the logic voltage source, body and source connected to a node b; and an input circuit including a fifth NMOS transistor, a sixth NMOS transistor, a third bias voltage control circuit, and A fourth bias control circuit; wherein, the drain of the fifth NMOS transistor is connected to the node a and the output terminal of the third bias control circuit, the gate is connected to the input terminal of the voltage switch circuit, and the body and The source is connected to a ground terminal; and, the sixth NMOS transistor, the drain is connected to the node b and the output terminal of the fourth bias control circuit, the gate is connected to the inverting input terminal of the voltage switch circuit, and the body is Connect the source to this ground.

The present invention relates to a voltage switch circuit, the output terminal of the voltage switch circuit is connected to a bus signal line and the bus signal line can be selectively provided with an input voltage by a control circuit, including: a first NMOS transistor, drain The pole is connected to the output end of the voltage switch circuit, the source and the body are connected to a node b; a first bias voltage control circuit, the control end of the first bias voltage control circuit is connected to the output end of the voltage switch circuit, the The input terminal of the first bias control circuit is connected to the input terminal of the voltage switch circuit, the output terminal of the first bias control circuit is connected to the gate of the first NMOS transistor; the drain of a second NMOS transistor is connected to the node b, the gate connected to a logic voltage source, the source and the body connected to a node a; a second bias control circuit, the control terminal of the second bias control circuit is connected to the input terminal of the voltage switch circuit , the input terminal of the second bias control circuit is selectively connected to the logic voltage source and a read voltage source, the output terminal of the second bias control circuit is connected to the node a; and a third NMOS transistor, The drain is connected to the node a, the gate is connected to the input terminal of the voltage switch circuit, and the source and body are connected to a ground terminal.

The present invention relates to a voltage switch circuit, which has a first voltage drop path including a node a, and a second voltage drop path has a node b, and the voltage switch circuit further includes: an output circuit connected to A high voltage source, and has a first output terminal connected to the first voltage drop path and a second output terminal connected to the second voltage drop path; a plurality of voltage drop control circuits, connected to the first output terminal and the Between the node a and between the second output terminal and the node b; an input circuit connected between the node a and the node b, and the input circuit has a first input terminal and a second input terminal ; wherein, when the first input terminal receives a high logic level and the second input terminal receives a low logic level, the voltage of the node a is equal to a ground terminal, and the first output terminal generates a middle voltage level, The node b generates the high logic level, and the second output end generates the voltage of the high voltage source, wherein the voltage of the high voltage source is greater than the middle voltage level, and the middle voltage level is greater than the high logic level.

In order to have a better understanding of the above and other aspects of the present invention, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of decoding circuit modules in a conventional memory.

FIG. 2A shows a specific embodiment of the voltage switch circuit of the present invention.

FIG. 2B is a schematic diagram of the bias voltage of the voltage switch circuit of the present invention.

FIG. 3A is a schematic diagram of another voltage switch circuit of the present invention.

3B to 3D are schematic diagrams of bias voltages of the voltage switch circuit in various states.

[Description of main component labels]

110: High-voltage decoding switching system 120: Voltage switching circuit

130: First voltage switch circuit group 140: Decoding unit

150: Low-voltage decoding switching system 160: Second voltage switching circuit group

210: output circuit 220: first voltage drop circuit

230: Second voltage drop circuit 232: First bias circuit

234: The second bias circuit 240: The third voltage drop circuit

250: Input circuit 252: The third bias circuit

254: The fourth bias circuit 310: The first bias circuit

320: Second bias circuit 340: Decoding unit

Detailed ways

Today's semiconductor manufacturers can already provide a high-voltage-resistant lightly doped (Lightly Doped) PMOS transistor in a standard logic process. In other words, such low-doped PMOS transistors are resistant to high voltage stress and compatible with today's standard logic processes. Therefore, the present invention utilizes low-doped PMOS transistors to design a voltage switch circuit. That is to say, in the voltage switch circuit of the present invention, only the low-doped PMOS transistor will experience high voltage stress, while other transistors will not experience high voltage stress.

Please refer to FIG. 2A , which shows a specific embodiment of the voltage switch circuit of the present invention. The voltage switch circuit includes: an output circuit 210 , a first voltage drop control circuit (voltage drop control circuit) 220 , a second voltage drop control circuit 230 , a third voltage drop control circuit 240 , and an input circuit 250 . Wherein, the high voltage source (HV) is greater than the reference voltage source (Vref), and the reference voltage source (Vref) is greater than the logic voltage source (VDD).

The output circuit 210 includes a first PMOS transistor pair (PMOS transistor pair), wherein the source (source) and body (body) of the first PMOS transistor p1 are connected to the high voltage source (HV), and the drain (drain) is connected to the inverter The phase output terminal (OUTB), the gate (gate) is connected to the output terminal (OUT); the source and body of the second PMOS transistor p2 are connected to the high voltage source (HV), and the drain is connected to the output terminal (OUT), the gate Connect to the inverting output (OUTB).

The first voltage drop control circuit 220 includes a second PMOS transistor pair, wherein the body of the third PMOS transistor p3 is connected to the high voltage source (HV), the source is connected to the inverting output terminal (OUTB), and the drain is connected to node e, the gate is connected to the reference voltage source (Vref); the body of the fourth PMOS transistor p4 is connected to the high voltage source (HV), the source is connected to the output terminal (OUT), the drain is connected to node f, and the gate is connected to Reference Voltage Source (Vref).

The second voltage drop control circuit 230 includes a first pair of NMOS transistors, a first bias control circuit 232 , and a second bias control circuit 234 .

The first bias control circuit 232 includes a fifth PMOS transistor p5 and a sixth PMOS transistor p6. The source of the fifth PMOS transistor p5 is the input terminal of the first bias control circuit 232 and is connected to the node b, the gate is connected to the reference voltage (Vref), the body and the drain are connected to each other and serve as the input terminal of the first bias control circuit 232 Output terminal; the source of the sixth PMOS transistor p6 is connected to the logic voltage source (VDD), the gate is the control terminal of the first bias control circuit 232 and is connected to the node e, and the body and the drain are connected to each other and connected to the first bias The output terminal of the voltage control circuit 232.

The second bias control circuit 234 includes a seventh PMOS transistor p7 and an eighth PMOS transistor p8. The source of the seventh PMOS transistor p7 is the input terminal of the second bias control circuit 234 and is connected to the node a, the gate is connected to the reference voltage (Vref), the body and the drain are connected to each other and serve as the input terminal of the second bias control circuit 234 Output terminal; the source of the eighth PMOS transistor p8 is connected to the logic voltage source (VDD), the gate is the control terminal of the second bias control circuit 234 and connected to the node f, and the body and the drain are connected to each other and connected to the second bias The output terminal of the voltage control circuit 234.

The first NMOS transistor pair includes: a first NMOS transistor n1 and a second NMOS transistor n2. The drain of the first NMOS transistor n1 is connected to the node e and the control terminal of the first bias control circuit 232, the gate is connected to the output terminal of the first bias control circuit 232, and the body and source are connected to the node c; The drain of the NMOS transistor n2 is connected to the node f and the control terminal of the second bias control circuit 234 , the gate is connected to the output terminal of the second bias control circuit 234 , and the body and source are connected to the node d.

The third voltage drop control circuit 240 includes a second NMOS transistor pair, wherein the drain of the third NMOS transistor n3 is connected to the node c, the gate is connected to the logic voltage source (VDD), and the body and the source are connected to the node a ; The drain of the fourth NMOS transistor n4 is connected to the node d, the gate is connected to the logic voltage source (VDD), and the body and the source are connected to the node b.

The input circuit 250 includes a third pair of NMOS transistors, a third bias control circuit 252 , and a fourth bias control circuit 254 .

The third bias control circuit 252 includes a ninth PMOS transistor p9 whose source and body are the input terminals of the third bias control circuit 252 and connected to the logic voltage source (VDD), and the gate is controlled by the third bias control circuit 252 The terminal is connected to the input terminal IN, and the drain is the output terminal of the third bias voltage control circuit 252 and connected to the node a.

The fourth bias control circuit 254 includes a tenth PMOS transistor p10 whose source and body are the input terminals of the fourth bias control circuit 254 and connected to the logic voltage source (VDD), and the gate is controlled by the fourth bias control circuit 254 The terminal is connected to the inverting input terminal INB, and the drain is the output terminal of the fourth bias voltage control circuit 254 and connected to the node b.

The third NMOS transistor pair includes: a fifth NMOS transistor n5 and a sixth NMOS transistor n6. The drain of the fifth NMOS transistor n5 is connected to node a and the output terminal of the third bias control circuit 252, the gate is connected to the input terminal (IN), and the body and source are connected to the ground terminal; the sixth NMOS transistor n6 The drain is connected to the node b and the output terminal of the fourth bias control circuit 254 , the gate is connected to the inverting input terminal (INB), and the body and source are connected to the ground terminal.

Please refer to FIG. 2B , which is a schematic diagram of the bias voltage of the voltage switch circuit of the present invention. Among them, the high voltage source (HV) is 18V, the reference voltage source (Vref) is 9V, and the logic voltage source (VDD) is 6V. A voltage drop path is formed from the reverse output terminal (OUTB) to the ground terminal, and another voltage drop path is formed from the output terminal (OUT) to the ground terminal. The following describes its operation process in detail.

When the input terminal (IN) receives a high logic level (6V) and the inverting input terminal (INB) receives a low logic level (0V), a third bias control circuit 252 in the input circuit 250 does not operate (inactivated) 1. The fourth bias control circuit 254 is operated (activated), the fifth NMOS transistor n5 is turned on (turnon), and the sixth NMOS transistor n6 is turned off (turn off). At this time, the voltage of the node a is 0V (Va=0V), and the node a The voltage of b is 6V (Vb=6V).

Since the voltage of node a is 0V (Va=0V) and the voltage of node b is 6V (Vb=6V), the third NMOS transistor n3 in the third voltage drop control circuit 240 is turned on, and the fourth NMOS transistor n4 is turned off. At this moment, the voltage of node c is 0V (Vc=0V), and the voltage of node d (Vd) needs to be determined by the second voltage drop control circuit 230 .

Furthermore, since the voltage at node b is 6V (Vb=6V), and the voltage at node c is 0V (Vc=0V), the first bias voltage control circuit 232 in the second voltage drop control circuit 230 (the sixth PMOS transistor p6 is turned on, The output terminal of the fifth PMOS transistor p5 is turned off) will output 6V to the gate of the first NMOS transistor n1 (Vg=6V), so that the first NMOS transistor n1 is turned on, and the voltage of the node e is 0V (Ve=0V).

When the voltage of the node e is 0V (Ve=0V), and the gates of the third PMOS transistor p3 and the fourth PMOS transistor p4 in the first voltage drop control circuit 220 are connected to the reference voltage source (Vref) of 9V, so that The voltage at the inverting output terminal (OUTB), that is, the source voltage of the third PMOS transistor p3, is (9V+|ΔVp|), where ΔVp is the threshold voltage (threshold voltage) of the PMOS transistor.

Next, in the output circuit 210, since the voltage at the inverting output terminal (OUTB) is (9V+|ΔVp|), the second PMOS transistor p2 is turned on, and the voltage at the output terminal (OUT) is equal to the high power supply voltage (HV) which is 18V, The first PMOS transistor p1 is turned off.

Since the output terminal voltage (OUT) is 18V, the fourth PMOS transistor p4 in the first voltage drop control circuit 220 is turned on, and the voltage of the node f is 18V (Vf=18V).

Since the voltage of node f is 18V (Vf=18V) and the voltage of node a is 0V (Va=0), therefore, the eighth PMOS transistor p8 in the second bias control circuit 234 is turned off, so that the second bias control circuit The output terminal of 234 generates a voltage of (9V+|ΔVp|) to the gate of the second NMOS transistor n2 (Vg=9V+|ΔVp|), so the voltage of node d will maintain at 9V (Vd=9V).

Since the voltage switch circuit of the present invention is a left-right symmetrical circuit, when the input terminal (IN) is a low logic level (0V) and the inverting input terminal (INB) is a high logic level (6V), all operations The principle can refer to the above description, so that the output terminal (OUT) generates (9V+|ΔVp|), and the inverting output terminal (OUTB) generates 18V.

Assuming that the threshold voltage ΔVp of the PMOS transistor is (-1V), when the input terminal (IN) receives a high logic level (6V), the output terminal (OUT) can generate 18V of the high voltage source (HV); at the input terminal When (IN) receives a low logic level (0V), the output (OUT) can generate 10V.

Of course, the input terminal (IN) and the inverting input terminal (INB) in Figure 2A can be reversed, so that when the input terminal (IN) receives a low logic level (0V), the output terminal (OUT) can generate a high voltage source (HV) 18V; when the input terminal (IN) receives a high logic level (6V), the output terminal (OUT) can generate 10V.

Alternatively, the output terminal (OUT) and the inverting output terminal (OUTB) in Figure 2A can be reversed, so that when the input terminal (IN) receives a low logic level (0V), the output terminal (OUT) can generate a high voltage source (HV) 18V; when the input terminal (IN) receives a high logic level (6V), the output terminal (OUT) can generate 10V.

Furthermore, it can be known from the bias voltage diagram of the voltage switch circuit that the first to eighth PMOS transistors p1-p8 will bear high voltage stress under certain circumstances, so low-doped PMOS transistors compatible with the logic circuit process are used to complete the process. The first to eighth PMOS transistors p1-p8. Therefore, the voltage switch circuit of the present invention can be completed by logic circuit manufacturing process, and can reduce the cost and the complexity of the circuit design.

The bias control circuit of the present invention can also be applied to the voltage switch circuit in the known second voltage switch circuit group. Referring to FIG. 3A , it is a schematic diagram of another voltage switch circuit of the present invention. Wherein, the output terminal (OUT) of the voltage switch circuit is connected to the array bus signal line (Array-bus), and the decoding unit 340 can selectively provide the input voltage (VPP) to the output terminal (OUT) of the voltage switch circuit.

The voltage switch circuit includes a first NMOS transistor n1 , a second NMOS transistor n2 , a third NMOS transistor n3 , a first bias voltage control circuit 310 , and a second bias voltage control circuit 320 .

The first bias control circuit 310 includes a first PMOS transistor p1 and a second PMOS transistor p2. The source of the first PMOS transistor p1 is the input terminal of the first bias voltage control circuit 310 and is connected to the input terminal (IN) of the voltage switch circuit, the gate is connected to the reference voltage (Vref), the body and the drain are connected to each other and serve as the first The output terminal of the bias voltage control circuit 310; the source of the second PMOS transistor p2 is connected to the logic voltage source (VDD), and the gate is the control terminal of the first bias voltage control circuit 310 and is connected to the output terminal (OUT) of the voltage switch circuit, The body and the drain are connected to each other and to the output terminal of the first bias control circuit 310 .

The drain of the first NMOS transistor n1 is connected to the output terminal (OUT) of the voltage switch circuit, the gate is connected to the output terminal of the first bias control circuit 310 , and the source and body are connected to the node b.

The drain of the second NMOS transistor n2 is connected to the node b, the gate is connected to the logic voltage source (VDD), and the source and body are connected to the node a.

The second bias control circuit 320 includes a source and body of a third PMOS transistor p3 as an input terminal of the second bias control circuit 320 and is selectively connected to a logic voltage source (VDD) or a read voltage source (VR), The gate is the control terminal of the second bias control circuit 320 and is connected to the input terminal (NB) of the voltage switch circuit, and the drain is the output terminal of the second bias control circuit 320 and is connected to node a.

The drain of the third NMOS transistor n3 is connected to the node a, the gate is connected to the input terminal (NB) of the voltage switch circuit, and the source and body are connected to the ground terminal.

Please refer to FIG. 3B to FIG. 3D , which are schematic diagrams showing bias voltages of the voltage switch circuit in various states. Wherein, the input voltage (VPP) provided by the decoding unit 340 is 18V, the reference voltage source (Vref) is 9V, the logic voltage source (VDD) is 6V, and the reading voltage source (VR) is 1.8V. The following describes its operation process in detail.

As shown in FIG. 3B, in the first state, when the 18V input voltage (VPP) provided by the decoding unit 340 is supplied to the output terminal (OUT) of the voltage switch circuit and the input terminal (IN) is at a low logic level (0V), the second The second bias control circuit 320 is activated (activated), the third NMOS transistor n3 is turned off, and the voltage of the node a is 6V (Va=6V).

Since the voltage of the node a is 6V (Va=6V), the gate of the second NMOS transistor n2 is connected to the logic voltage source (VDD) of 6V. Therefore, the second NMOS transistor n2 is turned off, and the voltage of node b (Vb) is determined according to the bias voltage of the first NMOS transistor n1.

Since the voltage of the output terminal (OUT) is 18V (OUT=18V) and the voltage of the input terminal (IN) is a low logic level (IN=0V), the second PMOS transistor p2 in the first bias voltage control circuit 310 closed, so that the output terminal of the first bias control circuit 310 generates a voltage of (9V+|ΔVp|) to the gate of the first NMOS transistor n1 (Vg=9V+|ΔVp|), so the voltage of node b will be maintained at 9V (Vb =9V).

As shown in FIG. 3C, in the second state, when the decoding unit 340 does not provide the 18V input voltage (VPP) to the output terminal (OUT) of the voltage switch circuit and the input terminal (IN) is at a high logic level (6V), the second The second bias control circuit 320 is inactivated, and the third NMOS transistor n3 is turned on, and the voltage of the node a is 0V (Va=0V).

Since the voltage of the node a is 0V (Va=0V), the second NMOS transistor n2 is turned on. At this time, the voltage of node b is 0V (Vb=0V).

Furthermore, since the node b voltage is 0V (Vb=0V) and the input terminal (IN) receives a high logic level of 6V, the first bias voltage control circuit 310 (the second PMOS transistor p2 is turned on, and the first PMOS transistor p1 is turned off) The output terminal of will output 6V to the gate of the first NMOS transistor n1 (Vg=6V), so that the first NMOS transistor n1 is turned on, so that the voltage of the output terminal (OUT) is 0V (OUT=0V).

As shown in FIG. 3D, in the third state, the 18V input voltage (VPP) not provided by the decoding unit 340 is sent to the output terminal (OUT) of the voltage switch circuit and the input terminal (IN) is a low logic level (0V) and the second The input terminals of the two bias voltage control circuits 320 are connected to a read voltage source (VR) of 1.8V. At this moment, the second bias voltage control circuit 320 is activated, and the third NMOS transistor n3 is turned off, and the voltage of the node a is 1.8V (Va=1.8V).

Since the voltage of the node a is 1.8V (Va=1.8V), the gate of the second NMOS transistor n2 is connected to a logic voltage source (VDD) of 6V. Therefore, the second NMOS transistor n2 is turned on, and the voltage of the node b is 1.8V (Vb=1.8V).

Moreover, since the node b voltage is 1.8V (Vb=1.8V) and the input terminal (IN) receives a low logic level of 0V, the first bias voltage control circuit 310 (the second PMOS transistor p2 is turned on, the first PMOS transistor p1 closed) will output 6V to the gate of the first NMOS transistor n1 (Vg=6V), so that the first NMOS transistor n1 is turned on, so that the voltage of the output terminal (OUT) is 1.8V (OUT=1.8V).

It can be known from the bias voltage diagrams of the voltage switch circuit in FIG. 3B to FIG. 3D that the first to second PMOS transistors p1-p2 will bear high voltage stress under certain circumstances, so low-doped PMOS transistors compatible with the logic circuit process are used to The first and second PMOS transistors p1˜p2 are completed. Therefore, the voltage switch circuit of the present invention can be completed by logic circuit manufacturing process, and can reduce the cost and the complexity of the circuit design.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (31)

1. voltage switch circuit comprises:

One output circuit comprises one the one PMOS transistor, and source electrode and the body utmost point are connected to a high voltage source, and drain electrode is connected to the reversed-phase output of this voltage switch circuit, and grid is connected to the output of this voltage switch circuit; And, one the 2nd PMOS transistor, source electrode and the body utmost point are connected to this high voltage source, and output, the grid that drain electrode is connected to this voltage switch circuit is connected to the reversed-phase output of this voltage switch circuit;

One first pressure drop control circuit comprises one the 3rd PMOS transistor, and the body utmost point is connected to this high voltage source, and source electrode is connected to this reversed-phase output, and drain electrode is connected to a node e, and grid is connected to a reference voltage source; And, one the 4th PMOS transistor, the body utmost point is connected to this high voltage source, and source electrode is connected to this output, and drain electrode is connected to a node f, and grid is connected to this reference voltage source;

One second pressure drop control circuit comprises one first nmos pass transistor, one second nmos pass transistor, one first bias control circuit and one second bias control circuit; Wherein, the drain electrode of this first nmos pass transistor is connected to the control end of this node e and this first bias control circuit, and grid is connected to the output of this first bias control circuit, and the body utmost point and source electrode are connected to a node c; And, this second nmos pass transistor, drain electrode is connected to the control end of this node f and this second bias control circuit, and grid is connected to the output of this second bias control circuit, and the body utmost point and source electrode are connected to a node d;

One the 3rd pressure drop control circuit comprises one the 3rd nmos pass transistor, and drain electrode is connected to this node c, grid is connected to a logic voltage source, the body utmost point and source electrode and is connected to a node a; And, one the 4th nmos pass transistor, drain electrode is connected to this node d, grid is connected to this logic voltage source, the body utmost point and source electrode and is connected to a node b; And

One input circuit comprises one the 5th nmos pass transistor, one the 6th nmos pass transistor, and one the 3rd bias control circuit is with one the 4th bias control circuit; Wherein, the 5th nmos pass transistor, drain electrode is connected to the output of this node a and the 3rd bias control circuit, and grid is connected to the input of this voltage switch circuit, and the body utmost point and source electrode are connected to an earth terminal; And, the 6th nmos pass transistor, drain electrode is connected to the output of this node b and the 4th bias control circuit, and grid is connected to the inverting input of this voltage switch circuit, and the body utmost point and source electrode are connected to this earth terminal.

2. voltage switch circuit according to claim 1, wherein the voltage of this high voltage source is greater than the voltage of this reference voltage source, and the voltage of this reference voltage source is greater than the voltage in this logic voltage source.

3. voltage switch circuit according to claim 1, wherein the voltage of this high voltage source is 18V, and the voltage of this reference voltage source is 9V, and the voltage in this logic voltage source is 6V.

4. voltage switch circuit according to claim 1, wherein a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, with the 4th PMOS transistor be high voltage bearing low-doped PMOS transistor.

5. voltage switch circuit according to claim 1, wherein, this first bias control circuit comprises: one the 5th PMOS transistor AND gate 1 the 6th PMOS transistor; Wherein, the 5th PMOS source transistor very this first bias control circuit input and be connected to this node b, grid is connected to that this reference voltage source, the body utmost point interconnect with drain electrode and as the output of this first bias control circuit; And the 6th PMOS transistor, source electrode are connected to this logic voltage source, and grid is for the control end of this first bias control circuit and be connected to this node e, and the body utmost point and drain electrode interconnect and be connected to the output of this first bias control circuit.

6. voltage switch circuit according to claim 5, wherein the 5th PMOS transistor, with the 6th PMOS transistor be high voltage bearing low-doped PMOS transistor.

7. voltage switch circuit according to claim 1, wherein, this second bias control circuit comprises: one the 7th PMOS transistor AND gate 1 the 8th PMOS transistor; Wherein, the 7th PMOS source transistor very this second bias control circuit input and be connected to this node a, grid is connected to that this reference voltage source, the body utmost point interconnect with drain electrode and as the output of this second bias control circuit; And the 8th PMOS transistor source is connected to this logic voltage source, and grid is for the control end of this second bias control circuit and be connected to this node f, and the body utmost point and drain electrode interconnect and be connected to the output of this second bias control circuit.

8. voltage switch circuit according to claim 7, wherein the 7th PMOS transistor, with the 8th PMOS transistor be high voltage bearing low-doped PMOS transistor.

9. voltage switch circuit according to claim 1, wherein the 3rd bias control circuit comprises: one the 9th PMOS transistor, source electrode and body very the 3rd bias control circuit input and be connected to this logic voltage source, grid for the control end of the 3rd bias control circuit and be connected to this voltage switch circuit input, drain electrode is for the output of the 3rd bias control circuit and be connected to this node a.

10. voltage switch circuit according to claim 1, wherein the 4th bias control circuit comprises: 1 the tenth PMOS transistor, source electrode and body very the 4th bias control circuit input and be connected to this logic voltage source, grid for the control end of the 4th bias control circuit and be connected to this voltage switch circuit inverting input, drain electrode is for the output of the 4th bias control circuit and be connected to this node b.

11. a voltage switch circuit, the output of this voltage switch circuit are connected to a bus signal line and this bus signal line can optionally provide an input voltage by a control circuit, comprising:

One first nmos pass transistor, drain electrode is connected to the output of voltage switch circuit, and source electrode and the body utmost point are connected to a node b;

One first bias control circuit, the control end of this first bias control circuit is connected to the output of this voltage switch circuit, the input of this first bias control circuit is connected to the input of this voltage switch circuit, and the output of this first bias control circuit is connected to this first nmos pass transistor grid;

One second nmos pass transistor, drain electrode is connected to this node b, grid is connected to a logic voltage source, source electrode and the body utmost point and is connected to a node a;

One second bias control circuit, the control end of this second bias control circuit is connected to the input of this voltage switch circuit, the input of this second bias control circuit optionally is connected to this logic voltage source and one and reads voltage source, and the output of this second bias control circuit is connected to this node a; And

One the 3rd nmos pass transistor, drain electrode are connected to input, source electrode and the body utmost point that this node a, grid be connected to this voltage switch circuit and are connected to an earth terminal.

12. voltage switch circuit according to claim 11, wherein the input voltage of this control circuit is greater than the voltage of this reference voltage source, the voltage of this reference voltage source is greater than the voltage in this logic voltage source, and the voltage in this logic voltage source reads the voltage of voltage source greater than this.

13. voltage switch circuit according to claim 11, wherein the input voltage of this control circuit is 18V, and the voltage of this reference voltage source is 9V, and the voltage in this logic voltage source is 6V, and this voltage that reads voltage source is 1.8V.

14. voltage switch circuit according to claim 11, wherein a PMOS transistor, with the 2nd PMOS transistor be high voltage bearing low-doped PMOS transistor.

15. voltage switch circuit according to claim 11, wherein, this first bias control circuit comprises: one the one PMOS transistor AND gate 1 the 2nd PMOS transistor; Wherein, the one PMOS source transistor very this first bias control circuit input and connect the input of this voltage switch circuit, grid is connected to that this reference voltage source, the body utmost point interconnect with drain electrode and as the output of this first bias control circuit; And, the 2nd PMOS transistor, source electrode is connected to this logic voltage source, and grid is the control end of this first bias control circuit and the output that is connected to this voltage switch circuit, and the body utmost point and drain electrode interconnect and be connected to the output of this first bias control circuit.

16. voltage switch circuit according to claim 11, wherein, this second bias control circuit comprises: one the 3rd PMOS transistor, source electrode and body very this second bias control circuit input and optionally be connected to this logic voltage source with this read voltage source, grid for the control end of this second bias control circuit and be connected to this voltage switch circuit input, drain as the output of this second bias control circuit and be connected to this node a.

17. a voltage switch circuit has one first pressure drop path, comprises a node a, and one second pressure drop path has a node b, this voltage switch circuit also comprises:

One output circuit is connected in a high voltage source, and has that one first output is connected in this first pressure drop path and one second output is connected in this second pressure drop path;

A plurality of pressure drop control circuits, be connected between this first output and this node a and be connected between this second output and this node b;

One input circuit is connected in this node a and this node b, and this input circuit has a first input end and one second input;

Wherein, when this first input end receives a high logic level and this second input and receives a low logic level, the voltage of this node a equals an earth terminal, this first output produces voltage level in, this node b produces this high logic level, and this second output produces the voltage of this high voltage source, wherein, the voltage of this high voltage source is greater than voltage level in this, and voltage level is greater than this high logic level in this.

18. voltage switch circuit according to claim 17, wherein the voltage of this high voltage source is 18V, and voltage of voltage level is 10V in this, and the voltage in this logic voltage source is 6V.

19. voltage switch circuit according to claim 17, wherein, this output circuit comprises one the one PMOS transistor, and source electrode and the body utmost point are connected to this high voltage source, and drain electrode is connected to this second output, and grid is connected to this first output; And, one the 2nd PMOS transistor, source electrode and the body utmost point are connected to this high voltage source, and drain electrode is connected to this first output, grid is connected to this second output.

20. voltage switch circuit according to claim 17, wherein, this first pressure drop path also comprises a node c and a node e; This second pressure drop path has a node d and a node f, and one first pressure drop control circuit in these a plurality of pressure drop control circuits comprises: one the 3rd PMOS transistor, the body utmost point is connected to this high voltage source, source electrode is connected to this second output, drain electrode is connected to this node e, and grid is connected to a reference voltage source; And, one the 4th PMOS transistor, the body utmost point is connected to this high voltage source, and source electrode is connected to this first output, and drain electrode is connected to this node f, and grid is connected to this reference voltage source; Wherein, the voltage of this reference voltage source is less than voltage level in this, and the voltage of this reference voltage source is greater than the voltage in this logic voltage source.

21. voltage switch circuit according to claim 20, wherein the voltage of this reference voltage source is 9V.

22. voltage switch circuit according to claim 20, wherein a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, with the 4th PMOS transistor be high voltage bearing low-doped PMOS transistor.

23. voltage switch circuit according to claim 20, wherein, one second pressure drop control circuit in these a plurality of pressure drop control circuits comprises: one first nmos pass transistor, one second nmos pass transistor, one first bias control circuit and one second bias control circuit; Wherein, the drain electrode of this first nmos pass transistor is connected to the control end of this node e and this first bias control circuit, and grid is connected to the output of this first bias control circuit, and the body utmost point and source electrode are connected to this node c; And, this second nmos pass transistor, drain electrode is connected to the control end of this node f and this second bias control circuit, and grid is connected to the output of this second bias control circuit, and the body utmost point and source electrode are connected to this node d.

24. voltage switch circuit according to claim 23, wherein, this first bias control circuit comprises: one the 5th PMOS transistor AND gate 1 the 6th PMOS transistor; Wherein, the 5th PMOS source transistor very this first bias control circuit input and be connected to this node b, grid is connected to that this reference voltage source, the body utmost point interconnect with drain electrode and as the output of this first bias control circuit; And the 6th PMOS transistor, source electrode are connected to this logic voltage source, and grid is for the control end of this first bias control circuit and be connected to this node e, and the body utmost point and drain electrode interconnect and be connected to the output of this first bias control circuit.

25. voltage switch circuit according to claim 24, wherein the 5th PMOS transistor, with the 6th PMOS transistor be high voltage bearing low-doped PMOS transistor.

26. voltage switch circuit according to claim 23, wherein, this second bias control circuit comprises: one the 7th PMOS transistor AND gate 1 the 8th PMOS transistor; Wherein, the 7th PMOS source transistor very this second bias control circuit input and be connected to this node a, grid is connected to that this reference voltage source, the body utmost point interconnect with drain electrode and as the output of this second bias control circuit; And the 8th PMOS transistor source is connected to this logic voltage source, and grid is for the control end of this second bias control circuit and be connected to this node f, and the body utmost point and drain electrode interconnect and be connected to the output of this second bias control circuit.

27. voltage switch circuit according to claim 26, wherein the 7th PMOS transistor, with the 8th PMOS transistor be high voltage bearing low-doped PMOS transistor.

28. voltage switch circuit according to claim 23, wherein, one the 3rd pressure drop control circuit in these a plurality of pressure drop control circuits comprises: one the 3rd nmos pass transistor, and drain electrode is connected to this node c, grid is connected to this logic voltage source, the body utmost point and source electrode and is connected to this node a; And, one the 4th nmos pass transistor, drain electrode is connected to this node d, grid is connected to this logic voltage source, the body utmost point and source electrode and is connected to this node b.

29. voltage switch circuit according to claim 17, wherein, this input circuit comprises one the 5th nmos pass transistor, one the 6th nmos pass transistor, and one the 3rd bias control circuit is with one the 4th bias control circuit; Wherein, the 5th nmos pass transistor, drain electrode is connected to the output of this node a and the 3rd bias control circuit, and grid is connected to the input of this voltage switch circuit, and the body utmost point and source electrode are connected to this earth terminal; And, the 6th nmos pass transistor, drain electrode is connected to the output of this node b and the 4th bias control circuit, and grid is connected to the inverting input of this voltage switch circuit, and the body utmost point and source electrode are connected to this earth terminal.

30. voltage switch circuit according to claim 29, wherein the 3rd bias control circuit comprises: one the 9th PMOS transistor, source electrode and body very the 3rd bias control circuit input and be connected to this logic voltage source, grid for the control end of the 3rd bias control circuit and be connected to this first input end, drain electrode is for the output of the 3rd bias control circuit and be connected to this node a.

31. voltage switch circuit according to claim 29, wherein the 4th bias control circuit comprises: 1 the tenth PMOS transistor, source electrode and body very the 4th bias control circuit input and be connected to this logic voltage source, grid for the control end of the 4th bias control circuit and be connected to this second input, drain electrode is for the output of the 4th bias control circuit and be connected to this node b.

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