CN105590866B

CN105590866B - Method for determining individual die identifier and multi-chip module device

Info

Publication number: CN105590866B
Application number: CN201410558275.7A
Authority: CN
Inventors: 陈毓明
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2014-10-20
Filing date: 2014-10-20
Publication date: 2019-01-15
Anticipated expiration: 2034-10-20
Also published as: CN105590866A

Abstract

The present invention provides a method for determining individual die identifiers and a multi-chip module device. Individual die IDs are determined based on their individual unique identifiers (UIDs) in a plurality of commonly packaged memory dies as a memory device. An external controller starts an internal die ID (DID) determination process, and after determining a number of clock signals based on its UID, each die eventually triggers a signal on its inter-die signal pin, and before its own signal responds, assigns its own die ID based on the number of signals triggered by other dies. Before each die's own signal responds, each die records the number of signals triggered by other dies, and the total number of signals on the signal pin can selectively determine the number of packaged dies of the device.

Description

Determine the method and multi-wafer modular device of individual crystalline grains identifier

Technical field

The present invention relates to the multi-memory crystal grain (memory die) that one kind encapsulates jointly, and in particular to one kind Multi-memory crystal grain for encapsulating jointly determines the method and multi-wafer modular device of individual crystalline grains identifier.

Background technique

It is common thing that two or more memory crystal grains, which are packaged in an encapsulation, to be used for various uses.Crystal grain can be It is identical or different.It is partially or even wholly to interconnect in partial picture crystal grain individual interfaces crystal grain, it is therefore desirable to use To distinguish the technology of the pin between different crystal grain using encapsulation.When crystal grain is identical type, this problem can become special Seriously.

The chip selection pin of stacked memory crystal grain can be used for differentiating crystal grain in crystal grain.It is taken off on January 30th, 2013 It is exposed to tables of data " the S70FL256P 256-Mbit CMOS 3.0 of Fei Suo semiconductor limited liability company (Spansion Inc.) Volt Flash Memory with 104-MHz SPI Multi I/O Bus " amendment the 5th edition.Two identical 128Mb Crystal grain is stacked on their other chip selection inputs and is bonded to individual pins of encapsulation to form flash memory device.So Memory device be operable to identical Serial Peripheral Interface (SPI) (Serial Peripheral Interface, referred to as SPI) the SPI device of two separation of bus, user select (Chip select) primary access twin crystal grain by individual wafer The crystal grain stacked.Adversely, controller is required to provide and manage multiple/CS control signal.In addition, two or more chips The demand of selection pin eliminates quaternary SPI and quaternary peripheral interface (Quad Peripheral Interface, abbreviation QPI) The option suitable as the encapsulation of eight pins.

Memory crystal grain typically has unique identifier (Unique Identifier, the abbreviation established during fabrication UID), controlled for producing.An example of suitable UID is device number, process lot number, wafer number and crystal grain The combination of X-Y coordinate ensures that the uniqueness of UID.If peripheral control unit learns that UID, UID so can be by generally connecing Mouth to identify a crystal grain and other crystal grain in a package.Unfortunately, it is a after crystal grain interface is interconnects during manufacture Other UID may be inaccessible, so that individual UID may be unknown for external controller.

It is special that technology after encapsulation in the stacked position of the programmable memory crystal grain of multiple grain memory device is exposed in the U.S. Sharp application publication number US 2009/0085608, inventor Alzheimer are disclosed on April 2nd, 2009.Each crystal grain is corresponding Identify data bit drive output signal to share output end in the crystal grain of crystal grain.Each crystal grain also includes arbitration (arbitration) circuit, the control signal for generating the identification bit corresponding to crystal grain do not match the correspondence of other crystal grain Identification bit.It controls signal and stacks enabled fuse (stack enable fuse) according to the particular result programming of arbitration.

Summary of the invention

The present invention provides the method and multi-wafer modular device of a kind of decision individual crystalline grains identifier.

One embodiment of the invention provides a kind of decision individual crystalline grains identifier (Die Identifier, abbreviation DID) Method is suitable for multiple common sealed storage device crystal grain with individual unique identifiers (UID), comprising: enabled memory is brilliant Common connection (common connection) between grain；Unique identifier based on memory crystal grain establishes the memory The individual crystalline grains selection criterion of crystal grain；Timing movement synchronously is carried out to memory crystal grain；And the meter in each memory crystal grain When movement during: determine when crystal grain selection criterion be meet timing movement operation when；It generates and corresponds to being located at for deciding step Signal in common connection；Common connection is monitored before the generation step, brilliant there are increasing when signal when connecting jointly Grain position (Die Position, abbreviation DP) parameter；And DP parameter is established as DID.

Another embodiment of the present invention provides a kind of multi-wafer modular device, comprising: multiple memory crystal grains respectively include Unique identifier (UID), crystal grain identifier (DID) control circuit, multiple interface pins and intercrystalline signal pin (inter-die signaling pin)；And encapsulation, the multiple memory accommodated in multi-wafer model block configuration are brilliant Grain, and encapsulate with multiple encapsulation pins, encapsulating pin, at least one is coupled to the interface pins of each memory crystal grain At least one, wherein each memory crystal grain has memory addressing ability；Wherein each DID control circuit packet Include: signal circuit is coupled to the intercrystalline signal pin；Counter circuit is coupled to the signal circuit and is configured to base Start the signal circuit when several clock signals occurs in UID；And event counter, it is coupled to intercrystalline signal pin and warp Configuration is with before there are several clock signals based on UID, the increase when each signal positioned at intercrystalline signal pin occurs Die locations (DP) parameter.

Detailed description of the invention

Fig. 1 is the illustrative view of functional configuration of the embodiment of SPI flash memory polycrystalline sheet devices；

Fig. 2 is the function of the embodiment for any type polycrystalline sheet devices that any type have common sealed storage device crystal grain It can structural schematic diagram；

Fig. 3 is the structural schematic diagram with the SPI-NOR flash memory crystal grain of DID decision circuitry；

Fig. 4 is the flow chart that a DID judges process；

Fig. 5 is the flow chart that another DID judges process；

Fig. 6 is that the DID of Fig. 5 judges the circuit structure diagram and waveform diagram of process；

Fig. 7 is the flow chart that another DID judges process；

Fig. 8 is the plane for the multi-wafer module for having stacked memory crystal grain and having spacer body (spacer) between crystal grain Side view；

Fig. 9 be with using crystal grain be staggered (staggering) stacked memory crystal grain multi-wafer module planar side View；

Figure 10 is the planar side view with the multi-wafer module of various sizes of stacked memory crystal grain；

Figure 11 is the structural schematic diagram of the DID control circuit of another embodiment.

Description of symbols:

100: Multi-chip encapsulating device；

110,120,130,140,820,840,920,940:SPI flash memory crystal grain；

150:SPI encapsulates pin；

200: Multi-chip encapsulating device；

210,220,230,240,1020,1040: crystal grain；

250: encapsulation pin；

260: internal connection；

300:NOR flash memory crystal grain；

310: instruction processing and control circuit；

320:NOR flash memory array；

322: high-pressure generator；

323: page address latch/counter；

324: write protection logical AND column decoder；

326: byte address latch device/counter；

328: row decoder and page buffer；

330: register；

340,370,610,620,630,640:DID control circuit；

342: counter；

344: comparator；

346,376: connector；

348,374: monitor；

350,612,622,632,642: drawing upwardly device；

360: transistor；

372: counter can be preloaded into；

378:NAND；

400~420,500~520,700~740: process；

616,626,636,646: weld pad；

614,624,634,644: pull device；

800,900,1000:SPI flash memory device；

810,910,1010: packaging body；

830: spacer body；

861,862,863,864,980,990,1021,1022,1041: conducting wire；

850,950,1050: adhesive；

860,960,1060: cooling pad；

870,880,970,1070,1080: lead；

930,1030: material；

/ CS ,/HOLD, IO3 ,/WP, IO2, DO, IO1, DI, IO0: pin；

BP: weld pad；

CLK: clock pulse；

CNT: it counts；

ENABLE: enabled；

UID: unique identifier；

DP: die locations；

GND: ground connection；

INPUT: input；

OUTPUT: output；

PDC: encapsulation crystal grain counts；

PRELOAD: it is preloaded into；

VCC, Vcc: power supply；

Vss: negative supply voltage.

Specific embodiment

Embodiment described herein, which is concentrated on, determines unique crystal grain mark for Serial Peripheral Interface (SPI) flash memory device Know symbol, the multi-die package technology such as polycrystalline in any requirement can be used in any number of which SPI flash memory crystal grain Piece module (Multiple Chip Module, abbreviation MCM) is encapsulated as single device together, under the advantages of maintaining SPI interface, To realize for example every bit of different performances inexpensive (low per-bit cost), high density storage, to random access memory Device (Random Access Memory, abbreviation RAM) code covers (code shadowing) and fast random accesses in execution One of (execute in place) application or said combination.However, technology described herein can be used for memory crystalline substance Any combination of grain, regardless of whether it is identical, there is completely or partially common connecting interface, and can be used in any It is required that multi-die package technology be encapsulated as single device together, including for example stack, be mounted on same layer (mounted in- Plane) miniature printed circuit board or ceramic substrate, be mounted on multilayer (multi-layer) laminated printed circuit boards or ceramic base Plate is deposited on substrate (base substrate) using thin film technique etc..

Fig. 1 is the illustrative view of functional configuration of the embodiment of SPI flash memory polycrystalline sheet devices；Specifically, Fig. 1 is tool There are a group four identical SPI flash memory crystal grain 110, SPI flash memory crystal grain 120, SPI flash memory crystal grain 130, SPI flash memory crystal grain 140 is collectively coupled to the Multi-chip encapsulating device 100 of one group of SPI encapsulation pin 150, Described in SPI flash memory crystal grain 110, SPI flash memory crystal grain 120, SPI flash memory crystal grain 130, SPI quick flashing The SPI interface having the same of memory crystal grain 140.Individual SPI memory crystal grain 110, SPI flash memory crystal grain 120, SPI One of flash memory crystal grain 130, pin of SPI interface of SPI flash memory crystal grain 140 use described herein Technology can be used for communication (signaling).Fig. 2 is any type multi-wafer that any type have common sealed storage device crystal grain The illustrative view of functional configuration of the embodiment of device；Specifically, Fig. 2 show the tool of Multi-chip encapsulating device 200, there are four a groups Crystal grain 210, crystal grain 220, crystal grain 230, crystal grain 240, the crystal grain 210, crystal grain 220, crystal grain 230, crystal grain 240 can have or can There is no any kind or the identical interface of more than one type, but has part (having shown that) or whole (not shown) common It is connected to one group of encapsulation pin 250.Crystal grain can be entirely different or identical, or part can be different and part can be identical. For example, the connection 260 that is common but being fully located inside of one separation can be used for crystal grain 210, crystalline substance using technology described herein Grain 220, crystal grain 230, the communication between crystal grain 240.It is retouched herein alternatively, being commonly connected to one of encapsulation pin and can be used The technology stated makees the communication between crystal grain.

Technology described herein makes every crystal grain in two or more common encapsulation crystal grain, can be relative to last Crystal grain in crystal grain or encapsulation determines unique crystal grain identifier (Die Identifier, abbreviation DID), and if wanting It asks, it is also possible to find the crystal grain participated in decision sum.What no matter the address pins of crystal grain or address can configure (address-configurable) interface section of pin or be fully collectively coupled to encapsulation pin, this decision all can It generates.Each crystal grain has any kind of unique identifier (UID), for example, in the identifier for handling foundation earlier, this mark Know symbol to specify for producing control.Peripheral control unit transmits specific instruction, for example, decision DID instruction, initial internal crystal grain ID Judge that process requires unique crystal grain ID in encapsulation crystal grain jointly.Each crystal grain have for crystal grain ID judge in process with other The signal pin of crystal grain communication.Signal pin can be one of interface pins, and interface pins can be collectively coupled to one Or more other crystal grain in one or more other similar interface pins to corresponding encapsulation pin, or it is not external A part of interface pins, therefore can not be connect with any encapsulation pin, but as instead uniquely or with other function It can be provided as crystal grain ID decision together, when crystal grain receives clock pulse, and after determining by its UID the number of clock signal, each crystalline substance Grain finally triggers (assert) signal in its intercrystalline signal pin, and the signal number based on triggering assigns the crystal grain of itself ID (if occur above situation, by other crystal grain triggering be prior to itself signal respond).Each crystal grain record is by other crystalline substances The signal number of grain triggering, and selectively, by the encapsulation number of die of the signal sum determination device on signal pin.

Fig. 3 is the structural schematic diagram with the SPI-NOR flash memory crystal grain of DID decision circuitry, such as NOR flash memory Reservoir crystal grain 300 comprising NOR (or non-) flash memory array 320 and interlock circuit such as high-pressure generator 322, page Face address latch/counter 323, write protection logical AND column decoder 324, byte address latch device/counter 326, with And row decoder and page buffer 328.Shown type of memory is for example, and can be used in required with interlock circuit Any type of memory and interlock circuit.Instruction processing handles the different instruction received with control circuit 310, for example, SPI Interface, including clock pulse CLK, pin/CS, pin/HOLD or pin IO3, pin/WP or pin IO2, pin DO or pin IO1, And pin DI or pin IO0.Although the NOR flash memory crystal grain of SPI interface is used below in crystal grain ID judgment technology 300 can describe, and it is any kind of whole or local shared interface that technology, which is suitable for all types of memory crystal grains, The encapsulation of (common interface), including mixing of different types memory crystal grain such as NOR, NAND (with non-), resistance-type RAM (Resistive RAM, abbreviation ReRAM) and Electrically Erasable Programmable Read-Only Memory (Electronically Erasable Programmable Read Only Memory, abbreviation EEPROM).It is fitted in single bit and more bit SPI The NOR and nand memory and additional information of conjunction, which can be found in, gives the 7,558,900th of Jigour et al. on July 7th, 2009 Number United States Patent (USP) and the publication of Huabang Electronics Co., Ltd, including October in 2013,16 solar corona nation electronics share was limited The publication W25Q256FV of company: " spiflash 3V 256M-Bit Serial Flash Memory with Dual/ The publication W25N01GV of Quad SPI&QPI " version F and Huabang Electronics Co., Ltd's on November 26th, 2013: “spiflash 3V 1G-Bit Serial SLC NAND Flash Memory with Dual/Quad SPI& The preliminary version B of Continuous Read ", the above patent and publication are incorporated herein in a manner of being cited in full text.

Crystal grain ID (DID) control circuit 340 for being shown in Fig. 3 is separated from instruction processing with control circuit 310 clearly to show Show, however DID control circuit can also be required to be integrated to instruction processing and control circuit 310.DID control circuit 340 includes enabled ENABLE input, clock pulse CLK input, unique identifier UID input, signal pin input INPUT, the output of signal pin It is defeated that OUTPUT, the output of die locations DP parameter and encapsulation crystal grain count (Packaged Die Count, abbreviation PDC) parameter Out.Signal pin is connected to signal circuit, can be, for example, any suitable drop-down or pull-up circuit.Pull-down circuit can As shown in figure 3, its weak pull-up device 350 such as transistor, diode, resistance and similar component, VCC for using are provided to weak Drawing upwardly device 350 and pull device may be, for example, metal-oxide half field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviation MOSFET) transistor 360, source electrode, which is connected to, inputs INPUT, and drain electrode is connected to Ground connection GND or negative supply voltage Vss and grid are connected to output OUTPUT.Particular value depends on the design details of crystal grain, weak Drawing upwardly device 350 may be, for example, resistance, and resistance value can be 3M Ω at 3V VCC, and mosfet transistor 360 may be, for example, N class Type.It is interfered in order to prevent in the general operation of the interface pins jointly connected, weak pull-up device 350 is preferably only inside Portion DID judges that process works.Drawing upwardly device (not shown) may include that strong pull-up device is series at weak pull-down device.

The UID input of DID control circuit 340 can receive UID bit from register, can for directly (not shown) or indirectly Ground is usually to build on to handle in early days via instruction processing and control circuit 310.For example, UID bit can be deposited from being located at The read-only register or read/write register of device 330 receive.UID bit compared with the counting CNT generated in counter, It can be by external clock pulse CLK signal timing.Counter 342 can be started counting when receiving enable signal, and be believed in each clock pulse CLK Number increase count.The output of comparator corresponds to be provided by the particular kind of relationship counted between CNT and UID that comparator 344 detects To transistor 360 grid with pulldown signal pin, to other crystal grain of communication.

The monitoring of monitor 348 input INPUT is to detect the drop-down of signal pin, for determining DP and PDC.In some implementations Example, monitor 348 can also be by the monitoring comparison results (shown in dotted line) of connector 346, for determining DP.

Figure 11 is the structural schematic diagram of the DID control circuit of another embodiment；As shown in figure 11, DID control circuit 370, Including being preloaded into, PRELOAD input, clock pulse CLK input, unique identifier UID input, signal pin inputs INPUT, signal connects Foot exports OUTPUT, the output of die locations DP parameter and encapsulation crystal grain and counts the output of PDC parameter.Signal pin, which is connected to, appoints There is source electrode to be connected to input for what suitable weak pull-up device 350 and any suitable pull device, such as transistor 360 INPUT, drain electrode is connected to ground connection GND or negative supply voltage Vss and grid is connected to output OUTPUT.UID bit is preloaded into It can be extremely preloaded into counter 372, can be to count up or count downwards.Counter 372 can be preloaded into can be by external clock pulse CLK Signal timing.It is to be provided to any suitable group by suitable signal wire that the count value of counter 372 can be preloaded by, which being stored in, Combinational logic circuit is used to detect pre-determined condition, such as to NAND gate 378 to detect zero count.The output of NAND gate 378 It supplies to the grid of transistor 360 pre-determined count value pulldown signal pin ought be being reached, to other crystal grain of communication.

The monitoring of monitor 374 input INPUT is to detect signal pin drop-down, to determine DP and PDC.In some implementations Example, monitor 374 can also be by the monitoring comparison results (shown in dotted line) of connector 346, for determining DP.

DID control circuit 340 and DID control circuit 370 can by any suitable hardware, software, firmware or it is any on Combination is stated, including realizing as the mode of state machine (state machine).

Fig. 4 is the flow chart that a DID judges process, such as: DID control circuit 340, DID control circuit 370.It is being connected to Determine DID instruction (process 400), for example it can be the form of two byte operation codes (opcode), initialize any in DID The element (process 402) of the counter of control circuit and other states.When being ready to provide crystal grain ID to based on specific die The specific die (process 404 is) that UID is determined, the signal of (inter-chip) is touched between the chip of the signal pin of crystal grain (process 406) is sent out to notify all common encapsulation crystal grain.When signal is present in signal pin (process 408), signal pin Also it is monitored to detect.If not detecting signal so (process 408 is no), DID control circuit is advanced (advanced) state (process 416) and repetition (process 418 is no) or termination (process 418 is) process.If signal so It is detected (process 408 is) and not yet meets UID crystal grain selection criterion (process 410 is no), increase both DP parameter and PDC parameter (process 412).If signal so is detected (process 408 is) and has met UID crystal grain selection criterion (process 410 is), Then only have PDC parameter to increase (process 414).Although in schematic flow, if the signal of trigger signal pin, DID control Circuit processed does not increase DP, when UID crystal grain selection criterion meets, DP can increase (shortly past process 404 be after), by the first crystalline substance Whether the crystal grain ID of grain is intended to become 0 or 1.DID control circuit is that advanced state (process 416) and process can be to repeat (process 418 is no) or terminate (process 418 is).

Fig. 5 is the flow chart that another DID judges process, and Fig. 6 is that the DID of Fig. 5 judges the circuit structure diagram and wave of process Shape figure.Internal DID judges that process 500 counts PDC ginseng using CNT parameter, die locations DP parameter and encapsulation crystal grain is counted Number, above-mentioned counting CNT parameter, die locations DP parameter and encapsulation crystal grain count PDC parameter and are initially set to 0 (process 502). PDC is selectable, but in certain processes for example from last crystal grain bending pitch of the laps (wrap-around) to the first crystal grain in sequence Reading data can be highly useful.Compare the UID (process 504) of CNT crystal grain.In case of matching (match), under crystal grain Its signal pin (process 506) is drawn, therefore communication is indicated to other crystal grain encapsulated jointly it is determined that the crystal grain encapsulated jointly Crystal grain ID.In addition to this signal pin is without being interrupted.Process continues monitoring signal pin pull-down state (process 508).If Signal pin is not pulled down, indicates that no crystal grain ID is determined, and CNT increases (process 510) and repeats process (process 518 is not) Until end (process 518 be).If signal pin is pulled down, UID compares CNT (process 512) again, or works as CNT= Whether when (not shown) can be read in UID, the element of stateful (stateful) is set, to determine specific die it is determined that it is brilliant Grain ID.If UID is greater than CNT, specific die not yet determines its crystal grain ID, therefore DP and PDC increase (process as CNT 516).However, specific die is it is determined that its crystal grain ID, therefore DP not will increase, although PDC and CNT are still if UID is not more than CNT Continue growing (process 514).

Fig. 6 shows four DID control circuits 610, DID control circuit 620, DID control circuit 630, DID control circuit 640 are coupled to four individual weld pad (pad) weld pads 616, weld pads 626, weld pad 636, weld pad 646 in individual crystalline grains.Weld pad 616, weld pad 626, weld pad 636, weld pad 646 for example engage (wire bonded) together with conducting wire.Each weld pad 616, weld pad 626, weld pad 636, weld pad 646 are respectively provided with the above-mentioned drawing upwardly device 612, drawing upwardly device 622, drawing upwardly device 632, pull-up of connection Device 642 and pull device 614, pull device 624, pull device 634, pull device 644, for example, pull device can be crystalline substance Body pipe.Drawing upwardly device 612, drawing upwardly device 622, drawing upwardly device 632, drawing upwardly device 642 are coupled to power Vcc.Four DID controls Circuit 610, DID control circuit 620, DID control circuit 630, DID control circuit 640 are provided individual UID, such as have respectively There is value 99,1,210 and 12.To four all DID control circuits 610, DID control circuit 620, DID control circuit 630, For DID control circuit 640, counting CNT waveform can be to be identical, and similarly all crystal grain can be synchronized to common clock.? Counting CNT is under the first count value, and DID control circuit 620 is first and matches its UID, and pulls down its weld pad 626, makes it His DID control circuit 610, DID control circuit 630, DID control circuit 640 increase their individual DP parameters as responding.DID The DP of control circuit 620 is maintained at when detecting matched initial value, specifically for " 0 ".When CNT is the 12nd count value, DID Control circuit 640 is next its UID of matching, and pulls down its weld pad 646, makes DID control circuit 610, DID control circuit 630 increase their individual DP parameters as response.When a match is detected, the DP of DID control circuit 640 is maintained at its increase by one Secondary numerical value, specifically for " 1 ".When CNT is the 99th count value, DID control circuit 610 is next its UID of matching, and Its weld pad 616 is pulled down, therefore DID control circuit 630 increases its DP parameter as response.When a match is detected, DID control electricity The DP on road 610 is maintained at it and increases secondary numerical value, i.e. " 2 ".When CNT is the 210th count value, DID control circuit 630 It is next its UID of matching, and pulls down its weld pad 636.When a match is detected, the DP of DID control circuit 630 is maintained at it Increase numerical value three times, i.e., " 3 ".Fig. 6 also illustrates PDC corresponding to first, the 12nd, the 99th, the 210th count value Increase.At the end of process 500, each DID control circuit 610, DID control circuit 620, DID control circuit 630, DID control Circuit 640 processed have it is determined that DP parameter, can be stored in read/write register (for example, register 330 (figure 3)) be used as crystal grain ID, and it is determined that PDC parameter can be stored in read/write register.The BP of Fig. 6 is weld pad (Bonding Pad)。

Determine that process 500 can be terminated by several means.For example, when clock pulse loop reaches preset number or returns When zero, the decision process in each crystal grain terminates.Again by way of further example for, each crystal grain can by participate in determine crystal grain quantity Lai It carries out preprogramming (pre-programmed), or is guided by providing the crystal grain quantity for participating in determining as decision The parameter of (Determination Instruction), and stop to determine process when event counter reaches the number.

Fig. 7 is the flow chart that another DID judges process.When clock pulse CLK starts, enable signal is connect by crystal grain ID control circuit It receives, as response, crystal grain ID control circuit sets count parameter " CNT ", crystal grain ID parameter " DID " and encapsulation crystal grain and counts ginseng " PDC " is counted to zero (process 702).Compare the UID (process 704) of crystal grain in next clock pulse CNT.If not detecting matching (stream Journey 704 it is no), then detect the state (process 710) of signal pin.If signal pin is not pulled down (process 710 no), indicate There is the UID met without encapsulation crystal grain jointly, increases (process 714) in next clock pulse CNT, and return in the process of next clock pulse Compare CNT and UID (process 704).If signal pin is pulled down (process 710 be), indicate in addition to possessing the specific of matching UID Other crystal grain other than crystal grain, DP and PDC increase (process 712), and CNT increases (process 714) in next clock pulse, and process It returns to and compares CNT and UID (process 704) in next clock pulse.Return to process 704, if detect matching detection (process 704 It is), the output OUTPUT of comparator is triggered therefore signal pin is pulled down (process 720) and increases (process in last DP 722).If situation needs, the crystal grain of pulldown signal pin do not need for oneself to be included in when setting DP parameter (that is, If situation needs DP, counting can start from scratch), process 722 can be omitted.Then, the state (process 730) of signal pin is detected. If signal pin is pulled down (process 730 be), PDC increases (process 732).CNT can increase (process in two cases 734) and the judgement (process 736) whether CNT reaches its numerical value is made.Process 700 can terminate (process 740) or return to monitoring letter Number pin is to monitor the drop-downs (process 730) of other crystal grain.

As following, the variation of these processes and other similar algorithms can be used for only using signal connection to determine crystal grain ID。

Judgement process described herein is it is particularly advantageous to the SPI flash encapsulated for stacking and being encapsulated in eight pins Device crystal grain.Eight pins encapsulation so can be used to realize that signal pin can connect for SPI for whole SPI protocols including quaternary SPI One of mouth pin, or can be the special pin provided in crystal grain, it is not connected to any encapsulation pin.

It is of the invention that the low-density crystal grain of same type, which is stacked to form highdensity serial flash memory device, One of example.The capacity of single crystal grain is 256Mb, for example, the serial flash memory crystal grain of two same types It is stackable to realize 512Mb (2x256Mb) device, and the serial flash memory crystal grain of four same types is stackable to realize 1Gb (4x256Mb) device.The example of SPI-NOR flash memory crystal grain application type is limited to be used in winbond electronics share The type of the product type W25Q256FV of company, referring to the publication of the October in 2013 of Huabang Electronics Co., Ltd on the 16th W25Q256FV: " spiflash 3V256M-Bit Serial Flash Memory with Dual/Quad SPI&QPI " version This F, case disclosed above are incorporated herein in a manner of being cited in full text, and the disclosure can be suitably modified to judge comprising crystal grain ID Circuit, software/firmware, instruction and the control logic that crystal grain selection instruction can be handled.It can also be used for SPI flash memory crystal grain Other types, such as four stacking SPI-NAND flash memory crystal grain are for example for the product of Huabang Electronics Co., Ltd The type of model W25N01GV, referring to the publication W25N01GV of Huabang Electronics Co., Ltd's on November 26th, 2013: “spiflash 3V 1G-Bit Serial SLC NAND Flash Memory with Dual/Quad SPI& The preliminary amendment B of Continuous Read ", case disclosed above is incorporated herein in a manner of being cited in full text, and the disclosure can be fitted Locality modification is to include crystal grain ID decision circuitry, software/firmware, instruction and the control logic that can handle crystal grain selection instruction.? Other kinds of SPI-NOR and SPI-NAND flash memory crystal grain can be used, as required.Minimum two SPI quick flashings Memory crystal grain stacking just has its advantage, and more generally, the present invention can be used for any quantity.Although the n times side using 2 is convenient , the quantity of SPI flash memory crystal grain is not limited to 2 n times side.

In addition, different types of flash memory crystal grain is stackable to realize that single memory device has suitable for specific The unique combination of application performance.Particularly modification (the specially- of SPI-NOR type flash memory and some types Modify) SPI-NAND type flash memory is suitable for code application such as execution (execute-in-place) and code screening It covers (code shadowing), however SPI-NAND type flash memory is generally applicable to high density data storage.Two types The flash memory crystal grain of type may be stacked in an encapsulation to provide two kinds of performances.The size of the memory array of multiple crystal grain can It is same or different, or can and part difference identical for part.The stacking and performance enhancement of NOR crystal grain and NAND crystal grain (performance-enhanced) further information is illustrated in U.S. Patent Application Publication No. US 2012/0084491, Inventor Eungjoon Park et al. is disclosed on April 5th, 2012.Case disclosed above is incorporated to this in a manner of being cited in full text Text, and the disclosure can be suitably modified to select comprising crystal grain ID decision circuitry, software/firmware, instruction with that can handle crystal grain Select the control logic of instruction.

As used herein, term " memory crystal grain " include any single type or multiple types memory array and The integrated-circuit die of one group interface pin, any of them single type or a plurality of types of memory arrays can for NOR, The combination of NAND, ReRAM, EEPROM and any of above type, and a group interface pin includes one or more pin For memory addressing and data.Interface protocol includes SPI, internal integrated circuit (I2C), the serial (3-Wire of three lines ) including single bit and more bit serialized interface agreements and parallel etc. serial.The major function of memory crystal grain is several According to the crystal grain of storage.

As used herein, term " SPI flash memory crystal grain " includes any single type or multiple types flash Device array and meet SPI protocol a group interface pin integrated-circuit die.

As used herein, term " pin " refers to connecing for the electric conductivity to exposed electrical connection serial flash memory crystal grain Mouthful element, no matter it is that a contact on crystal grain, such as weld pad or one are embedded in that encapsulation is upper (including to be placed in hidden The contact of my place) contact, swash of wave contacts etched (flush contacts) and prominent contact (projecting contacts) Such as prominent (prong) and ball grid array ball (Ball Grid Array ball, abbreviation BGA ball) etc..

As used herein, term " SPI- elasticity (SPI-compliant) pin " refers to the group interface for conforming to SPI protocol Pin.According to SPI protocol, six pin configurations can be list SPI, double SPI, quaternary SPI and quaternary peripheral interface (Quad Peripheral Interface, abbreviation QPI) (also referred to as serial quaternary interface (Serial Quad Interface), or " SQI "), and including single bit or more bit instructions and/or address input and single bit or multi-bit data output, to the greatest extent Pipe configurability may be limited by the subclass of any demand of above-mentioned form.Six pins provide chip selection/CS, clock pulse CLK, configurable pin (configurable pin) DI (IO0), configurable pin DO (IO1), configurable pin/WP (IO2), And configurable pin/HOLD (IO3).It is operated in single bit SPI, configurable pin can be used as data input pin DI, number According to output connecting pin DO (or single pin (single pin) DIO is configurable as input and output), reversed (bar) write protection Pin/WP and reversely holding pin/HOLD.For double SPI, configurable pin can be used as input/output pin IO0, defeated Enter/output connecting pin IO1, write protection pin/WP and keep pin/HOLD.For quaternary SPI and QPI, configurable pin It can be used as input/output pin IO0, input/output pin IO1, input/output pin IO2 and input/output pin IO3.

In an embodiment, 2 or 4 SPI flash memory crystal grain are respectively provided with six pins in accordance with SPI protocol, in addition to There are two pins respectively as power supply (VCC) and ground connection (GND), and described 2 or 4 SPI flash memory crystal grain such as Fig. 8 extremely The mode of Figure 10 encapsulates together.It so stacks and common encapsulation SPI flash memory crystal grain can provide following benefit: is (a) more Stacking SPI flash memory crystal grain has single entities (physical) pin/CS；(b) eight pins encapsulate implementable quaternary SPI behaviour Make；(c) some SPI operations (concurrent) can execute simultaneously；(d) existing SPI flash memory crystal grain only need to do compared with Small modification；(e) it is suitable for typical multi-die package technology；And (f) heterogeneous (heterogeneous) SPI flash memory Reservoir crystal grain is stackable to achieve the purpose that more performances and multi-effect.Use the SPI so for stacking SPI flash memory crystal grain Flash memory device is compatible in conventional flash memories instruction group, and is instructed and increased by any suitable " crystal grain selection ". Schematic crystal grain selection instruction can be the two byte hexadecimal operation codes (opcode) used by eight bit crystal grain ID.Although needing The amount of bits wanted is to be determined by the stackable maximum value of SPI flash memory device crystal grain supported, and up to four stack Two bits are enough when crystal grain, and eight bits are to be reserved to crystal grain ID, therefore crystal grain ID can end at byte boundary (byte Boundary) and this crystal grain ID is usually as memory instructions.

Crystal grain selection instruction may operate at following manner, in any other SPI quick flashing of multiple grain stacked package selection Memory crystal grain.Crystal grain selection instruction is distributed to SPI flash memory device and specific die by controller (not shown) Unique crystal grain ID to demand access.All stacked dies correspond to crystal grain selection instruction.The crystal grain identifier match of crystal grain Entire SPI instruction set can be corresponded in the crystal grain ID content (argument) of crystal grain selection instruction.The crystal grain mark of other crystal grain The crystal grain ID argument that knowledge symbol does not match crystal grain crystal grain selection instruction can correspond to the subclass of SPI instruction group, referring to herein Locate to close as general (Universal) subset of instructions, otherwise not correspond to SPI instruction set (set).If to occurring simultaneously (concurrent) support of operation has demand, and the SPI order (command) of non-selected crystal grain and control logic can be held It is continuous to execute any current ongoing internal operation.This performance can be designed into SPI instruction and each stacking SPI flash memory The control logic of crystal grain.Schematic crystal grain selection instruction, which is stacked and operated with another viewpoint, stacks retouching for flash memory crystal grain It states in 2 months 2014 U.S. Patent Application No. 14/194,248 filed in 28 days, entitled " Stacked Die Flash Memory Device with Serial Peripheral Interface ", inventor Hui Chen and Teng Su (generation Manage people label No.1770.035.US1N), the above application case is incorporated herein in a manner of being cited in full text.

Although stacking SPI flash memory crystal grain may be disposed at the encapsulation with additional pins, although and this patent document The technology can make in conjunction with other technologies using additional pins in simple and very small-sized foot position (footprint) eight Pin encapsulates the stacking that can carry out multiple SPI flash memory crystal grain.Eight pins encapsulation for example, small outline integrated circuit (Small Outline Integrated Circuit, abbreviation SOIC) type, and extremely small thin outline without lead (Very Very Thin Small Outline No Lead, abbreviation WSON) type, since eight pins are encapsulated in system printing The small-sized foot position of circuit-board laying-out, therefore the selection for keeping serial flash memory device popular.

Fig. 8 is the plane for the multi-wafer module for having stacked memory crystal grain and having spacer body (spacer) between crystal grain Side view；Specifically, it includes two heaps in packaging body 810 that Fig. 8, which is eight pin WSON type SPI flash memory devices 800, The planar side view of folded SPI flash memory crystal grain 820, SPI flash memory crystal grain 840.It can be used in any suitable heap Folded technology, SPI flash memory device 800 are ensured using spacer body (spacer) 830 in SPI flash memory crystal grain 820 Bottom surface and conducting wire and bonding wire (for example, conducting wire 863, conducting wire 864 and associated in 840 top surface of SPI flash memory crystal grain Bonding wire) between have enough spaces.Spacer body can be any suitable type, and schematically be top surface and bottom surface is bonding plane The material of solid or viscous adhesive (viscous cement) or other engagement materials.SPI flash memory crystal grain 840 Using any suitable technology, for example, adhesive 850 or other engagement materials, are attached to cooling pad 860.SPI flash memory 820 conducting wire of crystal grain be bonded to lead frame (lead frame) different leads (for example, conducting wire 861, conducting wire 862, conducting wire 863, Conducting wire 864 and associated bonding wire are to lead 870, conducting wire 880).The different leads of lead frame, for example, lead 870, lead 880, it exposes to the open air across packaging body 810 to provide the weld pad for being connected to external circuit.Although the bonding wire illustrated is manufacture at from crystal grain Can also be for from crystal grain to crystal grain to lead or bonding wire, and then it can also be for from bottom die to lead.Although being illustrated as conducting wire to connect It closes, but the joining technique that can be used any other suitable between any crystal grain, for example, via hole replaces.

Fig. 9 be with using crystal grain be staggered (staggering) stacked memory crystal grain multi-wafer module planar side View；Specifically, it includes two stacking SPI that Fig. 9, which is eight pin WSON type SPI flash memory devices 900 in packaging body 910, The planar side view of flash memory crystal grain 920, SPI flash memory crystal grain 940.SPI flash memory device 900 uses brilliant Grain migration technology is to avoid 920 bottom surface of SPI flash memory crystal grain and leading in the top surface of SPI flash memory crystal grain 940 Interference between line and bonding wire (such as conducting wire 990 and associated bonding wire).Use any suitable material 930, for example, glue Mixture or top surface and bottom surface are the material of the solid of bonding plane, to ensure SPI flash memory crystal grain 920, SPI flash The stacking of device crystal grain 940.SPI flash memory crystal grain 940 use any suitable technology, for example, adhesive 950 or other connect Material is closed, cooling pad 960 is attached to.SPI flash memory crystal grain 920,940 conducting wire of SPI flash memory crystal grain are bonded to and draw The different leads (schematical, conducting wire 980, conducting wire 990 and associated bonding wire and lead 970) of wire frame.Lead frame Different leads (schematical, lead 970) pass through packaging body 910 and expose to the open air to provide the weld pad for being connected to external circuit.Although example The bonding wire shown is manufacture at can also be for from crystal grain to crystal grain from crystal grain to lead or bonding wire, and then can also be for from bottom die To lead.Although being illustrated as conducting wire engagement, the joining technique that can be used any other suitable between any crystal grain, citing and Speech, via hole replace.

Figure 10 is the planar side view with the multi-wafer module of various sizes of stacked memory crystal grain；Specifically, figure 10 be eight pin WSON type SPI flash memory devices 1000 in packaging body 1010 include two stacking SPI flash memories The planar side view of crystal grain 1020, SPI flash memory crystal grain 1040.SPI flash memory device 1000 uses different sizes Or the crystal grain of shape is to avoid 1020 bottom surface of SPI flash memory crystal grain and in 1040 top surface of SPI flash memory crystal grain Interference between conducting wire and bonding wire (such as conducting wire 1041 and associated bonding wire).Using any suitable material 1030, such as For the material for the solid that adhesive or top surface and bottom surface are bonding plane, with ensure to stack SPI flash memory crystal grain 1020, SPI flash memory crystal grain 1040.SPI flash memory crystal grain 1040 uses any suitable technology, such as adhesive 1050 Or other engagement materials are attached to cooling pad 1060.SPI flash memory crystal grain 1020, SPI flash memory crystal grain 1040 Part pin conducting wire is bonded to different leads (schematical, conducting wire 1021, conducting wire 1041 and the associated bonding wire of lead frame With lead 1070).Other pins are served only for internal connection (such as conducting wire 1022 and associated bonding wire).Crystal grain 1020,1040 In for signal crystal grain ID judge process the pin jointly connected can be connected to by conducting wire 1021,1041 pin of conducting wire to Lead 1070 (or as shown in Figure 8 by conducting wire 861, conducting wire 863 to lead 870), or can be connected to separately by 1022 pin of conducting wire One crystal grain.The different leads (schematical, lead 1070, lead 1080) of lead frame pass through packaging body 1010 and expose to the open air to provide It is connected to the weld pad of external circuit.Although being illustrated as conducting wire engagement, any other can be used between any crystal grain suitable to connect For example, for example, via hole replaces conjunction technology.

Stack Technology described herein and other Stack Technologies are not necessarily exclusive mutually, and more than two such skills Art can be used for manufacturing any given stack.Different Stack Technologies are widely disclosed among technical field；For example, It is disclosed in the patent application publication case in the U.S. the 2011/0195529th of No. 11 Wu of in August, 2011, the above patent to draw in full It is incorporated herein with mode.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims

1. A method for determining individual die identifiers, suitable for a plurality of co-packaged memory dies having individual unique identifiers, comprising:

enabling common connections between the memory dies;

establishing individual die selection criteria for the memory die based on the unique identifier for the memory die;

timing the memory die synchronously; and

During the timing action of each of the memory dies:

The determining step of each of the memory die includes:

reading the unique identifier into a comparator of each of the memory dies;

increasing the counter of each of the memory dies as a timing action of each of the memory dies to provide a count value;

comparing the count value of the unique identifier to determine a match indicating that the die selection criteria are met;

determining when the die selection criterion is in line with the operation of the timing action;

generating a signal on the common connection corresponding to the decision step;

monitoring the common connection prior to the generating step to increase a die position parameter when a signal is present on the common connection; and

The die position parameter is established as the die identifier.

2 . The method of claim 1 , further comprising establishing the common connection to the individual internal signal pins of the memory die coupled across wires or vias. 3 . connect.

3. The method of claim 1, wherein the memory die is packaged in a multi-die module configuration having multiple package pins, further comprising creating a cross-wire or Vias are coupled to individual interface pins of the memory die and the common connection of one of the package pins.

4. The method of claim 1, further comprising monitoring the common connection to increase a package die count parameter when a signal is present on the common connection.

5 . The method of claim 4 , further comprising establishing the common connection to the individual internal signal pins of the memory die coupled across wires or vias. 6 . connect.

6. The method of claim 4, wherein the memory die is packaged in a multi-die module configuration having a plurality of package pins, further comprising creating a cross-wire or Vias are coupled to individual interface pins of the memory die and the common connection of one of the package pins.

7. The method of claim 1, further comprising monitoring the common connection during the generating step during the timing action of each of the memory dies , to increase the die position parameter when the commonly connected signal is detected.

8. A method of determining individual die identifiers suitable for a plurality of co-packaged memory dies having individual unique identifiers, comprising:

enabling common connections between the memory dies;

timing the memory die synchronously; and

During the timing action of each of the memory dies:

The determining step of each of the memory die includes:

preloading the unique identifier into a counter of each of the memory dies to establish the value of the counter;

operating the counter as an operation of the timing action for each of the memory dies to change the value stored in the counter;

detecting that the value stored in the counter is a predetermined value indicating that the die selection criterion is met;

The die position parameter is established as the die identifier.

9. A multi-chip module device comprising:

a plurality of memory dies, respectively including a unique identifier, a die identifier control circuit, a plurality of interface pins, and inter-die signal pins; and

a package that accommodates the plurality of memory dies in a multi-chip module configuration, and the package has a plurality of package pins, at least one of which is coupled to all of the memory dies at least one of the interface pins, wherein each of the memory dies has memory addressing capability;

Each of the die identifier control circuits includes:

a signal circuit, the signal circuit includes a pull-up device and a pull-down device, the pull-up device is coupled to the inter-die signal pin, the pull-down device is coupled to the inter-die signal pin, the The pull-down device has a control input;

a counter circuit coupled to the signal circuit and configured to activate the signal circuit when a number of clock signals occur based on the unique identifier, the counter circuit including a counter and a comparator, the counter configured to providing an incremented count value, the comparator has a first input coupled to the counter, a second input coupled to the unique identifier, and an output coupled to all of the pull-down device the control input, the comparator configured to provide a pull-down signal to the output when a predetermined relationship between the count value and the unique identifier is generated; and

a signal counter including a pull-down counter coupled to the inter-die signal pin and configured to The die position parameter is added when each pull-down of the inter-die signal pins is described.

10 . The multi-chip module device of claim 9 , wherein in each of the memory dies, one of the inter-die signal pins and the interface pins are identical. 11 .

11 . The multi-chip module device of claim 9 , wherein in each of the memory dies, the inter-die signal pins and the interface pins are separate and distinct. 12 .

12. The multi-die module device of claim 9, wherein the signal counter of each of the die identifier control circuits is further configured to occur when a number of clock signals occur based on the unique identifier , increasing the die position parameter when a signal appears on the inter-die signal pin.

13. A multi-chip module device comprising:

Each of the die identifier control circuits includes:

a counter circuit coupled to the signal circuit and configured to activate the signal circuit when a number of clock signals occur based on the unique identifier, the counter circuit including a preloadable counter and a detector, the the pre-readable counter is configured to initially preload the unique identifier as the counter circuit value and to change the counter circuit value in accordance with the clock signal, the detector is configured to A pre-determined value of the counter occurs at the output to provide a pull-down signal; and

a signal counter including a pull-down counter coupled to the inter-die signal pin and configured to internally The die position parameter is increased when each of the die signal pins is pulled down.