CN105681815A - Method for increasing storage speed of reconstruction data of de-blocking filter module - Google Patents
Method for increasing storage speed of reconstruction data of de-blocking filter module Download PDFInfo
- Publication number
- CN105681815A CN105681815A CN201510930646.4A CN201510930646A CN105681815A CN 105681815 A CN105681815 A CN 105681815A CN 201510930646 A CN201510930646 A CN 201510930646A CN 105681815 A CN105681815 A CN 105681815A
- Authority
- CN
- China
- Prior art keywords
- data
- macro
- block
- row
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000000694 effects Effects 0.000 claims description 25
- 238000001914 filtration Methods 0.000 claims description 25
- 238000013507 mapping Methods 0.000 abstract description 5
- 241001269238 Data Species 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention relates to a method for increasing storage speed of reconstruction data of a de-blocking filter module. The invention provides a macroblock-based linear address mapping method which is different from the conventional two-dimensional address mapping storage mode in order to ensure a large amount of data of the de-blocking filter module for H.264 high-definition video coding to be reliably written into an external DDR2 (Double Data Rate 2) memory at high speed. The method comprises the following steps of responding to a write operation request sent by a coding core; continuously and linearly writing the data into cache; computing a to-be-accessed base address of an external memory; splicing data and computing a row address; and writing the data into an off-chip memory when a DDR2 controller is idle. According to the method, the requirements for the storage speed of the DBF data needed by high-definition real-time coding can be met.
Description
Technical field
The invention belongs to IC design technology, the method relating to improving block-eliminating effect filtering Restructuring Module data rate memory.
Background technology
Owing to the reconstruct write operation data volume of the DBF module of H.264 HD video coding is huge, and write operation is based on (each macro block has 16 row 2 column data) of macro block, often write a macro block when therefore writing DDR2SDRAM according to two-dimensional address and to carry out 16 row operations, this greatly reduces the speed of write operation and efficiency. In order to not change firmware (firmware), external memory address space is distributed, improve the reconstruct data write efficiency of block-eliminating effect filtering module, realize high definition real-time coding, it is proposed to improve the method that block-eliminating effect filtering module (being called for short DBF module) reconstructs data rate memory.
Summary of the invention
It is an object of the invention to provide a kind of method improving block-eliminating effect filtering Restructuring Module data rate memory, when the connected mode and the firmware address space distribution that do not change controller, it is possible to be effectively improved high speed write speed of operation and the efficiency of DBF Restructuring Module data.
The technical solution of the present invention is:
The method improving block-eliminating effect filtering Restructuring Module data rate memory, comprises the following steps:
1) the block-eliminating effect filtering data continuously linear write buffer memory of the two field picture that coding core is sent;
2) block-eliminating effect filtering data are spliced into the form that chip external memory needs:
2.1) splicing block-eliminating effect filtering data are read from buffer memory;
2.2) room of reserved 4 row brightness after the data write of first macro-block line terminates, 2 row colourities;
2.3) judge whether next macro-block line is 24 row, if it is, proceed to step 2.4; If not, the data of this macro-block line to be divided into 4 row brightness 2 row colourities and the data of 12 row brightness 6 row colourities, then the data of 4 row brightness 2 row colourities are write the reserved location place of each macro block of last macro-block line, 12 row brightness 6 row colourities write the macro block position that this macro-block line is corresponding, and reserved empty position is for next macro-block line write simultaneously; Repeat step 2.3;
2.4) brightness data of this macro-block line is first write 4 row for filling the reserved location of last macro-block line correspondence macro block, then 4 row data of remaining 12 row and request next time are integrated with the correspondence position of last macro-block line;
3) this two field picture initial address in sheet external memory is calculated;
4) address carrying out off-chip DDR2SDRAM storage chip maps:
4.1) in DDR2SDRAM memorizer, judge that signal distinguishes top field, field, the end according to field, the end, top, then by the brightness data of this two field picture according to one-dimensional mode Coutinuous store, top therein field data is placed on the first half in the luminance frame space by the initial address of this two field picture, and end field data is placed on the latter half in the luminance frame space that 1/2nd of this frame space highly corresponding addresses are risen;
4.2) in DDR2SDRAM memorizer, judge that signal distinguishes top field, field, the end according to field, the end, top, then by the chroma data of this two field picture according to one-dimensional mode Coutinuous store, top therein field data is placed on the first half in the chrominance frames space that the initial address striding across this frame brightness space rises, and end field data is placed on the latter half in the chrominance frames space that 1/2nd of chrominance frames space highly corresponding addresses are risen; Height is chrominance frames space two times of described luminance frame space;
4.3) calculation code core maps new_addr to the address of DDR2 controller, new_addr is mapped to the DDR2SDRAM physical address identified, then the reconstruct data of DBF module are continuously written in DDR2SDRAM storage chip according to the order of " top field brightness-end field brightness-field, top colourity-field, end colourity " successively;
Described calculation code core maps new_addr such as following formula to the address of DDR2 controller:
Mc_width_mbs × mb_rows_cnt ÷ 32+wxloc ÷ 2 × 32+ (new_yloc × 2-mb_rows_cnt × 32);
Mc_width_mbs: the picture traverse in units of macro block;
Mb_rows_cnt: macro-block line counts;
Wxloc: the abscissa of each macro block in units of pixel;
New_yloc: the vertical coordinate of each macro block in units of pixel.
Concretely comprising the following steps of the block-eliminating effect filtering data continuously linear write buffer memory of the two field picture that coding core is sent by above-mentioned steps 1:
Each macro block is sequentially written in from left to right by macro-block line, then writes the data of next macro-block line, till all data of last macro-block line all run through from coding core.
Above-mentioned steps 3 calculates this two field picture the concretely comprising the following steps of initial address in sheet external memory:
When new request arrives, DBF module distinguishes reconstruct data and down-sampled data, for reconstruct data, and present frame address that DBF module provides according to firmware and the two-dimensional coordinate of this operation, calculate this module and be mapped to the initial address of DDR2 controller input.
Beneficial effects of the present invention:
The mass data that the present invention encodes block-eliminating effect filtering module in order to ensure H.264 HD video reliably can write outside DDR2 memorizer at high speed, when the connected mode and the firmware address space distribution that do not change controller, propose a kind of to be different from traditional two-dimensional address and map storage mode, namely based on the linear address mapping method of macro block. First the method responds the write operation requests that coding core sends, and in the write buffer memory of data continuously linear, will then calculate the external memory storage base address to access; Splice data again, calculate rank addresses; Just write data in chip external memory when the DDR2 controller free time. Therefore, the present invention can be effectively improved high speed write speed of operation and the efficiency of DBF Restructuring Module data, thus the storage speed demand of DBF data needed for meeting high definition real-time coding
Accompanying drawing explanation
Fig. 1 is module system Organization Chart used by the present invention;
Fig. 2 is data connecting method of the present invention;
Fig. 3 is the storage mode in DDR2SDRAM of the present invention;
Fig. 4 is that the present invention controls module status machine;
The data that Fig. 5 is DBF write operation of the present invention flow away to figure;
Fig. 6 is the FB(flow block) of the present invention.
Detailed description of the invention
The present invention improves the method (block-eliminating effect filtering module is hereinafter referred to as DBF module) of block-eliminating effect filtering Restructuring Module data rate memory, referring to Fig. 6, has steps of:
Step 1, the data continuously linear write buffer memory that coding core is sent;
Step 2, block-eliminating effect filtering data reading from buffer memory and are spliced into the form that chip external memory needs: the macro-block line number of data lines for a two field picture beginning and end is not 16 (brightness), 8 (colourities), therefore the data of first macro-block line should reserve the room of 4 row brightness, 2 row colourities after the write of each macro block terminates;
Data for the macro-block line that line number is 16 to be divided into two parts (4 row brightness 2 row colourities, 12 row brightness 6 row colourities) data, and the data of 4 row brightness 2 row colourities are write the reserved location place of each macro block of last macro-block line, then remaining 12 row brightness 6 row colourities write the macro block position that this macro-block line is corresponding, and still reserved empty position writes for macro-block line below simultaneously;
When being written to last macro-block line, for brightness data: each macro block divides three operations, first write 4 row for filling the reserved location of last macro-block line correspondence macro block, then 4 row data of remaining 12 row and request next time are integrated with the correspondence position of last macro-block line;
Step 3, calculates the two field picture initial address in sheet external memory;
Step 4, block-eliminating effect filtering data address in off-chip DDR2SDRAM storage chip maps: in DDR2SDRAM memorizer, image stores according to one-dimensional mode, and brightness data is according to the initial address Coutinuous store of a two field picture. Top field data is placed on the first half (initial address) in a frame space, and end field data is placed on the latter half (address that 1/2nd of a frame are highly corresponding);
The write operation of colourity is identical with brightness method for designing, and simply the initial address of colourity needs to stride across the space of a frame brightness. The write operation processing mode of field mode is similar with frame pattern, simply needs to judge that signal distinguishes top field, field, the end according to field, the end, top. The reconstruct data of DBF module are continuously sequentially written in DDR2SDRAM storage chip according to " top field brightness-end field brightness-field, top colourity-field, end colourity " successively;
Map as follows from coding core to the address of DDR2 controller:
New_addr:mc_width_mbs*mb_rows_cnt*32+wxloc/2*32+ (new_yloc*2-mb_rows_cnt*32);
Mc_width_mbs: the picture traverse in units of macro block;
Mb_rows_cnt: macro-block line counts;
Wxloc: the abscissa of each macro block in units of pixel;
New_yloc: the vertical coordinate of each macro block in units of pixel;
New_addr is mapped to the DDR2SDRAM physical address (time-sharing multiplex two-dimensional address) identified.
In above-mentioned steps 1, do not consider the initial address of each macro block respectively, and the data in each macro block are linearly writing in order (namely, each macro block is sequentially written in from left to right by macro-block line, then the data of next macro-block line are write, until the data of last macro-block line write complete); Data can be regarded as one-dimensional Coutinuous store by this write operation, have only to latch the initial address of each brightness and chrominance macroblock during write operation.Each macro block has 16 row 2 to arrange data, and write operation is all first line by line every time, and end of being expert at goes to next wardrobe again, is written of till data all run through from coding core until all of 32.
In above-mentioned steps 3,
Distinguish data type: the address calculation of DBF module is used in differentiation reconstruct data and down-sampled data, when write operation requests new for DBF arrives, data type is judged according to type signal, when in the data write DDR2SDRAM once asked, the state machine of address calculation module will proceed to IDLE state, waits request next time;
Step 3 calculates initial address: the address calculation of DBF module is for producing the initial address of block-eliminating effect filtering write operation, DBF space initial address that this module can provide according to firmware (firmware) and the two-dimensional coordinate of this operation, calculate this module and be mapped to the initial address of DDR2 controller input.
The module system Organization Chart of the present invention is as shown in Figure 1.
1, the handshake operation of block-eliminating effect filtering module:
Coding core sends write operation requests signal, and write request module judges that the data of write are reconstruct or down-sampled data, judges whether DBF Write post module becomes full simultaneously, is then responding to request signal, and sends grant signal; Next cycle sends strobe signal again, in the data that the coding core of same cycle that strobe signal sends writes to rear end DBF module. The write operation of data is realized alternately according to such the shaking hands of req-grant-strobe. Each macro block is sequentially written in from left to right by macro-block line, then writes the data of next macro-block line, until the data of last macro-block line write complete.
Each macro block has 16 row 2 to arrange, and write operation is all carry out line by line every time, and end of being expert at goes to next wardrobe again, till all of 32 data all read from buffer memory.
2, the write operation initial address of block-eliminating effect filtering reconstruct data calculates:
When the write operation requests encoding core sends, judge data type according to type signal. DBF address calculation module distinguishes reconstruct data and down-sampled data. When data type is for reconstruct data, { x, y} calculate DBF module and are mapped to the initial address of DDR2 controller for DBF space initial address that DBF address module can provide according to firmware and the two-dimensional coordinate of this operation.
3, the data connecting method of DBF module:
As shown in Figure 2. The number of data lines of first macro-block line is 12, is spliced into the macro block of 16 row, is continuation address storage in a macro block, then initial address should be all 32 alignment of data every time. Therefore the room of 4 row brightness, 2 row colourities is reserved in the write of each macro block after terminating.
The data of second macro-block line to be divided into two parts (4 row brightness 2 row colourities, 12 row brightness 6 row colourities) data, then 4 row brightness (8 continuous datas) or 2 row colourities (4 continuous datas) are write the reserved location place of each macro block in last macro-block line. Before each macro block, the write operation initial address of 4 row brightness 2 row colourities is the initial address that a upper macro-block line is corresponding.
For second remaining 12 row brightness of macro-block line or 6 row colourities, then write the beginning address location that this macro-block line is corresponding, still leave a blank 4 row brightness simultaneously in advance or 2 row colourities use for macro-block line below. By that analogy, for the macro-block line except first and last, all adopt the method splicing data.
When being written to last macro-block line, for brightness: each macro block divides three operations, first write 4 row for filling the reserved location of last macro-block line correspondence macro block, then 4 row data of remaining 12 row and request next time are integrated with the correspondence position of last macro-block line.
4, DBF reconstructs data address mapping mode in DDR2SDRAM memorizer:
DBF reconstructs data address mapping mode in DDR2SDRAM memorizer as shown in Figure 3.
In DDR2SDRAM memorizer, image stores according to one-dimensional mode, and brightness data is according to the initial address Coutinuous store of a two field picture. Top field data is placed on the first half (initial address) in a frame space, and end field data is placed on the latter half (address that 1/2nd of a frame are highly corresponding).
The write operation of colourity is identical with brightness method for designing, and simply the initial address of colourity needs to stride across the space of a frame brightness. The write operation processing mode of field mode is similar with frame pattern, simply needs to judge that signal distinguishes top field, field, the end according to field, the end, top. The reconstruct data of DBF module are continuous being sequentially written in DDR2SDRAM storage chip according to " top field brightness-end field brightness-field, top colourity-field, end colourity " successively.
Map as follows from coding core to the address of DDR2 controller:
New_addr:mc_width_mbs*mb_rows_cnt*32+wxloc/2*32+ (new_yloc*2-mb_rows_cnt*32)
Finally new_addr is mapped to the DDR2SDRAM time-sharing multiplex two-dimensional address identified.
5, state machine controls and data stream:
Fig. 4 is that the present invention controls module status machine;
After system reset, state machine enters DBF_IDLE state; The write request data of DBF reconstruct when FIFO buffer memory, then buffer_ready unequal to 0 state machine simultaneously jumps to DBF_REQ, it was shown that DBF module can send write request to DDR2; If buffer_ready unequal to 0 condition is unsatisfactory for, then state machine is maintained at DBF_IDLE state;
In DBF_REQ state, as wr_ddr2_gnt==1 ' b1, entering DBF_RDDATA state, now DDR2 controller is all set, it is possible to starts to write DBF and reconstructs data; If wr_ddr2_gnt==1 ' b1 is unsatisfactory for, illustrates that other module takies controller, needed to wait for, and kept the state asking to write DDR2;
In DBF_RDDTA state, as wr_ddr2_end==1 ' b1, entering DBF_IDLE state, now back-end logic DBF module has been completed that data are to the write operation in DDR2, and forwards DBF_IDLE state to, and response encodes the write operation requests of core next time; If wr_ddr2_end==1 ' b1 is unsatisfactory for, illustrates that data also do not write complete in DDR2, remain in DBF_RDDATA state.
DBF write operation module can flow away to being divided into some child-operations according to data simply, specifically as shown in Figure 5.
Claims (3)
1. the method improving block-eliminating effect filtering Restructuring Module data rate memory, it is characterised in that: comprise the following steps:
1) the block-eliminating effect filtering data continuously linear write buffer memory of the two field picture that coding core is sent;
2) block-eliminating effect filtering data are spliced into the form that chip external memory needs:
2.1) splicing block-eliminating effect filtering data are read from buffer memory;
2.2) room of reserved 4 row brightness after the data write of first macro-block line terminates, 2 row colourities;
2.3) judge whether next macro-block line is 24 row, if it is, proceed to step 2.4; If not, the data of this macro-block line to be divided into 4 row brightness 2 row colourities and the data of 12 row brightness 6 row colourities, then the data of 4 row brightness 2 row colourities are write the reserved location place of each macro block of last macro-block line, 12 row brightness 6 row colourities write the macro block position that this macro-block line is corresponding, and reserved empty position is for next macro-block line write simultaneously; Repeat step 2.3;
2.4) brightness data of this macro-block line is first write 4 row for filling the reserved location of last macro-block line correspondence macro block, then 4 row data of remaining 12 row and request next time are integrated with the correspondence position of last macro-block line;
3) this two field picture initial address in sheet external memory is calculated;
4) address carrying out off-chip DDR2SDRAM storage chip maps:
4.1) in DDR2SDRAM memorizer, judge that signal distinguishes top field, field, the end according to field, the end, top, then by the brightness data of this two field picture according to one-dimensional mode Coutinuous store, top therein field data is placed on the first half in the luminance frame space by the initial address of this two field picture, and end field data is placed on the latter half in the luminance frame space that 1/2nd of this frame space highly corresponding addresses are risen;
4.2) in DDR2SDRAM memorizer, judge that signal distinguishes top field, field, the end according to field, the end, top, then by the chroma data of this two field picture according to one-dimensional mode Coutinuous store, top therein field data is placed on the first half in the chrominance frames space that the initial address striding across this frame brightness space rises, and end field data is placed on the latter half in the chrominance frames space that 1/2nd of chrominance frames space highly corresponding addresses are risen; Height is chrominance frames space two times of described luminance frame space;
4.3) calculation code core maps new_addr to the address of DDR2 controller, new_addr is mapped to the DDR2SDRAM physical address identified, then the reconstruct data of DBF module are continuously written in DDR2SDRAM storage chip according to the order of " top field brightness-end field brightness-field, top colourity-field, end colourity " successively;
Described calculation code core maps new_addr such as following formula to the address of DDR2 controller:
Mc_width_mbs × mb_rows_cnt ÷ 32+wxloc ÷ 2 × 32+ (new_yloc × 2-mb_rows_cnt × 32);
Mc_width_mbs: the picture traverse in units of macro block;
Mb_rows_cnt: macro-block line counts;
Wxloc: the abscissa of each macro block in units of pixel;
New_yloc: the vertical coordinate of each macro block in units of pixel.
2. the method for raising block-eliminating effect filtering Restructuring Module data rate memory according to claim 1, it is characterised in that:
Concretely comprising the following steps of the block-eliminating effect filtering data continuously linear write buffer memory of the two field picture that coding core is sent by described step 1:
Each macro block is sequentially written in from left to right by macro-block line, then writes the data of next macro-block line, till all data of last macro-block line all run through from coding core.
3. the method for raising block-eliminating effect filtering Restructuring Module data rate memory according to claim 1 and 2, it is characterised in that:
Described step 3 calculates this two field picture the concretely comprising the following steps of initial address in sheet external memory:
When new request arrives, DBF module distinguishes reconstruct data and down-sampled data, for reconstruct data, and present frame address that DBF module provides according to firmware and the two-dimensional coordinate of this operation, calculate this module and be mapped to the initial address of DDR2 controller input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510930646.4A CN105681815B (en) | 2015-12-12 | 2015-12-12 | The method for improving block-eliminating effect filtering Restructuring Module data rate memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510930646.4A CN105681815B (en) | 2015-12-12 | 2015-12-12 | The method for improving block-eliminating effect filtering Restructuring Module data rate memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105681815A true CN105681815A (en) | 2016-06-15 |
| CN105681815B CN105681815B (en) | 2018-12-25 |
Family
ID=56189568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510930646.4A Active CN105681815B (en) | 2015-12-12 | 2015-12-12 | The method for improving block-eliminating effect filtering Restructuring Module data rate memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105681815B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107026999A (en) * | 2016-08-04 | 2017-08-08 | 成都小娱网络科技有限公司 | Compression method is cached outside a kind of piece for ultra high-definition processing system for video |
| CN108024033A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of video image transtation mission circuit based on ARINC818 agreements |
| CN108614667A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frames power on automatic loaded circuit and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1878307A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Method for improving SDRAM bus efficiency in video decoder |
| CN101009840A (en) * | 2006-01-24 | 2007-08-01 | 扬智科技股份有限公司 | Method for decoding and displaying a video stream |
| CN101389033A (en) * | 2008-10-30 | 2009-03-18 | 四川长虹电器股份有限公司 | Decoder buffer control method under frame field adaptive decoding schema |
| EP2824925A1 (en) * | 2013-07-11 | 2015-01-14 | Nxp B.V. | Video decoding with reduced-complexity deblocking |
-
2015
- 2015-12-12 CN CN201510930646.4A patent/CN105681815B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101009840A (en) * | 2006-01-24 | 2007-08-01 | 扬智科技股份有限公司 | Method for decoding and displaying a video stream |
| CN1878307A (en) * | 2006-07-14 | 2006-12-13 | 杭州国芯科技有限公司 | Method for improving SDRAM bus efficiency in video decoder |
| CN101389033A (en) * | 2008-10-30 | 2009-03-18 | 四川长虹电器股份有限公司 | Decoder buffer control method under frame field adaptive decoding schema |
| EP2824925A1 (en) * | 2013-07-11 | 2015-01-14 | Nxp B.V. | Video decoding with reduced-complexity deblocking |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107026999A (en) * | 2016-08-04 | 2017-08-08 | 成都小娱网络科技有限公司 | Compression method is cached outside a kind of piece for ultra high-definition processing system for video |
| CN108614667A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frames power on automatic loaded circuit and method |
| CN108614667B (en) * | 2016-12-12 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frame power-on automatic loading circuit and method |
| CN108024033A (en) * | 2017-11-24 | 2018-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of video image transtation mission circuit based on ARINC818 agreements |
| CN108024033B (en) * | 2017-11-24 | 2020-06-09 | 中国航空工业集团公司西安航空计算技术研究所 | Video image sending circuit based on ARINC818 protocol |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105681815B (en) | 2018-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20100073029A (en) | Apparatus for image processing and method for managing frame memory in image processing | |
| CN105681815A (en) | Method for increasing storage speed of reconstruction data of de-blocking filter module | |
| JP2001022638A (en) | Information processing system | |
| CN108346131A (en) | A kind of digital image scaling method, device and display equipment | |
| JP6210743B2 (en) | Data processing device and data transfer control device | |
| CN102804150B (en) | Data processing device, data processing method and data sharing system | |
| KR101615466B1 (en) | Capturing multiple video channels for video analytics and encoding | |
| CN100356780C (en) | Image storing method for compressing video frequency signal decode | |
| CN102055976A (en) | Memory access control device and method thereof | |
| US9129344B2 (en) | Method and system for padding in a video processing system | |
| TWI517695B (en) | On die/off die memory management | |
| CN101729903B (en) | Method, system and multimedia processor for reading reference frame data | |
| CN103957419A (en) | Video decoder of dual-buffer-memory structure and control method | |
| US8581918B2 (en) | Method and system for efficiently organizing data in memory | |
| CN100444636C (en) | A Method of Improving SDRAM Bus Efficiency in Video Decoder | |
| CN110232657A (en) | A kind of image-scaling method, device, equipment and medium | |
| US20140009478A1 (en) | Image processing apparatus and control method | |
| US12375700B2 (en) | Video decoding and display system and memory accessing method thereof | |
| CN104954798B (en) | The straight-through display methods of video decoding and device | |
| US9372817B2 (en) | High perfomance DMA controller for video processors | |
| JP6210742B2 (en) | Data processing device and data transfer control device | |
| CN100403276C (en) | Memory access method | |
| CN101483743B (en) | A data access device and method | |
| CN104469228A (en) | 2D or multi-viewpoint naked eye 3D video data storing and reading-writing method | |
| JP2008299438A (en) | Memory controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |