CN106209066B - Method and chip for multiplexing chip pins - Google Patents

Abstract

The invention discloses a method for multiplexing chip pins and a chip, which allows any pin of the chip to be grounded through an external resistor, and controls the voltage of the pin to a fixed voltage or sets a fixed current to flow to the lead when the chip is started. Pin, by collecting the current flowing through the pin or the pin voltage and converting it, and then latching the converted output signal; so that the output signal has multiple or multiple forms under different off-chip resistances , so as to set various working states of the chip based on the output signal. The present invention uses the existing drive pins to set the working state of the chip through peripheral resistors without increasing the pins of the chip, so that the use of the chip is more convenient and flexible, and the cost of production and use is reduced.

Description

Method and chip for multiplexing chip pins

technical field

The invention belongs to the technical field of electronic chip design, and in particular relates to a chip pin multiplexing method and chip.

Background technique

At present, the testing of integrated circuit chips is usually carried out after the chips are put out. Due to the high integration and high complexity of the chip, not only the output signal of the chip needs to be tested, but also individual internal function signals need to be tested, so the testability of the chip is very important. In a traditional test, a test PAD or a pin of the chip is usually added inside the chip to check the correctness of the internal function signal.

For the same type of chip, it is often necessary to adjust the parameters of the chip and set different working states of the chip. For example, some chips have a reference voltage of 600mV, and another chip of the same series has a reference voltage of 1.2V, while other performance parameters are the same. Generally, two different chips need to be produced for two different occasions. In order to facilitate the use and reduce the cost, some chips add an additional setting pin. By setting the pin, the chip can be set to work in different states. Production of different chips will inevitably increase the production cost; however, if an additional setting pin is added to the chip, the area of the chip will increase a lot, and the packaging cost will increase, and the system cost will also increase accordingly.

With the development of integrated circuits, not only IC chips are required to be measurable, but also the test plan is required to save the chip area as much as possible, so as to save chip costs, thereby increasing product profits. The secondary casting provides convenience; so this becomes the direction that the applicant is committed to researching.

Contents of the invention

Based on the above, the present invention provides a chip pin multiplexing method and chip, without increasing the number of chip pins, using the existing pins to set the working state of the chip through peripheral resistors, so that the use of the chip is more convenient Flexible and reduces production and usage costs.

A chip pin multiplexing method, first ground any pin of the chip through an external resistor, when the chip is started, control the voltage of the pin to a fixed voltage or set a fixed current to flow to the pin, through the collection of The current of the pin or the voltage of the pin is converted, and then the converted output signal is latched; so that under different off-chip resistances, the working state of the chip is set according to the output signal.

Further, when the voltage of the control pin is a fixed voltage, the current flowing through the pin is collected and converted; when the fixed current is set to flow to the pin, the voltage of the pin is collected and converted .

Further, after the latching is completed, the fixed voltage control or fixed current setting of the pin is cancelled, so as not to affect the external device on the pin.

A pin multiplexing chip includes a pin multiplexing circuit; for any pin of the chip, the pin multiplexing circuit is connected with the pin and an external resistor, and the other end of the external resistor is Grounding; the pin multiplexing circuit includes a switch, a pin control module, a signal acquisition conversion module and a latch module; wherein:

The pin control module is connected to the pin through a switch, and is used to control the voltage of the pin to be a fixed voltage or set a fixed current to flow to the pin;

The signal collection and conversion module is used to collect and convert the current flowing through the pin or the voltage of the pin, so as to generate multiple or multiple forms of output signals;

The latch module is used to latch the output signal;

The switch is turned on when the chip is started, and turned off after the latch module completes latching.

Further, when the pin control module is used to control the pin voltage to be a fixed voltage, the signal acquisition conversion module is used to collect the current flowing through the pin and convert it; when the pin control module is used to set a fixed When the current flows to the pin, the signal acquisition and conversion module is used to acquire the voltage of the pin and convert it.

Further, when the pin control module is used to control the pin voltage to be a fixed voltage, it uses an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the fixed voltage, and the inverting input terminal of the operational amplifier and the output The terminals are connected together and connected to one end of the switch, and the other end of the switch is connected to this pin.

Further, when the pin control module is used to set a fixed current to flow to the pin, it adopts a current source, the current output by the current source is equal to the fixed current, the input terminal is connected to the power supply voltage, and the output terminal Connect to one end of the switch, and connect the other end of the switch to this pin.

Further, the described signal acquisition conversion module adopts an A/D conversion circuit, and the A/D conversion circuit has an N-bit conversion function, and its input terminal collects the current or the pin voltage flowing through the pin, and the output terminal generates 2 ^N channels The output signal of , N is a natural number greater than 0.

Furthermore, when the signal acquisition and conversion module is used to acquire and convert the current flowing through the pin, it consists of a fixed current source and a controlled current source, and the output current of the controlled current source is controlled by Controlling the current flowing through the pin, its input terminal is connected to the power supply voltage, and its output terminal is connected to the input terminal of the fixed current source to generate the output signal; the output current of the fixed current source is fixed, and its output terminal is grounded.

Further, the latch module adopts a D flip-flop or a multi-way latch.

The above-mentioned pins are switching tube drive pins.

A switch circuit includes a switch tube and a control chip thereof, and the control chip adopts the above-mentioned pin multiplexing chip.

Based on the above technical solution, the present invention uses the existing drive pins to set the working state of the chip through peripheral resistors without increasing the number of chip pins, making the use of the chip more convenient and flexible, and reducing production and use costs.

Description of drawings

FIG. 1 is a schematic structural diagram of a first embodiment of a pin multiplexing chip of the present invention.

FIG. 2 is a schematic structural diagram of a second embodiment of the pin multiplexing chip of the present invention.

FIG. 3 is a schematic structural diagram of a third embodiment of the pin multiplexing chip of the present invention.

Detailed ways

In order to describe the present invention more specifically, the technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

As shown in Figure 1, the pin multiplexing chip of this embodiment includes a pin multiplexing circuit and a control driving circuit U00; The other end of the off-chip resistor R10 is grounded; the control drive circuit U00 is used to provide switch control signals for the off-chip switch tube M00 through the drive pin GATE, and the drive pin GATE is also connected to the gate of the switch tube M00 and a chip The external capacitor C00 is connected, wherein C00 may be an external capacitor or a parasitic capacitance of the switching tube M00; the source of the switching tube M00 and the other end of the off-chip capacitor C00 are both grounded.

The pin multiplexing circuit in this embodiment includes a switch K10, an operational amplifier U10, a controlled current source I11, a fixed current source I12, and a D flip-flop U11; wherein: the non-inverting input terminal of the operational amplifier U10 is connected to a fixed voltage VREF, and the operational amplifier The inverting input terminal and output terminal of U10 are connected with one end of switch K10, so the output voltage of operational amplifier U10 is also VREF, and the other end of switch K10 is connected with drive pin GATE; the input terminal of controlled current source I11 is connected with power supply voltage VD, the current i10 flowing from the multiplexing circuit of the control terminal acquisition pin to the drive pin GATE, the output terminal is connected to the input terminal of the fixed current source I12 and the input terminal of the D flip-flop U11, the output terminal of the fixed current source I12 is grounded, D The clock terminal CLK of the flip-flop U11 receives the pulse signal.

When starting, the switch K10 is turned on, and the control drive circuit U00 does not pull up or pull down the switch tube M00, then the voltage on the drive pin GATE is VREF, and the fixed voltage VREF is lower than the threshold voltage of the switch tube M00, ensuring that the switch tube M00 is off. In order to ensure that the gate of the switch tube M00 is pulled down by the resistor when the chip is powered off, an on-chip resistor R00 can be added between the drive pin GATE and the ground, so as to ensure that the switch tube M00 is in the off state, making the system safe and reliable. Since in this embodiment, an off-chip resistor R10 has been added between the drive pin GATE and the ground, the on-chip resistor R00 can be added or not.

When the on-chip resistor R00 is added, the magnitude of the current i10 flowing from the pin multiplexing circuit to the drive pin GATE is VREF/(R10+R00). Among them, since the size of the on-chip resistor R00 is fixed for each chip, the size of the current i10 is only related to the off-chip resistor R10. When the on-chip resistor R00 is not added, i10=VREF/R10.

The controlled current source I11 is connected in series with the fixed current source I12, wherein the controlled current source I11 is a current controlled current source, and its output current is controlled by the current i10, and the fixed current source I12 is a fixed current output. When the output current of the controlled current source I11 is greater than the fixed current source I12, the voltage V1 at the connection point between the controlled current source I11 and the fixed current source I12 is pulled up by the controlled current source I11, that is, the voltage V1 is high; When the output current of the current source I11 is smaller than the fixed current source I12, the voltage V1 at the connection point between the controlled current source I11 and the fixed current source I12 is pulled down by the fixed current source I12, that is, the voltage V1 is low. The voltage V1 is connected to the digital input D of the D flip-flop. After the voltage of the driving pin GATE is stabilized at VREF, the voltage V1 is also stabilized at high level or low level. The pulse signal is input to the clock terminal CLK of the D flip-flop, and the output terminal OUT of the D flip-flop latches the voltage of the digital input terminal when the output CLK is high. After the latching of the D flip-flop is completed, the switch K10 is turned off, the pin multiplexing circuit does not affect the switch tube M00, and the setting of the circuit is completed.

The output terminal OUT of the D flip-flop keeps latching the high-level or low-level voltage, and two working states of the chip can be set. After the chip configuration is completed, the driving circuit U00 is controlled to control the switching action of the switching tube M00.

This embodiment provides the setting method of two working states, plus a controlled current source, a fixed current source and a D flip-flop, four working states can be set, and so on.

Example 2

As shown in Figure 2, the pin multiplexing chip of this embodiment includes a pin multiplexing circuit and a control driving circuit U00; The other end of the off-chip resistor R10 is grounded; the control drive circuit U00 is used to provide switch control signals for the off-chip switch tube M00 through the drive pin GATE, and the drive pin GATE is also connected to the gate of the switch tube M00 and a chip The external capacitor C00 is connected, and the source of the switch tube M00 and the other end of the off-chip capacitor C00 are both grounded.

The pin multiplexing circuit in this embodiment includes a switch K10, an operational amplifier U10, an A/D conversion circuit U20, and a latch U21; wherein: the non-inverting input terminal of the operational amplifier U10 is connected to a fixed voltage VREF, and the inverting input terminal of the operational amplifier U10 The input end and output end are connected to one end of the switch K10, so the output voltage of the operational amplifier U10 is also VREF, and the other end of the switch K10 is connected to the driving pin GATE; the input end of the A/D conversion circuit U20 is connected to the driving pin GATE It is used to collect the current i10 flowing from the pin multiplexing circuit to the drive pin GATE, the output terminal is connected to the input terminal of the latch U21, and the clock terminal CLK of the latch U21 receives the pulse signal.

When starting, the switch K10 is turned on, and the control drive circuit U00 does not pull up or pull down the switch tube M00, then the voltage on the drive pin GATE is VREF, and the fixed voltage VREF is lower than the threshold voltage of the switch tube M00, ensuring that the switch tube M00 It is in an off state; the current i10 flowing from the pin multiplexing circuit to the driving pin GATE is VREF/R10.

The sampled current i10 enters the A/D conversion circuit U20 to convert the analog current signal into a digital signal. The A/D conversion circuit U20 connects its output to the digital input terminal D of the latch U21. After the voltage of the driving pin GATE is stabilized at VREF, the magnitude of the current i10 is also stable. The pulse signal is input to the clock terminal CLK of the latch U21, and the output terminal OUT of the latch U21 latches the voltage of the digital input terminal when the output CLK is high. After the latching of the latch U21 is completed, the switch K10 is turned off, the pin multiplexing circuit does not affect the switch tube M00, and the setting of the chip is completed. Wherein, the A/D conversion circuit U20 may be an N-bit conversion circuit, and its output signal has 2 ^N channels, and the input and output of the latch U21 each have 2 ^N channels of signals, and 2 ^N working states can be set.

Example 3

As shown in Figure 3, the pin multiplexing chip of this embodiment includes a pin multiplexing circuit and a control driving circuit U00; The other end of the off-chip resistor R10 is grounded; the control drive circuit U00 is used to provide switch control signals for the off-chip switch tube M00 through the drive pin GATE, and the drive pin GATE is also connected to the gate of the switch tube M00 and a chip The external capacitor C00 is connected, and the source of the switch tube M00 and the other end of the off-chip capacitor C00 are both grounded.

The pin multiplexing circuit in this embodiment includes a switch K10, a fixed current source I30, a clamp circuit U30, an A/D conversion circuit U20, and a latch U21; wherein: the input terminal of the fixed current source I30 is connected to the power supply voltage VD, The output end is connected to one end of the switch K10, and the other end of the switch K10 is connected to the drive pin GATE; the clamping circuit U30 is connected between the output end of the fixed current source I30 and the ground, and the input end of the A/D conversion circuit U20 is connected to the fixed The output terminal of the current source I30 is connected to collect the voltage of the drive pin GATE, the output terminal is connected to the input terminal of the latch U21, and the clock terminal CLK of the latch U21 receives the pulse signal.

When starting, the switch K10 is turned on, and the control drive circuit U00 does not pull up or pull down the switch tube M00, the current i30 output by the fixed current source I30 is fixed, and the voltage on the driving pin GATE is i30*R10; the current i30 is from the fixed The output terminal of the current source I30 flows to the drive pin GATE, and the clamping circuit U30 is connected in parallel with the drive pin GATE through the switch K10, and its clamping voltage is lower than the turn-on threshold voltage of the switch tube M00, so as to prevent the switch Tube M00 is incorrectly turned on. The off-chip resistor R10 cannot be too large, otherwise i30*R10 is greater than the clamping voltage of the clamping circuit U30, and the clamping circuit U30 will clamp the voltage of the driving pin GATE.

The voltage of the driving pin GATE is obtained by sampling, and enters the A/D conversion circuit U20 to convert the analog voltage signal into a digital signal. The A/D conversion circuit U20 connects its output to the digital input terminal D of the latch U21. After the voltage of the driving pin GATE is stabilized, the pulse signal is input to the clock terminal CLK of the latch U21, and the output terminal OUT of the latch U21 latches and outputs the voltage of the digital input terminal when CLK is high. After the latching of the latch U21 is completed, the switch K10 is turned off, the pin multiplexing circuit does not affect the switch tube M00, and the setting of the chip is completed. Wherein, the A/D conversion circuit U20 may be an N-bit conversion circuit, and its output signal has 2 ^N channels, and the input and output of the latch U21 each have 2 ^N channels of signals, and 2 ^N working states can be set.

The above description of the embodiments is for those of ordinary skill in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to the above-mentioned embodiments, and apply the general principles described here to other embodiments without creative efforts. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art according to the disclosure of the present invention should fall within the protection scope of the present invention.

Claims (6)

1. a pin multiplexing chip, is characterized in that: comprise pin multiplexing circuit; For any pin of this chip, described pin multiplexing circuit is connected in total with this pin and an external resistance, The other end of the off-chip resistor is then grounded; the pin multiplexing circuit includes a switch, a pin control module, a signal acquisition conversion module and a latch module; wherein: The pin control module is connected to the pin through a switch, and is used to control the voltage of the pin to be a fixed voltage or set a fixed current to flow to the pin; The signal collection and conversion module is used to collect and convert the current flowing through the pin or the voltage of the pin, so as to generate multiple or multiple forms of output signals; The latch module is used to latch the output signal; The switch is turned on when the chip is started, and turned off after the latch module completes latching; When the pin control module is used to control the pin voltage to be a fixed voltage, the signal acquisition conversion module is used to collect the current flowing through the pin and convert it; when the pin control module is used to set the fixed current flow to the pin In the case of the pin, the signal acquisition conversion module is used to acquire the pin voltage and convert it; When the pin control module is used to control the pin voltage to be a fixed voltage, it adopts an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the fixed voltage, and the inverting input terminal and output terminal of the operational amplifier are connected together. And connected to one end of the switch, the other end of the switch is connected to this pin; When the pin control module is used to set the fixed current to flow to the pin, it adopts a current source whose output current is equal to the fixed current, the input terminal is connected to the power supply voltage, and the output terminal is connected to the switch. One end of the switch is connected to this pin. 2. chip according to claim 1, it is characterized in that: described signal acquisition conversion module adopts A/D conversion circuit, and this A/D conversion circuit has N-bit conversion function, and its input terminal collection flows through pin Current or pin voltage, the output terminal generates 2 ^N output signals, where N is a natural number greater than 0. 3. The chip according to claim 1, characterized in that: when the signal acquisition conversion module is used to collect the current flowing through the pin and convert it, it consists of a fixed current source and a controlled current source Composition, the current output by the controlled current source is controlled by the current flowing through the pin, its input terminal is connected to the power supply voltage, and the output terminal is connected to the input terminal of the fixed current source to generate the output signal; the fixed current source The magnitude of the outputted current is fixed, and its output end is grounded. 4. The chip according to claim 1, wherein the latch module adopts a D flip-flop or a multi-way latch. 5. The chip according to claim 1, wherein the pin is a drive pin of a switch tube. 6. A switch circuit, comprising a switch tube and its control chip, characterized in that the control chip is the chip according to any one of claims 1-5.

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