CN110970501A - Semiconductor power device - Google Patents
Semiconductor power device Download PDFInfo
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- CN110970501A CN110970501A CN201811147319.1A CN201811147319A CN110970501A CN 110970501 A CN110970501 A CN 110970501A CN 201811147319 A CN201811147319 A CN 201811147319A CN 110970501 A CN110970501 A CN 110970501A
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- Prior art keywords
- gate
- source
- semiconductor substrate
- power device
- body region
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 210000000746 body region Anatomy 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 description 48
- 239000011229 interlayer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
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- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of semiconductor power devices, and particularly discloses a semiconductor power device, which comprises: a semiconductor substrate; at least one gate trench in the semiconductor substrate; the gate dielectric layer, the first control gate, the second control gate, the isolation dielectric layer and the shielding gate are positioned in the gate trench; a body region located in the semiconductor substrate and adjacent to one side of the first control gate; a source region located in the body region; and the source contact hole is positioned above the body region, the source contact hole extends to the position above the grid groove, and the body region, the source region, the first control grid and the shielding grid are externally connected with source voltage through a source metal layer in the source contact hole. The invention can reduce the space between adjacent gate trenches in the semiconductor power device, thereby improving the doping concentration of the semiconductor substrate and reducing the on-resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor power device capable of reducing the space between adjacent gate trenches.
Background
Fig. 1 is a schematic cross-sectional view of a semiconductor power device of the prior art, and as shown in fig. 1, the semiconductor power device of the prior art includes: the semiconductor device comprises an n-type semiconductor substrate 100, an n-type drain region 10 located at the bottom of the n-type semiconductor substrate 100, an n-type drift region 11 located in the n-type semiconductor substrate 100 and located above the n-type drain region 10, a plurality of gate trenches located in the n-type semiconductor substrate 100, a p-type body region 16 located between the adjacent gate trenches, an n-type source region 17 located in the p-type body region 16, a gate dielectric layer 12, a control gate 13, an isolation dielectric layer 14 and a shielding gate 15 located in the gate trenches, wherein the control gate 13 is usually located at the position of the side wall of the upper portion of the gate trenches and controls the opening and closing of a current channel between the n-type source region 17 and the n-type drift region 11 through external gate voltage. The shielding grid 15 is located in the grid groove and is isolated from the n-type semiconductor substrate 100 and the control grid 13 through the isolation dielectric layer 14, the shielding grid 15 is connected with the n-type source region 17 through the source metal layer 19, and therefore the shielding grid 15 can form a transverse electric field in the n-type drift region 11 through external source voltage, and the effect of improving withstand voltage is achieved. The interlayer insulating layer 18 serves to isolate the source metal layer 19 from a gate metal layer, which is not shown in fig. 1, based on the positional relationship of the cross-section.
In the semiconductor power device shown in fig. 1 in the prior art, the source metal layer 19 is in contact with the n-type source region 17 and the p-type body region 16 at the middle position of the p-type body region 16, usually, the source metal layer 19 is embedded into the p-type body region 16, the n-type source region 17 is arranged on both sides of the source metal layer 19 in the p-type body region 16, and the distance between adjacent gate trenches is difficult to reduce due to the limitation of etching process conditions.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor power device, so as to solve the problem in the prior art that the pitch between adjacent gate trenches is difficult to shrink.
To achieve the above object of the present invention, the present invention provides a semiconductor power device comprising:
a semiconductor substrate;
the drain region is positioned at the bottom of the semiconductor substrate;
at least one gate trench in the semiconductor substrate;
the first control gate and the second control gate are respectively positioned on the side walls of the two sides of the upper part of the gate trench and are respectively isolated from the semiconductor substrate through gate dielectric layers;
the shielding gate is positioned in the gate trench and is isolated from the semiconductor substrate, the first control gate and the second control gate through an isolation dielectric layer;
a body region located in the semiconductor substrate and adjacent to one side of the first control gate;
a source region located in the body region;
a source contact hole located above the body region, the source contact hole extending above the gate trench, the body region, the source region, the first control gate and the shield gate all externally connected with a source voltage through a source metal layer in the source contact hole;
the second control grid is externally connected with grid voltage.
Optionally, in the semiconductor power device of the present invention, the body regions and the gate trenches are alternately arranged at intervals in sequence.
Optionally, in the semiconductor power device of the present invention, the source metal layer is embedded in the body region.
Optionally, in the semiconductor power device of the present invention, the thickness of the isolation dielectric layer between the shielding gate and the semiconductor substrate is greater than or equal to the thickness of the isolation dielectric layer between the shielding gate and the first and second control gates.
Optionally, in the semiconductor power device of the present invention, the semiconductor substrate, the drain region, and the source region are respectively doped in an n-type manner, and the body region is doped in a p-type manner.
Optionally, in the semiconductor power device of the present invention, the shielding gate and the isolation dielectric layer cover a lower portion of the gate trench and separate the first control gate and the second control gate at an upper portion of the gate trench.
The invention provides a semiconductor power device, which comprises: the source contact hole positioned above the body region extends to the position above the grid groove, so that the body region, the source region, the first control grid in the grid groove and the shielding grid can be connected with source voltage through the source metal layer in the source contact hole at the same time, the source region between the source metal layer and the first control grid can be prevented from being formed in the body region, and the source region between the source metal layer and the second control grid is only formed in the body region, so that the limitation of photoetching process conditions can be reduced, the distance between adjacent grid grooves can be further reduced, the doping concentration of a semiconductor substrate can be further improved, and the on-resistance of a semiconductor power device can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It should be clear that the described figures are only views of some of the embodiments of the invention to be described, not all, and that for a person skilled in the art, other figures can be derived from these figures without inventive effort.
FIG. 1 is a schematic cross-sectional view of one embodiment of a semiconductor power device of the prior art;
fig. 2 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.
It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic diagrams listed in the drawings of the specification enlarge the thicknesses of the layers and regions of the present invention, and the sizes of the listed figures do not represent actual sizes; the drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure. The examples listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the resulting shapes such as deviations due to production and the like.
Fig. 2 is a schematic cross-sectional structure diagram of an embodiment of a semiconductor power device provided in the present invention. As shown in fig. 2, a semiconductor power device provided by the embodiment of the present invention includes an n-type semiconductor substrate 200, and the material of the n-type semiconductor substrate 200 is typically silicon. And an n-type drain region 20 located at the bottom of the n-type semiconductor substrate 200.
At least one gate trench 201 in the n-type semiconductor substrate 200, 6 gate trenches 201 are exemplarily shown in the embodiment of the present invention. A gate dielectric layer 22, a first control gate 33, a second control gate 23, an isolation dielectric layer 24 and a shield gate 25 in each gate trench 201. The first control gate 33 and the second control gate 23 are respectively located at two side wall positions of the upper portion of the gate trench 201, and the first control gate 33 and the second control gate 23 are respectively isolated from the n-type semiconductor substrate 200 through the gate dielectric layer 22. The shield gate 25 is isolated from the n-type semiconductor substrate 200, the first control gate 33 and the second control gate 23 by an isolation dielectric layer 24, and preferably, the shield gate 25 and the isolation dielectric layer 24 cover a lower portion of the gate trench 201 and separate the first control gate 33 and the second control gate 23 at an upper portion of the gate trench 201, as shown in fig. 2.
The thickness of the isolation dielectric layer 24 between the shielding gate 25 and the n-type semiconductor substrate 200 may be the same as the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the first and second control gates 33 and 23, or may be greater than the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the first and second control gates 33 and 23, and fig. 2 only exemplarily shows a structure in which the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the n-type semiconductor substrate 200 is the same as the thickness of the isolation dielectric layer 24 between the shielding gate 25 and the first and second control gates 33 and 23.
Typically, the gate dielectric layer 22 and the isolation dielectric layer 24 are made of silicon oxide, and the first control gate 33, the second control gate 23 and the shielding gate 25 are made of doped polysilicon.
When a plurality of p-type body regions 26 and a plurality of gate trenches 201 are disposed in the p-type body region 26 located in the n-type semiconductor substrate 200 and close to the first control gate 33, the plurality of p-type body regions 26 and the plurality of gate trenches 201 should be alternately arranged at intervals in sequence, as shown in fig. 2. An n-type source region 27 located in the p-type body region 26. The portion of the n-type semiconductor substrate located between p-type body region 26 and n-type drain region 20 is an n-type drift region 21 of the semiconductor power device.
One source contact hole 203 formed in the interlayer insulating layer 28 over the p-type body region 26, the source contact hole 203 extending to above the gate trench 201, so that the p-type body region 26, the n-type source region 27, the first control gate 33 and the shield gate 25 are all externally connected to a source voltage through the source metal layer 29 in the source contact hole 203.
In fig. 2, the source metal layer 29 is embedded into the p-type body region 26, and thus the n-type source region 27 should be located in the p-type body region 26 between the source metal layer 29 and the first control gate 33. Alternatively, the source metal layer 29 may not be embedded in the p-type body region 26, but a contact region with a high doping concentration is formed in the p-type body region, and the source metal layer is in contact connection with the p-type body region through the contact region with a high doping concentration.
The second control gate 23 is externally connected to a gate voltage through the gate metal layer, and the second control gate 23 controls on and off of a current channel between the n-type source region 27 and the n-type drift region 21 through the gate voltage. Based on the position relationship of the cross section, the specific structure of the gate metal layer is not shown in fig. 2. The interlayer insulating layer 28 is used to isolate the source metal layer 29 from the gate metal layer, and the material of the interlayer insulating layer 28 is usually silicon glass, borophosphosilicate glass or phosphosilicate glass.
In a semiconductor power device according to the present invention as shown in fig. 2, a source contact hole 203 over p-type body region 26 extends over gate trench 201, so that the p-type body region 26, the n-type source region 27, the first control gate 33 and the shield gate 25 can simultaneously externally connect a source voltage through the source metal layer 29 in the source contact hole 203, it is possible to avoid the formation of an n-type source region between the source metal layer 29 and the first control gate 33 in the p-type body region 26, while only n-type source regions 27 between the second control gate 23 and the source metal layer 29 are formed within the p-type body region 26, this can reduce the limitation of the photolithography process conditions, can further reduce the pitch between the adjacent gate trenches 201, further, the doping concentration of the n-type semiconductor substrate 200 can be increased under the same operating voltage condition, and the on-resistance of the semiconductor power device can be reduced.
The above embodiments and examples are specific supports for the technical idea of the semiconductor power device proposed by the present invention, and the protection scope of the present invention is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme proposed by the present invention still belong to the protection scope of the technical scheme of the present invention.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (6)
1. A semiconductor power device, comprising:
a semiconductor substrate;
the drain region is positioned at the bottom of the semiconductor substrate;
at least one gate trench in the semiconductor substrate;
the first control gate and the second control gate are respectively positioned on the side walls of the two sides of the upper part of the gate trench and are respectively isolated from the semiconductor substrate through gate dielectric layers;
the shielding gate is positioned in the gate trench and is isolated from the semiconductor substrate, the first control gate and the second control gate through an isolation dielectric layer;
a body region located in the semiconductor substrate and adjacent to one side of the first control gate;
a source region located in the body region;
a source contact hole located above the body region, the source contact hole extending above the gate trench, the body region, the source region, the first control gate and the shield gate all externally connected with a source voltage through a source metal layer in the source contact hole;
the second control grid is externally connected with grid voltage.
2. The semiconductor power device according to claim 1, wherein said body regions and said gate trenches are alternately arranged in sequence at intervals.
3. A semiconductor power device according to claim 1, wherein said source metal layer is embedded in said body region.
4. The semiconductor power device according to claim 1, wherein a thickness of the isolation dielectric layer between the shield gate and the semiconductor substrate is greater than or equal to a thickness of the isolation dielectric layer between the shield gate and the first and second control gates.
5. The semiconductor power device according to claim 1, wherein the semiconductor substrate, the drain region and the source region are each doped n-type and the body region is doped p-type.
6. A semiconductor power device according to claim 1, wherein said shield gate and said isolation dielectric layer cover a lower portion of said gate trench and separate said first control gate and said second control gate at an upper portion of said gate trench.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811147319.1A CN110970501A (en) | 2018-09-29 | 2018-09-29 | Semiconductor power device |
| PCT/CN2019/108739 WO2020063918A1 (en) | 2018-09-29 | 2019-09-27 | Semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811147319.1A CN110970501A (en) | 2018-09-29 | 2018-09-29 | Semiconductor power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110970501A true CN110970501A (en) | 2020-04-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811147319.1A Pending CN110970501A (en) | 2018-09-29 | 2018-09-29 | Semiconductor power device |
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| Country | Link |
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| CN (1) | CN110970501A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284210A1 (en) * | 2021-07-13 | 2023-01-19 | 苏州东微半导体股份有限公司 | Semiconductor power device and control method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090096019A1 (en) * | 2007-02-08 | 2009-04-16 | Dev Alok Girdhar | Mosgated power semiconductor device with source field electrode |
| CN107527948A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
-
2018
- 2018-09-29 CN CN201811147319.1A patent/CN110970501A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090096019A1 (en) * | 2007-02-08 | 2009-04-16 | Dev Alok Girdhar | Mosgated power semiconductor device with source field electrode |
| CN107527948A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023284210A1 (en) * | 2021-07-13 | 2023-01-19 | 苏州东微半导体股份有限公司 | Semiconductor power device and control method therefor |
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Application publication date: 20200407 |