CN112151365A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a plurality of channel laminated layers are sequentially formed on the substrate; forming a dummy gate structure crossing the channel stack; etching the channel lamination layers on two sides of the pseudo-gate structure, enabling the channel lamination layers to sequentially retract along the direction in which the top of the pseudo-gate structure points to the substrate, and enabling the rest channel lamination layers and the substrate to enclose a groove; forming a source drain doping layer in the groove; removing the dummy gate structure to form a gate opening exposing the channel lamination; removing the sacrificial layer in the channel lamination to form a through groove, wherein the through groove is surrounded by the adjacent channel layer and the source-drain doping layer, or is surrounded by the substrate, the channel layer adjacent to the substrate and the source-drain doping layer, and the through groove is communicated with the grid opening; forming an inner wall layer on the side wall of the source drain doping layer exposed from the through groove; and forming a gate structure in the gate opening and the through groove. The embodiment of the invention meets the requirement that the semiconductor structure can be applied to circuits with different working voltages.

Description

Semiconductor structure and method of forming the same

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing in the direction of higher component density and higher integration, and the development trend of semiconductor process nodes following Moore's Law is decreasing. As the most basic semiconductor device, transistors are widely used at present. Therefore, with the improvement of component density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors has to be continuously shortened.

The shortening of the transistor channel length has the benefit of increasing the die density of the chip, increasing the switching speed, etc. However, with the shortening of the channel length, the distance between the source and the drain of the transistor is also shortened, so the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, the so-called short-circuit leakage. Channel effects (short-channel effects, SCE) are more likely to occur, increasing the channel leakage current of the transistor.

Therefore, in order to better meet the requirements of device size scaling down, the semiconductor process gradually begins to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as gate-all-around (GAA) transistors . In a fully surrounding gate transistor, the gate surrounds the area where the channel is located. Compared with a planar transistor, the gate of a fully surrounding gate transistor has stronger control over the channel and can better suppress short-channel effects. .

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to satisfy the requirement that a transistor with a fully surrounding gate structure can be applied to circuits with different operating voltages.

In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate on which a plurality of channel stacks are sequentially formed, and each of the channel stacks includes a sacrificial layer and a a channel layer on the sacrificial layer; forming a dummy gate structure across the channel stack, the dummy gate structure covering part of the top and part of the sidewall of the channel stack; etching the dummy gate Channel stacks on both sides of the structure, so that the plurality of channel stacks are directed along the direction from the top of the dummy gate structure to the substrate, the ends of the channel layers are indented in sequence, and the remaining channels are forming a groove with the substrate; forming a source-drain doped layer in the groove; removing the dummy gate structure to form a gate opening exposing the channel stack; removing the channel stack A sacrificial layer in the layer to form a through groove, the through groove is surrounded by the adjacent channel layer and the source and drain doped layers, or, the through groove is formed by the substrate, the groove adjacent to the substrate The channel layer and the source-drain doped layer are surrounded, the through groove is communicated with the gate opening; an inner wall layer is formed on the sidewall of the source-drain doped layer exposed by the through groove; on the gate A gate structure is formed in the pole opening and the through groove formed with the inner wall layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; a channel structure layer, located on the substrate and spaced apart from the substrate, the channel structure layer including a plurality of channels spaced apart layer, and along the direction of the top of the channel structure layer pointing to the substrate, the ends of the channel layer are indented in turn; across the gate structure of the channel structure layer, the gate structure covering a portion of the top of the substrate and surrounding the channel layer, a gate structure between the substrate and the channel layer adjacent to the substrate, and a gate between adjacent channel layers The pole structure is the first part of the gate structure, and the remaining gate structure is the second part of the gate structure; the source-drain doping layer is located in the channel structure layer on both sides of the gate structure; the inner wall layer is located in the gate between the first part of the structure and the source and drain doped layers.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, the channel stacks on both sides of the dummy gate structure are etched, so that the plurality of channel stacks are directed along the direction from the top of the dummy gate structure to the substrate. The lengths of the channel layers are all different, so that after the gate all around (GAA) transistor is formed, each channel layer in the GAA transistor has different Therefore, when the device is operating, the effect of turning on different channel layers in the transistor can be achieved by applying voltages of different magnitudes to the transistor, so as to satisfy the application of the fully enclosed gate structure transistor to the transistor with requirements of circuits with different operating voltages; and, after removing the dummy gate structure and the sacrificial layer in the channel stack, the embodiment of the present invention further includes: on the side of the source-drain doped layer exposed by the through groove An inner wall layer is formed on the wall. After the gate structure is subsequently formed, the gate structure located in the through groove is used as the first part of the gate structure, and the inner wall layer is located between the first part of the gate structure and the source-drain doping layer. The distance between the first part of the gate structure and the source-drain doped layer is increased, which is beneficial to reduce the parasitic capacitance between the gate structure and the source-drain doped layer, thereby improving the semiconductor structure. and the inner wall layer is formed after removing the dummy gate structure and the sacrificial layer in the channel stack in the embodiment of the present invention, so that it can be formed on the sidewalls of the source and drain doped layers exposed by all the through grooves in the same step The inner wall layer is beneficial to simplify the process flow and the process steps are simple.

Description of drawings

1 is a schematic structural diagram of a semiconductor structure;

2 to 14 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

15 to 27 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

FIG. 28 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

Detailed ways

It is difficult for the transistors with the fully surrounding gate structure formed at present to be applied to circuits with different operating voltages. The reasons why it is difficult for transistors to be applied to circuits with different operating voltages are now combined with a semiconductor structure.

Referring to FIG. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure includes: a substrate 600; a channel structure layer 614, located on the substrate 600 and spaced apart from the substrate 600, the channel structure layer 614 includes a plurality of spaced apart channel layers 613; The gate structure 620 of the channel structure layer 614, the gate structure 620 covers part of the top of the substrate 600 and surrounds the channel layer 613; the source-drain doped layer 650 is located on the gate structure 620 Inside the channel structure layer 614 on both sides.

The semiconductor structure is a fully surrounding gate structure transistor. In the semiconductor structure, the width of the channel layer 613 is the same, and the turn-on voltage of each channel layer 613 in the semiconductor structure is also the same. During operation, the semiconductor structure can only be applied to circuits with a single operating voltage, or the semiconductor structure cannot be applied to different circuits with different operating voltages, which is difficult to apply to the semiconductor structure with different operating voltages. circuit requirements.

In order to solve the technical problem, in the embodiment of the present invention, the channel stacks on both sides of the dummy gate structure are etched, so that the plurality of channel stacks are directed along the direction from the top of the dummy gate structure to the substrate, The ends of the channel layers are indented in sequence, and the lengths of the channel layers are all different, so that after the fully surrounding gate structure transistor is formed, each channel layer in the fully surrounding gate structure transistor has a different value. Therefore, when the device is working, the effect of turning on different channel layers in the transistor can be achieved by applying voltages of different magnitudes to the transistor, so as to satisfy the application of the fully surrounded gate structure transistor to the transistor. requirements of circuits with different operating voltages; and, after removing the dummy gate structure and removing the sacrificial layer in the channel stack, the embodiments of the present invention further include: source-drain doping exposed in the through groove An inner wall layer is formed on the sidewall of the impurity layer. After the gate structure is subsequently formed, the gate structure located in the through groove is used as the first part of the gate structure, and the inner wall layer is located in the first part of the gate structure and the source and drain dopant. between the impurity layers, the distance between the first part of the gate structure and the source and drain impurity layers is increased, thereby helping to reduce the parasitic capacitance between the gate structure and the source and drain impurity layers, thereby improving the The performance of the semiconductor structure, and in the embodiment of the present invention, after removing the dummy gate structure and the sacrificial layer in the channel stack, the inner wall layer is formed, so that the source and drain doped layer sides exposed by all the through grooves can be formed in the same step. The inner wall layer is formed on the wall, which is beneficial to simplify the process flow and the process steps are simple.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 14 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIG. 2 , a substrate (not shown) is provided on which a plurality of channel stacks 114 are sequentially formed, and each of the channel stacks 114 includes a sacrificial layer 112 and a channel layer 113 on the sacrificial layer 112 .

The substrate provides a process platform for the subsequent formation of gate-all-around (GAA) transistors.

In this embodiment, the base is a three-dimensional structure, and the base includes the substrate 100 and the fins 110 protruding from the substrate 100 . In other embodiments, when the substrate is a planar structure, the substrate accordingly includes only the substrate.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator liner Bottom and other types of substrates.

The fins 110 expose a part of the substrate 100 to provide a process basis for the subsequent formation of the isolation structure.

In this embodiment, the material of the fins 110 and the substrate 100 is the same, and the material of the fins 110 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium and other semiconductor materials suitable for forming the fins, and the material of the fins may also be the same as the material of the substrate. different.

The channel stack 114 provides a process basis for the subsequent formation of the channel layer 113 provided with the suspended space. Specifically, the sacrificial layer 112 supports the channel layer 113, thereby providing a technological basis for the subsequent realization of the spaced suspension setting of the channel layer 113, and also occupying a space for the subsequent formation of the metal gate structure. The channel layer 113 is used to provide a fully enclosed gate channel of the transistor. In this embodiment, the channel stack 114 is formed on the fins 110 .

In this embodiment, the material of the channel layer 113 is Si, and the material of the sacrificial layer 112 is SiGe. In the subsequent process of removing the sacrificial layer 112, the etching selection of SiGe and Si is relatively high, so by setting the material of the sacrificial layer 112 to SiGe and the material of the channel layer 113 to Si, the sacrificial layer can be effectively reduced. The removal process of 112 affects the channel layer 113, thereby improving the quality of the channel layer 113, which is beneficial to improve device performance. In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology can be used, the material of the fin and the channel layer is SiGe, and the material of the sacrificial layer is Si.

In this embodiment, the number of channel stacks 114 is two, including a first channel stack 114a and a second channel stack 114b located on the first channel stack 114a. In other embodiments, according to actual process requirements, the number of channel stacks may be greater than or equal to three.

In this embodiment, the method for forming the semiconductor structure further includes: forming an isolation structure 111 on the substrate 100 where the trench stack 114 is exposed, and the isolation structure 111 exposes sidewalls of the trench stack 114 .

The isolation structures 111 are used to isolate adjacent devices or adjacent channel stacks 114 . In this embodiment, the material of the isolation structure 111 is silicon oxide. In other embodiments, the material of the isolation structure may also be other insulating materials such as silicon nitride or silicon oxynitride.

In this embodiment, the top surfaces of the isolation structures 111 are flush with the top surfaces of the fins 110, thereby preventing the fins 110 from being used as channels.

With continued reference to FIG. 2 , a dummy gate structure 130 is formed across the channel stack 114 , the dummy gate structure 130 covering a portion of the top and a portion of the sidewall of the channel stack 114 .

The dummy gate structure 130 occupies a space for the subsequent formation of the gate structure. In this embodiment, the dummy gate structure 130 includes a dummy gate layer 120, and the dummy gate layer 120 spans the channel stack 114 and covers part of the top and part of the sidewall of the channel stack 114.

In this embodiment, the material of the dummy gate layer 120 is polysilicon. In other embodiments, the material of the dummy gate layer may also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.

In this embodiment, the dummy gate structure 120 is a stacked structure. Before the dummy gate layer 120 is formed, it further includes: forming a gate oxide layer 121 (as shown in FIG. 2 ) conformally covering the surface of the channel stack 114 , the dummy gate layer 120 and the gate oxide layer 121 at the bottom of the dummy gate layer 120 are used to form the dummy gate structure 130 . In other embodiments, the dummy gate structure may also be a single-layer structure, and the dummy gate structure accordingly only includes a dummy gate layer.

In this embodiment, the material of the gate oxide layer 121 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

In this embodiment, a gate mask layer 123 is further formed on the top of the dummy gate layer 120 . The gate mask layer 123 is used as an etching mask when forming the dummy gate layer 120, and the gate mask layer 123 is also used to protect the dummy gate layer 120. In this embodiment, the material of the gate mask layer 123 is silicon nitride.

In this embodiment, after the dummy gate structure 130 is formed, the method further includes: forming a first spacer 122 on the sidewall of the dummy gate layer 120 . The first spacer 122 is used as an etching mask for the subsequent etching process to define the formation region of the subsequent source and drain doped layers, and the first spacer 122 is also used to protect the sidewall of the dummy gate layer 120.

The material of the first spacer 122 may be selected from silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride, and the first spacer 122 may be Single layer structure or stacked structure. In this embodiment, the first spacer 122 is a single-layer structure, and the material of the first spacer 122 is silicon oxide.

It should be noted that, after the first spacer 122 is formed, the gate oxide layer 121 exposed by the first spacer 122 and the dummy gate layer 120 is retained, and the gate oxide layer 121 can protect the channel stack 114 in subsequent processes. In other embodiments, the gate oxide layer exposed by the first sidewall spacer and the dummy gate layer may also be removed, and only the gate oxide layer covered by the dummy gate layer and the first sidewall spacer is retained, exposing the channel stack on both sides of the dummy gate layer, It is convenient to carry out subsequent process steps.

Referring to FIG. 3 to FIG. 8 , the channel stacks 114 on both sides of the dummy gate structure 130 are etched, so that the plurality of channel stacks 114 are directed along the direction from the top of the dummy gate structure 130 to the substrate, The ends of the channel layers 113 are indented in sequence, and the remaining channel stacks 114 and the substrate form a groove 150 (as shown in FIG. 8 ).

By orienting the plurality of channel stacks 114 along the direction from the top of the dummy gate structure 130 to the substrate, the ends of the channel layers 113 are indented in sequence, so that the lengths of the channel layers 113 are all different, so that the fully surrounding gate structure is formed. After the transistor, each channel layer 113 in the transistor has a different turn-on voltage, so that when the device is operating, the different channel layers 113 in the transistor can be turned on by applying voltages of different magnitudes to the transistor. Therefore, the requirement of applying the fully surrounded gate structure transistor to circuits with different operating voltages is satisfied.

The distance by which the end of the channel layer 113 is indented should not be too small or too large. If the distance by which the end of the channel layer 113 is retracted is too small, when the device is operating, the difference in the turn-on voltage of each channel layer 113 is also relatively small, and the difference in the turn-on voltage of different channel layers 113 is also small, which is difficult to achieve. Distinguish the effect of different turn-on voltages; if the indentation distance of the end of the channel layer 113 is too large, when the number of channel layers 113 is large, the width of the channel layer 113 close to the substrate is correspondingly too small, which is easy to increase the channel stack. The risk of layer collapse also easily affects the effective channel length of the device, which in turn affects the performance of the device. For this reason, in this embodiment, the distance by which the end of the channel layer 113 is indented on one side is greater than 0 nm and less than or equal to 5 nm.

In this embodiment, the number of the channel stacks 114 is two, and the steps of etching the channel stacks 114 on both sides of the dummy gate structure 130 include:

As shown in FIG. 3 , using the dummy gate structure 130 as a mask, the second channel stack 114b exposed by the dummy gate structure 130 (as shown in FIG. 2 ) is etched, and the remaining second channel stack 114b after etching As the top channel stack 114c; as shown in FIG. 4, a second spacer 115 is formed on the sidewall of the top channel stack 114c; as shown in FIG. 5, the first trench exposed by the second spacer 115 is etched The channel stack 114a (as shown in FIG. 4 ), the remaining first channel stack 114a after etching is used as the bottom channel stack 114d.

The second channel stack 114b exposed by the dummy gate structure 130 is etched to prepare for the formation of the second spacer 115 . Specifically, using the first spacer 122 and the dummy gate structure 130 as masks, the second channel stack 114b is etched.

In this embodiment, an anisotropic dry etching process is used to etch the second channel stack 114b exposed by the dummy gate structure 130 . By selecting the dry etching process, it is easy to achieve anisotropic etching, so that the second channel stack 114b exposed by the dummy gate structure 130 can be removed, and the dry etching process has better cross-section controllability, which is beneficial to Next, second spacers 115 are formed on the sidewalls of the top channel stack 114c. Specifically, the anisotropic dry etching process may be a plasma etching process.

In this embodiment, the material of the sacrificial layer 112 is SiGe, and the material of the channel layer 113 is Si, so the main etching gas used in the dry etching process includes fluorine-based gas, such as CF ₄ , CHF ₃ or C ₂ F ₆ etc.

The second spacer 115 is used as an etching mask for subsequent etching of the first channel stack 114a, and the second spacer 115 also protects the sidewalls of the top channel stack 114c. In this embodiment, the second spacer 115 is located on the sidewalls of the top channel stack 114c and the first spacer 122 .

In this embodiment, the materials of the second sidewall 115 and the first sidewall 122 are different, so as to facilitate the subsequent removal of the second sidewall 115 and reduce the loss to the first sidewall 122 . In this embodiment, the material of the second spacer 115 is silicon nitride. In other embodiments, the material of the second spacer may also be selected from silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride.

The thickness of the second side wall 115 should not be too small nor too large. If the thickness of the second sidewall spacer 115 is too small, the effect of the second sidewall spacer 115 as an etching mask is easily reduced. The subsequent process further includes: laterally etching the channel layer 113 in the bottom channel stack, the second sidewall spacer If the thickness of the second sidewall 115 is too small, the second sidewall 115 is easily consumed, so that it is difficult for the second sidewall 115 to play a corresponding protective role; if the thickness of the second sidewall 115 is too large, it will be difficult to remove the second sidewall If the wall 115 is removed, it is easy to increase the process risk and reduce the process compatibility. If the thickness of the second sidewall 115 is too large, the width of the bottom channel stack is correspondingly large, and the channel in the bottom channel stack is subsequently etched laterally. The time spent on the layer 113 is correspondingly too long, which tends to reduce the production capacity. Therefore, in this embodiment, the thickness of the second sidewall spacer 115 is 3 nm to 10 nm.

In this embodiment, the steps of forming the second spacer 115 include: forming a spacer material layer (not shown) that conformally covers the top and sidewalls of the dummy gate structure 130 and the substrate; removing the top 130 of the dummy gate structure and the top of the substrate The remaining sidewall material layer is used as the second sidewall 115 .

In this embodiment, an atomic layer deposition process is used to form the sidewall material layer. The ALD process has better gap filling performance and step coverage, thereby improving the conformal coverage of the sidewall material layer, and the ALD process involves performing multiple ALD cycles to form a film of the desired thickness layer, which is beneficial to improve the thickness uniformity of the sidewall material layer and precisely control the thickness of the second sidewall 115 .

In this embodiment, a maskless etching process is used to remove the top 130 of the dummy gate structure and the sidewall material layer on the substrate, the process steps are simple, and the process cost is low. Specifically, an anisotropic dry etching process is used to etch the sidewall material layer to form the second sidewall spacer 115.

In this embodiment, the process of etching the first channel stack 114a exposed by the second sidewall spacers 115 is the same as the process of etching the second channel stack 114b exposed by the dummy gate structure 130, which is not repeated here.

In this embodiment, the number of the channel stacks 114 is taken as an example, so only one second spacer 115 is formed. In other embodiments, when the number of the channel stacks is greater than or equal to three, the times of forming the second spacers and etching the channel stacks are correspondingly adjusted according to the number of the channel stacks.

As shown in FIG. 6, the channel layer 113 in the bottom channel stack 114d is laterally etched along a direction perpendicular to the sidewall of the dummy gate structure 120.

By laterally etching the channel layer 113 in the bottom channel stack 114d, the end of the channel layer 113 in the bottom channel stack 114d is indented, so that the bottom channel stack 114d and the top channel stack The channel layers 113 in the layers 114c are different in width.

Specifically, the channel layer 113 in the bottom channel stack 114d is etched by an isotropic etching process, so that the channel layer 113 in the bottom channel stack 114d can be etched in a direction perpendicular to the sidewall of the dummy gate structure 120. Layer 113 is laterally etched.

In this embodiment, an isotropic dry etching process is used to laterally etch the channel layer 113 exposed by the bottom channel stack 114d. The dry etching process has good process controllability and etching uniformity, and it is easy to make the lateral etching amount of the channel layer 113 meet the process requirements. Specifically, isotropic etching can be achieved by adjusting the process pressure and bias voltage of the dry etching process, for example, a dry etching process using high process pressure and low bias voltage.

In this embodiment, the material of the channel layer 113 is silicon, therefore, the main etching gas of the isotropic dry etching process may be a fluorine-based gas, such as CF ₄ , CHF ₃ or C ₂ F ₆ . In other embodiments, when the material of the channel layer is SiGe, correspondingly, a wet etching process may be used to laterally etch the channel layer in the underlying channel stack.

In other embodiments, according to actual process requirements, a wet etching process may also be used to etch the channel layer in the underlying channel stack. The wet etching process has simple operation and low process cost.

It should be noted that, in this embodiment, after the channel layer 113 in the bottom channel stack 114d is laterally etched, the method further includes: as shown in FIG. The sacrificial layer 112 in the bottom channel stack 114d is etched.

By laterally etching the sacrificial layer 112 in the bottom channel stack 114d, the ends of the remaining sacrificial layers 112 in the bottom channel stack 114d are set back from the ends of the channel layers 113 in the bottom channel stack 114d, After the first part of the gate structure is subsequently formed at the position of the remaining sacrificial layer 112, the end of the first part of the gate structure will not protrude from the channel layer 113 located above it, which is beneficial to prevent the gate structure and source-drain doping If the layer distance is too close, problems such as large parasitic capacitance and leakage current are generated, and the performance of the semiconductor structure is correspondingly improved.

In this embodiment, the sacrificial layer 112 in the bottom channel stack 114d is laterally etched by a wet etching process. The wet etching process has the characteristic of isotropic etching, so that the sacrificial layer 112 can be laterally etched along the direction perpendicular to the sidewall of the dummy gate structure 130 .

In this embodiment, the material of the sacrificial layer 112 is SiGe, and the material of the channel layer 113 is Si; therefore, the sacrificial layer 112 is etched laterally by HCl vapor. The etching rate of HCl vapor to SiGe material is much higher than that of Si material, so using HCl vapor to etch sacrificial layer 112 can effectively reduce the probability of channel layer 113 being lost, which is beneficial to the improvement of device performance.

In other embodiments, when the material of the channel layer and the fins is SiGe, and the material of the sacrificial layer is Si, the etching solution used in the wet etching process is correspondingly tetramethylammonium hydroxide (TMAH) solution. The difference between the etching rate of Si material and the etching rate of SiGe material by tetramethyl ammonium hydroxide solution is large. Therefore, the use of tetramethyl ammonium hydroxide solution to etch the sacrificial layer can also effectively reduce the loss of the channel layer. probability.

As shown in FIG. 7 , the second sidewall spacers 115 are removed to expose the sidewalls of the top channel stack 114c. So as to prepare for the subsequent formation of source and drain doped layers.

In this embodiment, the second sidewall spacer 115 is removed by a wet etching process. The wet etching process is easy to achieve a larger etching selectivity ratio, thereby reducing the loss of other film structures. Specifically, a phosphoric acid solution can be used for the wet etching process.

In other embodiments, according to the actual process, a dry etching process may also be used to remove the second sidewall spacer.

Referring to FIG. 8 , in this embodiment, after removing the second spacer 115 , the method further includes: laterally etching the sacrificial layer 112 in the top channel stack 114c along a direction perpendicular to the sidewall of the dummy gate structure 130 .

The sacrificial layer 112 in the top channel stack 114c is laterally etched so that the end of the sacrificial layer 112 in the top channel stack 114c is indented from the end of the channel layer 113 in the top channel bottom layer 114c, and the remaining After the first part of the gate structure is formed at the position of the sacrificial layer 112, the end of the first part of the gate structure will not protrude from the channel layer 113 above it, which is beneficial to prevent the gate structure from being too close to the source and drain doped layers However, problems such as large parasitic capacitance and leakage current are generated, and the performance of the semiconductor structure is correspondingly improved.

In this embodiment, the sacrificial layer 112 is laterally etched by a wet etching process. The process steps of laterally etching the sacrificial layer 112 in the top channel stack 114c are the same as the aforementioned process steps of laterally etching the sacrificial layer 112 in the bottom channel stack 114d, and are not repeated here.

It should be noted that, in the process of laterally etching the sacrificial layer 112 in the top channel stack 114c, the sacrificial layer 112 in the bottom channel stack 114d is also laterally etched; and the top layer is laterally etched After the sacrificial layer 112 in the channel stack 114c is disposed, the sidewall of the sacrificial layer 112 in the bottom channel stack 114d is located on the side of the top channel stack 114 close to the dummy gate structure 130 .

Referring to FIG. 9 , a source-drain doped layer 140 is formed in the groove 150 (as shown in FIG. 8 ).

In this embodiment, the source and drain doped layers 140 are formed by epitaxy and doping processes, and the source and drain doped layers 140 include stress layers. Wherein, when the fully surrounding gate transistor is a PMOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the stress layer are P-type ions; when the fully surrounding gate transistor is an NMOS transistor, the material of the stress layer is Si or SiC, the doping ions in the stress layer are N-type ions.

In this embodiment, the step of forming the source-drain doped layer 140 includes: using a selective epitaxy process, filling the groove 150 with a stress material to form the stress layer, and in the process of forming the stress layer, in-situ self-doping corresponding types of ions to form the source-drain doping layer 140 .

In this embodiment, the top of the source-drain doping layer 140 is higher than the top of the channel stack 114 , and the source-drain doping layer 140 also covers part of the sidewalls of the first spacers 122 . In other embodiments, the top of the source and drain doped layers may also be flush with the top of the channel stack.

Referring to FIG. 10 , the dummy gate structure 130 is removed to form a gate opening 160 exposing the channel stack 114 .

The dummy gate structure 130 is removed to provide a space for the subsequent formation of the gate structure, and at the same time, the channel stack 114 is exposed to provide a process basis for the subsequent removal of the sacrificial layer 112 in the channel stack 114.

In this embodiment, the step of forming the gate opening 160 includes: forming an interlayer dielectric layer 124 (as shown in FIG. 10 ) on the exposed substrate of the dummy gate structure 130 , and the interlayer dielectric layer 124 exposes the top of the dummy gate structure 130 ; The dummy gate structure 130 is removed, and a gate opening 160 exposing the channel stack 114 is formed in the interlayer dielectric layer 124 .

The interlayer dielectric layer 124 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the material of the interlayer dielectric layer 124 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

Specifically, the step of forming the interlayer dielectric layer 124 includes: forming a dielectric material layer (not shown) on the exposed substrate 111 of the dummy gate layer 120, the dielectric material layer covering the top of the dummy gate layer 120; flattening the dielectric material layer After the planarization process, the dielectric material layer above the top of the dummy gate layer 120 is removed, and the remaining dielectric material layer after the planarization process is used as the interlayer dielectric layer 124 .

In this embodiment, the dielectric material layer covers the top of the gate mask layer 123 (as shown in FIG. 9 ), so in the process of forming the interlayer dielectric layer 124 , the gate mask layer 123 is also removed.

In this embodiment, the dummy gate layer 120 spans the channel stack 114 and covers part of the top and part of the sidewalls of the channel stack 114 . Therefore, after removing the dummy gate layer 120 and the gate oxide layer 121 at the bottom of the dummy gate layer 120 , , the gate opening 160 exposes at least part of the top and part of the sidewall of the channel stack 114 . Specifically, after the gate opening 160 is formed, the channel stack 114 protrudes from the bottom of the gate opening 160, and along the extending direction perpendicular to the fins 110, the gate opening 160 exposes the sidewalls of the remaining sacrificial layer 112.

Referring to FIG. 11 , the sacrificial layer 112 in the channel stack 114 is removed to form a through groove 170, the through groove 170 is surrounded by the adjacent channel layer 113 and the source-drain doped layer 140, or the through groove 170 is formed by the substrate, The channel layer 113 adjacent to the substrate and the source-drain doped layer 140 are surrounded, and the through groove 170 communicates with the gate opening 160 .

The sacrificial layer 112 in the channel stack 114 is removed to form through grooves 170 to provide space for the subsequent formation of the gate structure.

In this embodiment, the sacrificial layer 112 exposed by the gate opening 160 is removed by wet etching. Specifically, the material of the channel layer 113 is Si, and the material of the sacrificial layer 112 is SiGe, so the sacrificial layer 112 exposed by the gate opening 160 is removed by HCl vapor, and the etching rate of the sacrificial layer 112 by the wet etching process is much higher than The etch rate of the channel layer 113 and the fins 110 .

It should be noted that, since the sacrificial layer 112 is removed after the source-drain doped layer 140 is formed, after the sacrificial layer 112 exposed by the gate opening 160 is removed, along the extending direction of the fin 110 , both ends of the channel layer 113 are doped with the source and drain. The impurity layer 140 is connected and suspended in the gate opening 160 , so as to provide a foundation for the subsequent gate structure to surround the channel layer 113 .

In this embodiment, after the sacrificial layer 112 is removed, the channel layers 113 are spaced apart, and all the channel structure layers 12 and the channel layers 113 constitute the channel structure layer 125 , and the channel structure layer 125 is located on the fin portion 110 and is connected to the fin portion. 110 interval settings.

Referring to FIGS. 12 to 13 , inner wall layers 117 are formed on the sidewalls of the source-drain doped layer 140 exposed by the through trenches 170 (as shown in FIG. 13 ).

The inner wall layer 117 is used as an inner spacer to cover the sidewall of the gate structure formed in the through groove 170 later, and the gate structure formed in the through groove 170 is used as the first part of the gate structure. The inner wall layer 117 Located between the first part of the gate structure and the source-drain doped layer 140, the distance between the first part of the gate structure and the source-drain doped layer 140 is increased, thereby helping to reduce the gate structure and the source-drain doped layer The parasitic capacitance between 140 and 140, thereby improving the performance of the semiconductor structure.

Moreover, in this embodiment, the inner wall layer 117 is formed after the dummy gate structure 130 and the sacrificial layer 112 are removed, so that the inner wall layer 117 can be formed on the sidewalls of the source and drain doped layers 120 exposed by all the through grooves 170 in the same step. It is beneficial to simplify the process flow and the process steps are simple.

Therefore, the material of the inner wall layer 117 is a dielectric material. In this embodiment, the material of the inner wall layer 117 is silicon oxide, which is a commonly used dielectric material in the semiconductor process, which is beneficial to reduce process cost and improve process compatibility. In other embodiments, the material of the inner wall layer may also be silicon nitride, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. Among them, low-k dielectric materials refer to dielectric materials with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9, and ultra-low-k dielectric materials refer to dielectric materials with relative dielectric constant less than 2.6.

In this embodiment, the step of forming the inner wall layer 117 includes: as shown in FIG. 12 , forming a source-drain doped layer 140 that conformally covers the exposed through groove 170 , the channel layer 113 and the inner wall material layer 116 on the surface of the substrate; As shown in FIG. 13 , the channel layer 113 and the inner wall material layer 116 on the surface of the substrate are removed, and the remaining inner wall material layer 116 on the sidewall of the source and drain doped layer 140 exposed by the through groove 170 is used as the inner wall layer 117 .

In this embodiment, the inner wall material layer 116 is formed by an atomic layer deposition process. The atomic layer deposition process has better gap filling performance and step coverage, thereby improving the conformal coverage of the inner wall material layer 116, and the atomic layer deposition process includes performing multiple atomic layer deposition cycles to form the desired thickness of the film layer , which is beneficial to improve the thickness uniformity of the inner wall material layer 116 and precisely control the thickness of the inner wall layer 117 .

The atomic layer deposition process has better conformal coverage. Therefore, in this embodiment, in the step of forming the inner wall material layer 116, the inner wall material layer 116 is also formed on the sidewall of the gate opening 160 and the gate opening 160 is exposed. on the sidewall of the channel layer 113.

Correspondingly, after removing the channel layer 113 and the inner wall material layer 116 on the surface of the substrate, the inner wall layer 117 is also formed on the sidewall of the gate opening 170 . The gate structure subsequently formed in the gate opening 170 is used as the second part of the gate structure, and the inner wall layer 117 is also located on the sidewall of the second part of the gate structure, which can also increase the size of the second part of the gate structure and the source and drain accordingly. The distance between the doping layer 140 further reduces the parasitic capacitance between the gate structure and the source-drain doping layer 140 .

The thickness of the inner wall layer 117 should neither be too small nor too large. If the thickness of the inner wall layer 117 is too small, it is easy to cause the inner wall layer 117 to be difficult to perform the corresponding isolation function; It affects the effective channel length of the device, which in turn easily affects the performance of the semiconductor device. Therefore, in this embodiment, the thickness of the inner wall layer 117 is 1 nm to 10 nm.

In this embodiment, a remote plasma etch process is used to remove the channel layer 113 and the inner wall material layer 116 on the surface of the substrate.

The remote plasma etching process is to use a plasma source to form plasma outside the etching reaction zone, and then introduce the plasma into the etching reaction zone through gas flow, electric field, magnetic field, etc. to etch the material to be etched. craft. In the remote plasma etching process, the distance between the plasma ionization zone and the etching reaction zone is relatively long, which is beneficial to obtain better spatial uniformity, or obtain a more suitable ratio of ions, neutral components, and Different proportions of free radicals are beneficial to improve the etching effect of the plasma etching process.

Specifically, in this embodiment, in the step of the remote plasma etching process, the plasma can be drilled into the through groove 170 under the carrying of the air flow, and the surface of the channel layer 113 and the inner wall material layer 116 on the substrate can be drilled. Etching is performed, and since the flow velocity of the air flow along the sidewalls perpendicular to the through grooves 170 is relatively slow, the remote plasma etching process affects the inner wall material layer 116 on the sidewalls of the source and drain doped layers 140 exposed through the through grooves 170. The etching rate is also relatively slow. Therefore, after the surface of the channel layer 113 and the inner wall material layer 116 on the substrate are etched away, the sidewalls of the source and drain doped layers 140 exposed by the through grooves 170 and the gate opening 160 side are etched away. The inner wall material layer 116 on the wall can be reserved part of the thickness as the inner wall layer 117 .

In this embodiment, the material of the inner wall material layer 116 is silicon oxide. Therefore, the main etching gas for the remote plasma treatment includes a fluorine-based gas, such as CF ₄ , NF ₃ , or SF ₆ .

The bias voltage of the remote plasma etching process should not be too small nor too large. If the bias voltage is too small, it is easy to reduce the etching rate; if the bias voltage is too large, it is easy to cause the etching rate to be too fast, and then it is easy to reduce the isotropic etching effect of the remote plasma etching process. Therefore, in this embodiment, the bias voltage of the remote plasma etching process is 30V to 500V.

The process pressure of the remote plasma etching process should not be too low nor too high. If the process pressure is too low, it is easy to reduce the density of the plasma, thereby reducing the etching efficiency; if the process pressure is too high, it is easy to reduce the stability and uniformity of the etching process. Therefore, in this embodiment, the process pressure of the remote plasma etching process is 0.1 Torr to 760 Torr.

Referring to FIG. 14, a gate structure 135 is formed in the gate opening 160 and the through trench 170 in which the inner wall layer 117 is formed.

In this embodiment, the gate opening 160 is communicated with the through groove 170 . Therefore, after the gate structure 135 is formed in the gate opening 160 , the gate structure 135 is still located in the through groove 170 , and the gate structure 135 can extend from the gate opening 160 . The channel layer 113 exposed in the 160 surrounds the channel layer 113 and also covers the top of the fin 110, that is, the gate structure 135 can cover the upper surface, the lower surface and the side surface of the channel layer 113 and part of the top and part of the fin 110 side wall. Specifically, the gate structure 135 spans the channel structure layer 125 .

In this embodiment, the gate structure 135 located between the substrate and the channel layer 113 adjacent to the substrate, and the gate structure 135 located between the adjacent channel layers 113 are the first part 131 of the gate structure, and the remaining gate structures The pole structure 135 is the second portion 132 of the gate structure.

An inner wall layer 117 is also formed between the first part 131 of the gate structure and the source-drain doped layer 140, thereby increasing the distance between the first part 131 of the gate structure and the source-drain doped layer 140, and correspondingly reducing the gate The parasitic capacitance between the structure 135 and the source-drain doped layer 140 improves the performance of the semiconductor structure.

In this embodiment, the gate structure 135 is a metal gate structure, including a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. Specifically, the gate dielectric layer covers the upper surface, the lower surface and the side surfaces of the channel layer 113, and also covers part of the top part and part of the sidewall of the fin part 110.

In this embodiment, the material of the gate dielectric layer is a high-k dielectric material; wherein, the high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the gate dielectric layer is HfO ₂ . In other embodiments, the material of the gate dielectric layer may also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al ₂ O ₃ and the like.

In this embodiment, the material of the gate electrode is W. In other embodiments, the material of the gate electrode may also be a conductive material such as Al, Cu, Ag, Au, Pt, Ni, or Ti.

In this embodiment, along the direction from the top of the gate structure 135 to the substrate, the ends of the channel layer 113 are indented in sequence, the length of the channel layer 113 is different, and the width of the channel layer 113 covered by the gate structure 135 is different. are also different in sequence, so that each channel layer 113 in the fully-surrounding gate structure transistor has a different turn-on voltage. Therefore, when the device is working, it is possible to apply voltages of different magnitudes to the transistors. The effect of turning on the channel layer 113 can further satisfy the requirement of applying the fully surrounded gate structure transistor to circuits with different operating voltages.

15 to 27 are schematic structural diagrams corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

Similarities between this embodiment and the preceding embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that in the step of providing the substrate, the number of the channel stacks is greater than or equal to three, and the step of etching the channel stacks on both sides of the dummy gate structure is also different.

15, a substrate (not labeled) is provided on which a plurality of channel stacks 214 are sequentially formed, each channel stack 214 including a sacrificial layer 212 and a channel layer 213 on the sacrificial layer 212.

In this embodiment, the number of the channel stacks 214 is greater than or equal to three. Specifically, in this embodiment, the number of the channel stacks 214 is three as an example. For the detailed description of the substrate and the channel stack 214, reference may be made to the related descriptions of the foregoing embodiments, which will not be repeated here.

With continued reference to Figure 15, a dummy gate structure 230 is formed across the channel stack 214, the dummy gate structure 230 covering a portion of the top and a portion of the sidewall of the channel stack 214. For the detailed description of the dummy gate structure 230, reference may be made to the relevant descriptions of the foregoing embodiments, and details are not described herein again.

Referring to FIGS. 16 to 27 , the channel stacks 214 on both sides of the dummy gate structure 230 are etched, so that the plurality of channel stacks 214 are directed along the direction from the top of the dummy gate structure 230 to the substrate, and the ends of the channel layers 213 are sequentially Recessed, the remaining channel stack 214 and the substrate enclose a recess 250 (as shown in FIG. 27 ).

In this embodiment, the number of the channel stacks 214 is greater than or equal to three, and the steps of etching the channel stacks 214 on both sides of the dummy gate structure 230 include:

16 , using the dummy gate structure 230 as a mask, one channel stack 214 exposed by the dummy gate structure 230 is etched, and the remaining one channel stack 214 after etching is used as an upper channel stack (not shown). This prepares for the subsequent formation of spacers on the upper channel stack.

In this embodiment, the first sidewall spacers 222 are formed on the sidewalls of the dummy gate structure 230 . Therefore, a channel stack exposed by the dummy gate structure 230 is etched using the first sidewall spacers 222 and the dummy gate structure 230 as masks. Layer 214.

In this embodiment, an anisotropic dry etching process is used to etch a channel stack 214 exposed by the dummy gate structure 230. For a detailed description of the process of etching the one channel stack 214 exposed by the dummy gate structure 230 , reference may be made to the relevant description of the second channel stack exposed by etching the dummy gate structure in the foregoing embodiments.

Referring to FIGS. 17 to 20 , at least two preprocessing steps are performed, and the preprocessing steps include: forming second spacers 215 on the sidewalls of the upper channel stack; etching the exposed portions of the second spacers 215 and the upper channel The stacks 214 are adjacent to one channel stack 214 located below the upper channel stack, and the remaining channel stack 214 after etching is used as the lower channel stack (not marked); wherein, the dummy gate is directed along the substrate. In the direction of the top of the structure 230, the upper channel stack farthest from the substrate is the top channel stack 214a (as shown in FIG. 20), and the lower channel stack 214 closest to the substrate is the bottom channel stack 214b (as shown in FIG. 20). Figure 20).

By performing preprocessing at least twice, a plurality of second spacers 215 are sequentially formed on the sidewalls of all the remaining channel stacks 214 except the bottom channel stack 214b, so that each second spacer 215 can be In the subsequent process steps of laterally etching the lower channel stack 214 , the upper channel stack covered by it is protected, so that the etching times of different channel layers 213 are different, thereby realizing different channel layers 213 . The effect of different widths.

The second spacer 215 is used as an etching mask for the subsequent etching of the lower channel stack, and the second spacer 215 is also used to protect the adjacent lower channel stack in the subsequent step of etching the lower channel stack. sidewalls of the upper channel stack. In order to ensure that the second sidewall 215 can play a corresponding protective role, in this embodiment, the thickness of the second sidewall 115 is also 3 nm to 10 nm.

In this embodiment, the material of the second sidewall 215 is different from that of the first sidewall 222, so as to facilitate subsequent removal of the second sidewall 215. For the detailed description of the material of the second sidewall 215, reference may be made to the related description of the material of the second sidewall in the foregoing embodiments, and details are not repeated here.

In this embodiment, the number of the channel stacks 214 is three as an example, therefore, the preprocessing is performed twice. Correspondingly, two second sidewalls 215 ( 215 a and 215 b ) are formed in sequence after two pretreatments.

In this embodiment, the materials of the two second sidewalls 215 are different, which is correspondingly favorable for subsequent removal of one second sidewall 215 in sequence.

In other embodiments, when the number of channel stacks is greater than three, the number of preprocessing is correspondingly reduced by one from the number of channel stacks, and the number of formed second spacers is the same as the number of preprocessing. Correspondingly, in order to facilitate the subsequent removal of one second side wall in sequence, the materials of the adjacent second side walls are also different.

In this embodiment, the process steps of forming the second sidewall 215 are the same as those in the previous embodiment, and are not repeated here.

In this embodiment, the process of etching a channel stack 214 exposed by the second sidewall spacer 215 adjacent to the upper channel stack and located below the upper channel stack is similar to the process of etching the dummy gate structure 230 exposed above. The process of one channel stack 214 is the same, which is not repeated here.

Referring to FIG. 21 , after at least two pretreatments, the channel layer 213 in the exposed bottom channel stack 214b is laterally etched along the direction perpendicular to the sidewall of the dummy gate structure 230 .

In this embodiment, after the channel layer 213 in the bottom channel stack 214b is etched, compared with the channel layer 213 in the upper channel stack adjacent to the bottom channel stack 214b, the bottom channel stack The end of the channel layer 213 in 214b is indented, so that after the sidewall 215 on the sidewall of the upper channel stack is subsequently removed, and the exposed channel layer 213 is etched, the channel layer 213 in the remaining upper channel stack is The ends of the remaining channel layers 213 in the bottom channel stack 214b are still indented compared to layer 213 .

In this embodiment, an isotropic etching process is used to etch the channel layer 213 in the bottom channel stack 214b. The process of etching the channel layer 213 in the bottom channel stack 214b is the same as that in the previous embodiment.

In this embodiment, the number of the channel stacks 214 is greater than or equal to three, and after the channel layers 213 in the exposed bottom channel stacks 214b are etched laterally, the method further includes: as shown in FIG. The direction of the sidewall of the gate structure 230 is laterally etched to expose the sacrificial layer 212 in the underlying channel stack 214b.

The exposed sacrificial layer 212 in the bottom channel stack 214b is laterally etched, so that the end of the remaining sacrificial layer 212 in the bottom channel stack 214b is smaller than the end of the channel layer 213 in the bottom channel stack 214b Furthermore, after the first part of the gate structure is subsequently formed at the position of the remaining sacrificial layer 212, the end of the first part of the gate structure will not protrude from the channel layer 213 located above it, which is beneficial to prevent the gate structure and source-drain doping If the impurity layer is too close, problems such as large parasitic capacitance and leakage current are generated, which improves the performance of the semiconductor structure.

In this embodiment, the sacrificial layer 212 in the bottom channel stack 214b is laterally etched by a wet etching process. The process of laterally etching the sacrificial layer 212 in the bottom channel stack 214b is the same as the previous embodiment.

Referring to FIGS. 23 to 25 , after the channel layer 213 in the exposed underlying channel stack 214b is laterally etched, at least one lateral etching process is performed, and the lateral etching process includes: removing a second spacer 215, The sidewalls of the upper channel stack adjacent to the lower channel stack are exposed; along the direction perpendicular to the sidewalls of the dummy gate structure 230 , the exposed channel layer 213 is etched laterally.

By sequentially removing one of the second spacers 215 and laterally etching the exposed channel layer 213, in the direction from the substrate to the top of the dummy gate structure 230, the etching times of each channel layer 213 are different, so that the The channel layer 213 closer to the substrate is etched more times, and the channel layer 213 closer to the substrate is etched more, so that the channel layer is etched along the top of the dummy gate structure 230 toward the substrate. The ends of 213 are successively indented.

For example, the lateral etching process includes: as shown in FIG. 23 , removing the second spacer 215b (shown in FIG. 22 ) on the sidewalls of the upper channel stack adjacent to the bottom channel stack 214b ; as shown in FIG. 22 ; As shown in FIG. 24 , the exposed channel layer 213 is etched laterally along the direction perpendicular to the sidewall of the dummy gate structure 230 . Specifically, the exposed channel layer 213 in the bottom channel stack 214b and the channel layer 213 in the upper channel stack adjacent to the bottom channel stack 214b are laterally etched.

In this embodiment, a second sidewall spacer 215 is removed by a wet etching process. Removing one second sidewall 215 is the same as the process of removing the second sidewall in the foregoing embodiment, and details are not repeated here.

In this embodiment, the process of laterally etching the exposed channel layer 213 is the same as the process of etching the channel layer 213 in the bottom channel stack 214b, which is not repeated here.

In this embodiment, the number of the channel stacks 214 is three as an example, therefore, the number of times of performing the lateral etching treatment is correspondingly once. In other embodiments, when the number of channel stacks is greater than three, the number of lateral etching processes is correspondingly reduced by two for the number of channel stacks.

It should be noted that, in the step of performing the lateral etching process, after laterally etching the exposed channel layer 213 along a direction perpendicular to the sidewall of the dummy gate structure 230 , the method further includes: along a direction perpendicular to the sidewall of the dummy gate structure 230 . direction, the sacrificial layer 212 in the upper channel stack is etched laterally.

For example, as shown in FIG. 25 , after the channel layer 213 in the exposed bottom channel stack 214b is etched laterally, the bottom channel stack 214b and the bottom channel stack 214b are laterally etched in a direction perpendicular to the sidewall of the dummy gate structure 230 . The sacrificial layer 212 in the adjacent upper channel stack.

In the step of performing the lateral etching process, the sacrificial layer 212 in the upper channel stack is etched laterally along the direction perpendicular to the sidewall of the dummy gate structure 230, so that the end of the sacrificial layer 212 in the upper channel stack is larger than the upper channel stack. In the channel stack, the end of the channel layer 213 is indented, and the first part of the gate structure is subsequently formed at the position of the sacrificial layer 212 to be thick, and the end of the first part of the gate structure will not protrude from the channel layer located above it. 213, which is beneficial to prevent the gate structure and the source-drain doping layer from being too close to cause problems such as large parasitic capacitance and leakage current, and correspondingly improve the performance of the semiconductor structure.

In this embodiment, the process steps of laterally etching the sacrificial layer 212 in the upper channel stack are the same as the aforementioned process of laterally etching the sacrificial layer 212 in the bottom channel stack 214b, which will not be repeated here.

Referring to FIG. 26, after at least one lateral etching process, the second spacers 215a located on the sidewalls of the top channel stack 214a are removed (as shown in FIG. 25). Thereby, preparations are made for the subsequent formation of the source and drain doped layers.

In this embodiment, a wet etching process is used to remove the second spacers 215a located on the sidewalls of the top channel stack 214a. The process of removing the second sidewall spacer 215a is the same as the process of removing the second sidewall spacer in the foregoing embodiment, and will not be repeated here.

It should be noted that, after removing the second spacer 215 located on the sidewall of the top channel stack 214a, the method further includes: as shown in FIG. 27 , laterally etching the top trench along the direction perpendicular to the sidewall of the dummy gate structure 230 Sacrificial layer 212 in track stack 214a.

In this embodiment, the process of laterally etching the sacrificial layer 212 in the top channel stack 214a is the same as that in the previous embodiment, and will not be repeated here.

Subsequent process steps are the same as those in the foregoing embodiment, and are not repeated here.

Correspondingly, the present invention also provides a semiconductor structure. Referring to FIG. 28, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate (not shown); a channel structure layer 425 located on the substrate and spaced from the substrate, the channel structure layer 425 including a plurality of spaced-apart channel layers 413 and along the top of the channel structure layer 425 In the direction toward the substrate, the ends of the channel layer 413 are successively indented; the gate structure 435 across the channel structure layer 425, the gate structure 435 covers part of the top of the substrate and surrounds the channel layer 413, located between the substrate and the gate structure 435. The gate structures 435 between the adjacent channel layers 413 and the gate structures 435 between the adjacent channel layers 413 are the first part 431 of the gate structure, and the remaining gate structures 435 are the second gate structure Part 432; the source and drain doped layers are located in the channel structure layer 425 on both sides of the gate structure 435; the inner wall layer is located between the first part 431 of the gate structure and the source and drain doped layers.

By making the direction from the top of the channel structure layer 425 to the substrate, the ends of the channel layer 413 are indented in sequence, so the lengths of the channel layers 413 are all different, and the channel layer 413 covered by the gate structure 435 serves as a trench The lengths of the channel regions are also different, so that each channel layer 413 in the transistor with the fully surrounding gate structure has a different turn-on voltage. In the manner of voltage, the effect of turning on different channel layers 413 in the transistor can be realized, so as to meet the requirement of applying the fully surrounding gate structure transistor to circuits with different operating voltages.

The inner wall layer 417 is located between the first part 431 of the gate structure and the source-drain doped layer 440, which increases the distance between the first part 431 of the gate structure and the source-drain doped layer 440, thereby reducing the first part of the gate structure The parasitic capacitance between 431 and the source-drain doping layer 440 improves the performance of the semiconductor structure.

The substrate provides a process platform for the formation of all-around gate structure transistors. In this embodiment, the base is a three-dimensional structure, and the base includes the substrate 400 and the fins 410 protruding from the substrate 400 . In other embodiments, when the substrate is a planar structure, the substrate accordingly includes only the substrate.

In this embodiment, the substrate 400 is a silicon substrate. In this embodiment, the fins 410 are made of the same material as the substrate 400, and the material of the fins 410 is silicon. In other embodiments, the fins may also be of a different material than the substrate.

The fins 410 expose part of the substrate 400 so that the isolation structures 411 can be formed.

Therefore, in this embodiment, the semiconductor structure further includes: an isolation structure 411 located on the substrate 400 where the fins 410 are exposed. The isolation structure 411 is used to isolate adjacent devices. In this embodiment, the material of the isolation structure 411 is silicon oxide. In other embodiments, the material of the isolation structure may also be other insulating materials such as silicon nitride or silicon oxynitride.

In this embodiment, the tops of the isolation structures 411 are flush with the tops of the fins 410, thereby preventing the fins 410 from being used as channels.

The channel structure layer 425 is located on the fin portion 410 and is spaced apart from the fin portion 410 , and the channel structure layer 425 includes at least two spaced apart channel layers 413 , so that the gate structure 435 can surround the channel layer 413 .

The channel of the fully surrounding gate transistor is located in the channel structure layer 425 (ie, the channel layer 413). In this embodiment, the material of the channel layer 413 is the same as that of the fin portion 410, and the material of the channel layer 413 is Si. In other embodiments, when the fully surrounding gate transistor is a PMOS transistor, in order to improve the performance of the PMOS transistor, the SiGe channel technology is generally used. Correspondingly, the materials of the fin and the channel layer are all SiGe.

In this embodiment, the channel structure layer 425 includes two channel layers 413 arranged at intervals. In other embodiments, according to actual process requirements, the number of channel layers may be greater than or equal to three.

It should be noted that, the distance by which the end of the channel layer 413 is indented should not be too small or too large. If the indented distance of the end of the channel layer 413 is too small, the difference in the turn-on voltage of each channel layer 413 is relatively small when the device is operating, and it is difficult to achieve the effect of distinguishing different turn-on voltages; if the end of the channel layer 413 If the indentation distance is too large, when the number of channel layers 413 is large, the width of the channel layer 413 close to the substrate is correspondingly too small, which is easy to increase the process risk, and it is easy to affect the effective channel length of the device, which is easy to affect the device. performance. Therefore, in this embodiment, the distance by which the end of the channel layer 413 is indented on one side is greater than 0 nm and less than or equal to 5 nm.

In this embodiment, the gate structure 435 spans the channel structure layer 425 , the gate structure 435 surrounds the channel layer 413 and also covers part of the top of the fin 410 , that is, the gate structure 435 covers the upper surface of the channel layer 413 , The lower surface and sides and part of the top of the fins 410 .

In this embodiment, the gate structure 435 is a metal gate structure, and the gate structure 435 includes a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. Since the channel of the fully surrounding gate transistor is located in the channel layer 413 and the fin 410, the gate dielectric layer covers the upper surface, the lower surface and the side surface of the channel layer 413, and also covers part of the top of the fin 410.

In this embodiment, the material of the gate dielectric layer is HfO ₂ , and the material of the gate electrode is W.

In this embodiment, the gate structure 435 located between the substrate and the channel layer 413 adjacent to the substrate, and the gate structure 435 located between the adjacent channel layers 413 are the first part 431 of the gate structure, and the remaining gate structures 431 The pole structure 435 is the second portion 432 of the gate structure.

In this embodiment, along the direction from the top of the gate structure 435 to the substrate, the ends of the first portion 431 of the gate structure are indented in sequence, and the width of the first portion 431 of the gate structure is smaller than that adjacent to the first portion 431 of the gate structure and The width of the channel layer 413 located above the first portion 431 of the gate structure so that the end of the first portion 431 of the gate structure does not protrude from the channel layer 413 located above it, preventing the first portion 431 of the gate structure from interacting with the source If the distance between the drain doped layers 440 is too close, problems such as large parasitic capacitance and leakage current are generated, and the performance of the semiconductor structure is correspondingly improved.

In this embodiment, the semiconductor structure further includes a sidewall 422 located on the sidewall of the second portion 432 of the gate structure. The sidewall spacers 422 are used to protect the sidewalls of the second portion 432 of the gate structure, and the sidewall spacers 422 are also used to define the formation regions of the source and drain doped layers 440.

The material of the spacer 422 can be selected from silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride, and the spacer 422 can be a single-layer structure or Laminated structure. In this embodiment, the sidewall spacer 422 is a single-layer structure, and the material of the sidewall spacer 422 is silicon nitride.

In this embodiment, the source-drain doping layer 440 includes a stress layer doped with ions. Specifically, when the fully surrounding gate transistor is a PMOS transistor, the material of the stressor layer is Si or SiGe, and the doping ions in the stressor layer are P-type ions; when the fully surrounding gate transistor is an NMOS transistor, the material of the stressor layer is It is Si or SiC, and the doping ions in the stress layer are N-type ions.

In this embodiment, the top of the source-drain doped layer 440 is higher than the top of the channel structure layer 425 , and the source-drain doped layer 440 also covers part of the sidewall of the sidewall spacer 422 . In other embodiments, the top of the source and drain doped layers may also be flush with the top of the channel structure layer.

The inner wall layer 417 serves as an inner wall and is located between the first part 431 of the gate structure and the source-drain doped layer 440, which increases the distance between the first part 431 of the gate structure and the source-drain doped layer 440, which is beneficial to reduce the gate The parasitic capacitance between the first part 431 of the pole structure and the source-drain doped layer 440 improves the performance of the device.

In this embodiment, the inner wall layer 417 is also located on the sidewall of the second portion 432 of the gate structure, which can correspondingly increase the distance between the second portion 432 of the gate structure and the source-drain doped layer 440, thereby reducing the gate structure 435 Parasitic capacitance with the source-drain doped layer 440 .

Therefore, the material of the inner wall layer 417 is a dielectric material. In this embodiment, the material of the inner wall layer 417 is silicon oxide, which is a commonly used dielectric material in the semiconductor process, which is beneficial to reduce process cost and improve process compatibility. In other embodiments, the material of the inner wall layer may also be silicon nitride, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.

The thickness of the inner wall layer 417 should neither be too small nor too large. If the thickness of the inner wall layer 417 is too small, it is difficult to perform the corresponding isolation function; if the thickness of the inner wall layer 417 is too large, the volume of the first part 431 of the gate structure is likely to be too small, which easily affects the effective channel length of the device, and further easy semiconductor device performance. Therefore, the thickness of the inner wall layer 417 in this embodiment is 1 nm to 10 nm.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 424 located on the exposed substrate of the gate structure 435 . The interlayer dielectric layer 424 covers the source and drain doped layers 440 and exposes the top of the gate structure 435 .

The interlayer dielectric layer 424 is used to achieve electrical isolation between adjacent semiconductor structures. In this embodiment, the material of the interlayer dielectric layer 424 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

In this embodiment, the gate structure 435 is formed by a process of forming a high-k gate dielectric layer and then forming a high-k last metal gate last, and before the gate structure 435 is formed, the dummy gate structure used is a stack Therefore, the semiconductor structure further includes: a gate oxide layer 421 located between the spacer 422 and the channel structure layer 425 . Wherein, in the process of removing the dummy gate structure to form the gate structure 435, the gate oxide layer 421 between the spacer 422 and the channel structure layer 425 is preserved under the protection of the spacer 422.

In this embodiment, the material of the gate oxide layer 421 is silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride. In other embodiments, when the adopted dummy gate structure is a single-layer structure, the semiconductor structure may also not contain a gate oxide layer.

The semiconductor structure can be formed by the forming method described in the foregoing embodiments, or can be formed by other forming methods. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined by the claims.

Claims (21)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a plurality of channel lamination layers are sequentially formed on the substrate, and each channel lamination layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer;

forming a dummy gate structure crossing the channel lamination layer, wherein the dummy gate structure covers part of the top and part of the side wall of the channel lamination layer;

etching the channel lamination layers on two sides of the pseudo-gate structure to enable the channel lamination layers to be in the direction pointing to the substrate along the top of the pseudo-gate structure, enabling the end parts of the channel layers to be sequentially retracted, and enabling the residual channel lamination layers and the substrate to form a groove in a surrounding mode;

forming a source drain doping layer in the groove; removing the pseudo gate structure to form a gate opening exposing the channel lamination;

removing the sacrificial layer in the channel lamination to form a through groove, wherein the through groove is surrounded by the adjacent channel layer and the source-drain doping layer, or the through groove is surrounded by the substrate, the channel layer adjacent to the substrate and the source-drain doping layer, and the through groove is communicated with the grid opening;

forming an inner wall layer on the side wall of the source drain doping layer exposed out of the through groove;

and forming a gate structure in the gate opening and the through groove formed with the inner wall layer.

2. The method of forming a semiconductor structure according to claim 1, wherein in the step of providing a substrate, the number of the channel stacks is two, and the channel stacks include a first channel stack and a second channel stack located on the first channel stack;

the step of etching the channel lamination layers on the two sides of the pseudo gate structure comprises the following steps:

etching the second channel lamination layer exposed by the pseudo gate structure by taking the pseudo gate structure as a mask, wherein the second channel lamination layer is left after etching and is used as a top-layer channel lamination layer; forming a side wall on the side wall of the top-layer channel lamination; etching the first channel lamination layer exposed from the side wall, wherein the etched residual first channel lamination layer is used as a bottom layer channel lamination layer;

transversely etching the channel layer in the bottom channel lamination along the direction vertical to the side wall of the pseudo gate structure; removing the side wall and exposing the side wall of the top-layer channel lamination;

or,

the number of the channel lamination layers is more than or equal to three, and the step of etching the channel lamination layers on two sides of the pseudo gate structure comprises the following steps:

etching one exposed channel lamination layer of the pseudo gate structure by taking the pseudo gate structure as a mask, wherein the rest channel lamination layer after etching is taken as an upper channel lamination layer;

performing at least two pretreatments, the step of pretreating comprising: forming a side wall on the side wall of the upper-layer channel lamination; etching the side wall to expose a channel lamination which is adjacent to the upper channel lamination and is positioned below the upper channel lamination, and taking the etched residual channel lamination as a lower channel lamination; in the direction of pointing to the pseudo-gate structure along the substrate, the upper-layer channel lamination layer farthest from the substrate is a top-layer channel lamination layer, and the lower-layer channel lamination layer closest to the substrate is a bottom-layer channel lamination layer;

after at least two times of pretreatment, transversely etching the exposed channel layer in the bottom layer channel lamination along the direction vertical to the side wall of the pseudo gate structure;

after the exposed channel layer in the bottom channel lamination is transversely etched, transverse etching treatment is carried out at least once, and the transverse etching treatment comprises the following steps: removing one side wall to expose the side wall of the upper-layer channel lamination layer adjacent to the lower-layer channel lamination layer; transversely etching the exposed channel layer along a direction vertical to the side wall of the pseudo gate structure;

and after at least one time of transverse etching treatment, removing the side wall on the side wall of the top-layer channel lamination.

3. The method of forming a semiconductor structure of claim 2, wherein the number of the channel stacks is two;

after transversely etching the channel layer in the bottom channel lamination and before removing the side wall, the method further comprises the following steps: transversely etching the sacrificial layer in the bottom layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

after removing the side wall, before forming the source-drain doping layer, the method further comprises the following steps: transversely etching the sacrificial layer in the top-layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

or,

the number of the channel lamination layers is more than or equal to three, and after the channel layer in the bottom layer channel lamination layer exposed by transverse etching is carried out, the method also comprises the following steps of: transversely etching the exposed sacrificial layer in the bottom layer channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

in the step of performing the transverse etching treatment, after transversely etching the exposed channel layer along a direction perpendicular to the sidewall of the dummy gate structure, the method further includes: transversely etching the sacrificial layer in the upper channel lamination layer along the direction vertical to the side wall of the pseudo gate structure;

after removing the side wall on the side wall of the top-layer channel lamination, the method further comprises the following steps: and transversely etching the sacrificial layer in the top channel lamination layer along the direction vertical to the side wall of the pseudo gate structure.

4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the inner wall layer comprises: forming a source drain doping layer which conformally covers the exposed through groove, and inner wall material layers of the channel layer and the substrate surface; and removing the channel layer and the inner wall material layer on the surface of the substrate, wherein the residual inner wall material layer on the side wall of the source drain doping layer exposed from the through groove is used as the inner wall layer.

5. The method of forming a semiconductor structure of claim 4, wherein forming the gate opening comprises: forming an interlayer dielectric layer on the substrate exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; removing the pseudo gate structure, and forming the gate opening exposing the channel lamination in the interlayer dielectric layer;

in the step of forming the inner wall material layer, the inner wall material layer is further formed on the side wall of the gate opening and the side wall of the channel layer exposed from the gate opening;

and after the inner wall material layers on the surfaces of the channel layer and the substrate are removed, the inner wall layer is also formed on the side wall of the grid opening.

6. The method of claim 4, wherein the inner wall material layer is formed using an atomic layer deposition process.

7. The method of forming a semiconductor structure of claim 4, wherein the inner wall material layer of the channel layer and substrate surface is removed using a remote plasma etch process.

8. The method of forming a semiconductor structure of claim 7, wherein a process parameter of the remote plasma etch processThe number of the components comprises: the etching gas includes: CF (compact flash)₄、NF₃Or SF₆The bias voltage is 30V to 500V, and the process pressure is 0.1Torr to 760 Torr.

9. The method of claim 1, wherein the end of the channel layer is recessed by a distance greater than 0nm and less than or equal to 5 nm.

10. The method for forming the semiconductor structure according to claim 2, wherein in the step of forming the side wall, the thickness of the side wall is 3nm to 10 nm.

11. The method for forming the semiconductor structure according to claim 2, wherein the step of forming the side wall includes: forming a side wall material layer which conformally covers the top and the side wall of the pseudo gate structure and the substrate; and removing the side wall material layers on the top of the pseudo gate structure and the substrate, and taking the rest side wall material layers as the side walls.

12. The method of claim 2, wherein the material of the sidewall spacers comprises silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon oxycarbonitride.

13. The method for forming a semiconductor structure according to claim 2, wherein the sidewall spacers are removed by a wet etching process.

14. The method for forming a semiconductor structure according to claim 2, wherein the step of etching the second channel stack exposed by the dummy gate structure, the step of etching the first channel stack exposed by the sidewall, the step of etching the channel stack exposed by the dummy gate structure, and the step of etching the sidewall to expose a channel stack adjacent to and below the upper channel stack is an anisotropic dry etching process.

15. The method of forming a semiconductor structure of claim 2, wherein the process of laterally etching the channel layer in the bottom channel stack, the laterally etched exposed channel layer, is an isotropic dry etching process.

16. A semiconductor structure, comprising:

a substrate;

the channel structure layer is positioned on the substrate and is arranged at intervals with the substrate, the channel structure layer comprises a plurality of channel layers arranged at intervals, and the end parts of the channel layers are sequentially retracted along the direction in which the top of the channel structure layer points to the substrate;

the grid structure stretches across the channel structure layer, the grid structure covers the top of part of the substrate and surrounds the channel layer, the grid structure positioned between the substrate and the channel layer adjacent to the substrate and the grid structure positioned between the adjacent channel layers are first parts of the grid structure, and the rest of the grid structure is second parts of the grid structure;

the source-drain doping layer is positioned in the channel structure layers at two sides of the grid structure;

and the inner wall layer is positioned between the first part of the grid structure and the source-drain doping layer.

17. The semiconductor structure of claim 16, wherein ends of the first portion of the gate structure are sequentially tapered in a direction from a top of the gate structure toward the substrate, and wherein a width of the first portion of the gate structure is less than a width of a channel layer adjacent to and above the first portion of the gate structure.

18. The semiconductor structure of claim 16, wherein the inner wall layer is further located on sidewalls of the second portion of the gate structure.

19. The semiconductor structure of claim 16, wherein the material of the inner wall layer comprises silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material.

20. The semiconductor structure of claim 16, wherein the thickness of the inner wall layer is 1nm to 10 nm.

21. The semiconductor structure of claim 16, wherein an end portion of the channel layer is recessed a distance greater than 0nm and less than or equal to 5 nm.

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