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CN113962055B - Network Interconnection Detection System for Target Multilevel Design Connection Path - Google Patents
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CN113962055B - Network Interconnection Detection System for Target Multilevel Design Connection Path - Google Patents

Network Interconnection Detection System for Target Multilevel Design Connection Path Download PDF

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CN113962055B
CN113962055B CN202111537379.6A CN202111537379A CN113962055B CN 113962055 B CN113962055 B CN 113962055B CN 202111537379 A CN202111537379 A CN 202111537379A CN 113962055 B CN113962055 B CN 113962055B
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CN113962055A (en
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陈�峰
敬伟
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Beijing Yunshu Innovation Software Technology Co ltd
Shanghai Hejian Industrial Software Group Co Ltd
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Beijing Yunshu Innovation Software Technology Co ltd
Shanghai Hejian Industrial Software Group Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
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    • G06F30/30Circuit design
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    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
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    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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Abstract

本发明涉及一种目标多级设计连接路径的网络互联检测系统,包括第一显示区域、第二显示区域、预先配置的目标设计连接路径表,存储有计算机程序的存储器和处理器,其中,第一显示区域用于显示预先生成的多级设计连接路径的网络匹配结构,包括M个网络列区域;目标设计连接路径表包括N个网络列区域;所述第一显示区域和所述目标设计连接路径表中,每一网络列区域包括至少沿垂直方向排列的位于该网络列区域对应的设计元器件上的网络标识,第i列对应的设计元器件是第i+1列对应的设计元器件的父节点位于同一设计连接路径上的网络标识位于同一行。本发明所述系统提高了目标多级设计连接路径的网络互联的检测效率和准确度。

Figure 202111537379

The invention relates to a network interconnection detection system for target multi-level design connection paths, comprising a first display area, a second display area, a pre-configured target design connection path table, a memory and a processor storing a computer program, wherein the first display area is A display area is used to display the pre-generated network matching structure of multi-level design connection paths, including M network column areas; the target design connection path table includes N network column areas; the first display area is connected to the target design In the path table, each network column area includes at least the network identifiers on the design components corresponding to the network column area arranged in the vertical direction, and the design components corresponding to the i-th column are the design components corresponding to the i+1-th column. Net IDs whose parent nodes are on the same design connection path are on the same row. The system of the invention improves the detection efficiency and accuracy of the network interconnection of the target multi-level design connection path.

Figure 202111537379

Description

Network interconnection detection system of target multilevel design connection path
Technical Field
The invention relates to the technical field of electronic design, in particular to a network interconnection detection system for a target multilevel design connection path.
Background
In electronic design, it is usually necessary to detect connectivity of a multilevel interconnection link composed of a design (Device) such as a PCB (Printed Circuit Board), a Package, an Interposer (Package carrier), an IC (integrated Circuit), and the like. In the prior art, a network matching structure of a designed link is usually manufactured and displayed in a manual tabulation mode, and then network interconnection of multiple designed connection paths is manually compared based on a display result, so that network interconnection detection of a target multilevel designed connection path is realized. However, manual detection is usually limited to designing a two-stage structure of a link, which not only needs to consume a large amount of manual work, but also has low detection efficiency. In addition, with the increase of the design level, the manual tabulation can not clearly display the network matching structure of the whole multi-level design connection path, and the detection efficiency and accuracy of the network interconnection detection of the target multi-design connection path are reduced. Therefore, how to improve the detection efficiency and accuracy of the network interconnection detection of the target multi-design connection path becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a network interconnection detection system of a target multi-level design connection path, which realizes automatic detection and improves the detection efficiency and accuracy of network interconnection of the target multi-level design connection path.
According to an aspect of the present invention, a network interconnection detection system for a target multi-level design connection path is provided, including a first display area, a second display area, a pre-configured target design connection path table, a memory storing a computer program, and a processor, wherein the first display area is configured to display a network matching structure of a pre-generated multi-level design connection path, and includes M network column areas; the target design connection path table comprises N network column areas; in the first display area and the target design connection path table, each network column area comprises network identifiers which are arranged at least along the vertical direction and are positioned on the design components corresponding to the network column area, the design component corresponding to the ith column is a father node of the design component corresponding to the (i + 1) th column, the value range of i is 1 to MAX (M, N), and the network identifiers positioned on the same design connection path are positioned on the same row;
when the processor executes the computer program, the following steps are implemented:
step S1, selecting a region to be detected from the first display region according to the design component corresponding to the target design connection path table, and displaying the region which is not selected as the region to be detected in the first display region in a preset first display mode;
step S2, acquiring an intersection of a to-be-detected design connecting path set in the to-be-detected area and a target design connecting path set in the target design connecting path table, a first difference set of the to-be-detected design connecting path set and the target design connecting path set, and a second difference set of the target design connecting path set and the to-be-detected design connecting path set;
step S3, displaying the to-be-detected designed connection paths existing in the to-be-detected area in the intersection in a preset second presentation manner, displaying the to-be-detected designed connection paths existing in the first difference set in the to-be-detected area in a preset third presentation manner, and presenting the first difference set and the second difference set in the second display area.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By the technical scheme, the network interconnection detection system of the target multilevel design connection path can achieve considerable technical progress and practicability, has wide industrial utilization value, and at least has the following advantages:
the invention can automatically perform bidirectional matching on the network matching structure of the multilevel design connecting path displayed in the first display area and the target design connecting path table, perform bidirectional verification on the target design connecting path, and jointly present the detection result in the first display area and the second display area, thereby improving the detection efficiency and accuracy of the network interconnection of the target multilevel design connecting path.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the technical means can be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a network interconnection detection system for a target multi-level design connection path according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a network matching structure of a multi-level design connection path of a first display area according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given with reference to the accompanying drawings and preferred embodiments of a network interconnection detection system with a target multi-level design connection path according to the present invention.
An embodiment of the present invention provides a network interconnection detection system for a target multi-level design connection path, as shown in fig. 1, including a first display area, a second display area, a pre-configured target design connection path table, a memory storing a computer program, and a processor. The first display area is used for displaying a pre-generated network matching structure of a multi-level design connection path and comprises M network column areas; specifically, the processor responds to a network matching display creation instruction input by a user when executing a corresponding computer program, obtains network matching parameters in the multi-level design connection path, and displays a network matching structure of the multi-level design connection path in the display area. It should be noted that the multi-level design connection path may be obtained by establishing physical connections of pins of the designed components at corresponding levels directly based on the logic relationship between design data and the physical connection relationship between the components in advance in the prior art, and based on the established multi-level design connection path, a network matching state may be acquired, and the acquisition process is not described herein again. As an embodiment, each ith network column area in the first presentation area includes at least one of a first presentation area, a second presentation area and a blank area. The first presentation area is used for presenting the network identifiers in the ith network column area on the same design connection path as the network identifiers in the ith-1 network column area. The second presentation area is used for presenting the network identifications in the ith network column area on the same design connection path with the network identifications in the (i + 1) th network column area. Fig. 2 shows a schematic view of a first display area.
The target design connection path table includes N network column regions. In the first display area and the target design connection path table, each network column area includes at least network identifiers arranged in the vertical direction and located on the design components corresponding to the network column area, the design component corresponding to the ith column is a parent node of the design component corresponding to the (i + 1) th column, the value range of i is 1 to MAX (M, N), the network identifiers located on the same design connection path are located in the same row, it is noted that MAX (M, N) represents taking the maximum value of M and N, as a preferred embodiment, the design components corresponding to the target design connection path are part or all of the design components in the first display area, and then N is less than or equal to M. However, it is understood that N may be larger than M, and the design components corresponding to the target design connection path may also correspond to only a part of the design components in the first display area.
When the processor executes the computer program, the following steps are implemented:
step S1, selecting a region to be detected from the first display region according to the design component corresponding to the target design connection path table, and displaying the region which is not selected as the region to be detected in the first display region in a preset first display mode;
it can be understood that the target design connection path table corresponds to a group of design component sequences arranged according to the target design connection path, the design component sequences arranged according to the design connection path also exist in the first display region, and the design component sequences corresponding to the target design connection path table are usually a subset of the first display region design component sequences, so that the region to be detected is selected from the first display region directly based on the design components corresponding to the target design connection path table.
Step S2, acquiring an intersection of a to-be-detected design connecting path set in the to-be-detected area and a target design connecting path set in the target design connecting path table, a first difference set of the to-be-detected design connecting path set and the target design connecting path set, and a second difference set of the target design connecting path set and the to-be-detected design connecting path set;
it should be noted that, bidirectional detection can be quickly realized through step S2, that is, a connection path table is designed by using the area to be detected as a reference detection target; and detecting the area to be detected by taking the target design connection path table as a reference.
Step S3, displaying the to-be-detected designed connection paths existing in the to-be-detected area in the intersection in a preset second presentation manner, displaying the to-be-detected designed connection paths existing in the first difference set in the to-be-detected area in a preset third presentation manner, and presenting the first difference set and the second difference set in the second display area.
It should be noted that the presentation modes may be various, and may be distinguished by different identification modes, for example, different colors may be used for distinguishing, different lines may be marked for distinguishing, the lines may be straight lines, wavy lines, zigzag lines, and the like, different ground colors may also be set for distinguishing, different shapes of frame marks may also be used for distinguishing, and based on the detection result, the frame marks may be displayed in the first display region shown in fig. 2 in a display mode corresponding to the detection result. And the network matching condition of each designed link can be clearly and intuitively displayed through the content displayed in the first display area. In the example shown in fig. 2, PCB _ NET1, POWER, GROUND, PKG _ DIE2_ NET1 and the like displayed on the corresponding columns of test _ PCB _0820, PKG _0820, PKG _0820_2, PKG _0820_3, PKG _0820_4 and PKG _0820_5 are network identifiers on the device. test _ PCB _0820 is the parent node of pkg _0820, pkg _0820 is the parent node of pkg _0820_2, and so on.
As an embodiment, in the step S3, the presenting the first difference set and the second difference set in the second display area may specifically include designing a connection path in the first difference set to generate a first designed connection path table, generating a second designed connection path table from the design path in the second difference set, and presenting the first designed connection path table and the second designed connection path table in the second display area. It should be noted that the first display area and the second display area may be displayed simultaneously, or one of them may be displayed according to a selection of the user.
As an example, the third presentation manner may include a presentation manner, and in step S3, all the connection paths of the design to be detected in the region to be detected that exist in the first difference set are displayed in the same third presentation manner, which is suitable for a scenario in which the connection path of coarse detection or target design is short, and usually includes only two-level or three-level design.
However, in a case that the target design connection path is long, the first difference set may have the target design connection path, but an error may occur locally, and therefore, in order to improve accuracy of the detection result and further accurately locate the position of the connection error, the connection path to be detected in the first difference set may be further determined, as an embodiment, the third presentation manner includes a fourth presentation manner and a fifth presentation manner, the fourth presentation manner is the same as or different from the second presentation manner, and in step S3, the displaying the connection path to be detected existing in the first difference set in the region to be detected in a preset third presentation manner includes:
step S31, matching the to-be-detected design connection paths in the first difference set with the target design connection paths in the target design connection path table;
step S32, determining whether each to-be-detected design connection path in the first difference set exists in a local matching path locally matched with the target design connection path, if yes, displaying a local matching path in the to-be-detected design connection paths according to a fourth presentation mode, and displaying other local paths in the to-be-detected design connection paths in which the local matching path exists according to a fifth presentation mode.
Taking the designed connection paths to be detected in the first difference set as a, B, C, E, X, Y, and Z as an example, if there is one target designed connection path a, B, C, E, X, U, and Z, then a, B, C, E, and X are local matching paths. And displaying the local matching path in a fourth presentation mode, and displaying other local paths in the to-be-detected design connection path with the local matching path in a fifth presentation mode, so that the connection condition of part of the target design path in the first presentation area can be further clearly presented.
As an embodiment, in step S32, displaying a local matching path in the connection paths to be designed according to a fourth presentation manner, where the displaying includes:
step S321, generating a candidate target design local path set based on the target design connection path table, wherein the candidate target design local path at least comprises 3 continuous network identifications;
as an example, the r row in the target design connection path table includes
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For the network identifier corresponding to the nth column of the R-th row, a value range of N is 1 to N, N is the number of identifiers during the target design period, a value range of R is 1 to R, and R is the total number of rows of the connection paths in the target design connection path table, the S321 includes:
step S3211, initializing r =1, X =3, Y = N-2, and leaving the candidate set W empty;
step S3212, the step of
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Adding into W, adding
Figure 471297DEST_PATH_IMAGE012
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Adding the mixture into W;
step S3213, determining whether X is less than N-1 and Y is greater than 2, if yes, setting X = X +1 and Y = Y-1, returning to step S3212, and if X is equal to N-1 and Y is equal to 2, executing step S3214;
step S3214, determining whether R is less than R, if R is less than R, setting R = R +1, X =3, and Y = N-2, returning to execute step S3212, and if R is equal to R, determining current W as the candidate target design local path set.
Step S322, matching the local path of each to-be-detected design connection path in the first difference set with the candidate target design local path of the corresponding design component position in the candidate target design local path set, and if matching is successful, displaying the successfully-matched local matching path in the to-be-detected design connection path according to a fourth presentation manner.
Preferably, the second presentation mode and the fourth presentation mode are the same.
It should be noted that, in some other local paths in the designed connection path to be detected where the local matching path exists, a network identifier group formed by two consecutive network identifiers may also exist to be correct, so that the part may be further judged to further improve the accuracy of the detection result. As an embodiment, the fifth presentation mode includes a sixth presentation mode and a seventh presentation mode, the sixth presentation mode is the same as or different from the second presentation mode, and in the step S32, displaying other local paths in the to-be-detected design connection path having the local matching path according to the fifth presentation mode includes:
step S323, willEach network identifier in other local paths in the design connection path to be detected with the local matching path and the previous network identifier and the next network identifier of the network identifier form a network identifier group to be detected { E }k,Fk}, Ek,FkThe network identifiers are two network identifiers of a kth network identifier group to be detected, the value range of K is 1 to K, and K is the total number of the network identifier group to be detected;
step S324, each network identification group to be detected and the network identification group { P) at the corresponding position in the target design connection path tables,Qs}, Ps,QsMatching two network identifications of the S-th network identification group, wherein the value range of S is 1 to S, and if { E } existsk,Fk}={Ps,QsAnd no E is presentk= Ps,Fk≠QsAnd no E is presentk≠ Ps,Fk=QsThen will { Ek,FkIs presented in a sixth presentation, otherwise, will { E }k,FkIn a seventh presentation.
Preferably, the sixth presentation manner is the same as the second presentation manner.
As an embodiment, the step S3 further includes a step S33, where if there is a network identifier in the connection path to be detected, the connection path and the previous network identifier in the connection path form a part of a local matching path, and the connection path and the next network identifier form a part of a non-local matching path; or, the network identifier and the previous network identifier in the path form a part of a non-local matching path, and form a part of a local matching path with the next network identifier, and then the network identifier is presented in an eighth presentation mode. This makes it possible to clearly display the intersection points where the layout connection is correct and the local connection is incorrect.
It should be noted that names of the component network identifier corresponding to the first display area and the component network identifier in the target design connection path table may be different, and therefore, the system further includes a network identifier mapping table, where the network identifier mapping table is used to store a mapping relationship between the network identifier in the first display area and the network identifier in the target design connection path table, and before executing step S2, the network identifier in the first display area and the network identifier in the target design connection path table are converted and unified based on the network identifier mapping table, that is, the step of obtaining an intersection and a difference is performed after the conversion is unified, so as to improve accuracy of the detection result.
As an embodiment, the first display area further comprises M-1 pin column areas, the network column areas and the pin column areas are alternately arranged, as shown in FIG. 2, and A1, A2, K1, K9 and the like corresponding to Contact Pins are pin identifications. The j-th pin column area is used for displaying pin identifiers connected with a j-th column network and a j + 1-th column network which are at least positioned in the same row, the value range of j is 1 to M-1, and when the processor executes the computer program, the following steps are further realized:
and step S4, presenting all the pin column areas in a first presentation mode.
As an embodiment, the first display area further includes M-1 pin column areas, the network column areas and the pin column areas are arranged alternately, the jth pin column area is used to display pin identifiers connected to the jth network and the jth +1 column network at least in the same row, and a value range of j is 1 to M-1, when the processor executes the computer program, the following steps are further implemented:
and step S5, displaying the detection design connection path successfully matched with the target design connection path in the detection design connection path and the pin column region in the local matching path successfully matched in a ninth display mode, and displaying the detection design connection path unsuccessfully matched and the pin column region in the local path unsuccessfully matched in a tenth display mode, wherein the tenth display mode is the same as or different from the second display mode.
As a preferred embodiment, as shown in fig. 2, the first network column area, i.e. the first column area, includes a second presentation area and a blank area, and the first column area has no first presentation area. The second network column area comprises a first presentation area, a second presentation area and a blank area which are sequentially arranged along the vertical direction. The Mth network column area, namely the tail column area, comprises at least one first presentation area and at least one blank area, a plurality of first presentation areas are arranged in a discrete mode, a plurality of blank areas are arranged in a discrete mode, and the tail column area does not comprise the second presentation area. The network marks in the first display area are continuously arranged along the vertical direction, the network marks in the second display area are continuously arranged along the vertical direction, and the inside of the blank area is also continuously arranged.
As a preferred embodiment, in the second presentation area, if the same identifier is located in multiple design connection paths, the same identifier corresponding to the multiple design connection paths is continuously displayed in the vertical direction. Thus, technicians can observe the test strip conveniently, and the detection efficiency is improved. It should be noted that, in the existing display technology for a design data network structure, the same repeated identification bit is displayed once, and then used as a parent node to display subsequent child nodes one by one, such display is that each design connection path cannot be visually and completely displayed, especially under the conditions that the design connection paths are more and the number of components involved in the design connection paths is more, the whole network matching state cannot be completely presented, but the application can completely and clearly display the network matching structure of each design connection path of the whole system by continuously displaying the same identification corresponding to a plurality of design connection paths along the vertical direction, and is also convenient for observation, thereby improving the detection efficiency and accuracy.
As an embodiment, one or more pin identifier groups are included between the j column network and the j +1 column network in the same row, each pin identifier group includes a j column pin identifier, a preset first spacer and a j +1 column pin identifier, the j column pin identifier is a pin identifier corresponding to the j column network corresponding to the row, and the j +1 column pin identifier is a pin identifier corresponding to the j +1 column network corresponding to the row. The plurality of pin identification groups are horizontally arranged in the same row, and different pin identification groups are separated by a preset second separator. Still taking the example shown in fig. 2, between the PKG _ NET1 of PKG _0820 and the PKG _ NET1 of PKG _0820_2 is through a 10: a10 and B9: b9 are connected by two sets of pins, namely PKG _ NET1 of PKG _0820 is connected by pin a10 of PKG _0820 and pin a10 of PKG _0820_2, and PKG _ NET1 of PKG _0820 is connected by pin B9 of PKG _0820_2 and pin B9 of PKG _0820_ 2. In the example shown in fig. 2, ": the symbol is a preset first separator symbol, and the symbol is a preset second separator symbol, and other symbols can be replaced according to specific requirements. It should be noted that the names of the connection networks corresponding to different designed components may be the same or different, and the names of the connected pins may be the same or different.
The embodiment of the invention can automatically perform bidirectional matching on the network matching structure of the multilevel design connecting path displayed in the first display area and the target design connecting path list, perform bidirectional verification on the target design connecting path, and jointly present the detection result in the first display area and the second display area. The second display area can clearly display the design connecting paths existing in the target design connecting path table but not existing in the area to be detected, and a user can make a design adjustment decision by comparing the first display area with the second display area.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, this is for illustrative purposes only and many of the steps may be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A network interconnection detection system of a target multilevel design connection path is characterized in that:
the network matching structure comprises a first display area, a second display area, a pre-configured target design connection path table, a memory and a processor, wherein the memory and the processor are used for storing a computer program, the first display area is used for displaying a pre-generated network matching structure of a multi-level design connection path and comprises M network column areas; the target design connection path table comprises N network column areas; in the first display area and the target design connection path table, each network column area comprises network identifiers which are arranged at least along the vertical direction and are positioned on the design components corresponding to the network column area, the design component corresponding to the ith column is a father node of the design component corresponding to the (i + 1) th column, the value range of i is 1 to MAX (M, N), and the network identifiers positioned on the same design connection path are positioned on the same row;
when the processor executes the computer program, the following steps are implemented:
step S1, selecting a region to be detected from the first display region according to the design component corresponding to the target design connection path table, and displaying the region which is not selected as the region to be detected in the first display region in a preset first display mode;
step S2, acquiring an intersection of a to-be-detected design connecting path set in the to-be-detected area and a target design connecting path set in the target design connecting path table, a first difference set of the to-be-detected design connecting path set and the target design connecting path set, and a second difference set of the target design connecting path set and the to-be-detected design connecting path set;
step S3, displaying the to-be-detected designed connection paths existing in the to-be-detected area in the intersection in a preset second presentation manner, displaying the to-be-detected designed connection paths existing in the first difference set in the to-be-detected area in a preset third presentation manner, and presenting the first difference set and the second difference set in the second display area.
2. The system of claim 1, wherein:
the third presentation mode includes a presentation mode, and in step S3, all the connection paths to be detected in the area to be detected that exist in the first difference set are displayed in the same third presentation mode.
3. The system of claim 1, wherein:
the third presentation mode includes a fourth presentation mode and a fifth presentation mode, the fourth presentation mode is the same as or different from the second presentation mode, and in the step S3, the displaying the to-be-detected design connection paths existing in the first difference set in the to-be-detected region in a preset third presentation mode includes:
step S31, matching the to-be-detected design connection paths in the first difference set with the target design connection paths in the target design connection path table;
step S32, determining whether each to-be-detected design connection path in the first difference set exists in a local matching path locally matched with the target design connection path, if yes, displaying a local matching path in the to-be-detected design connection paths according to a fourth presentation mode, and displaying other local paths in the to-be-detected design connection paths in which the local matching path exists according to a fifth presentation mode.
4. The system of claim 3, wherein:
in step S32, displaying a local matching path in the to-be-detected design connection path according to a fourth presentation mode, including:
step S321, generating a candidate target design local path set based on the target design connection path table, wherein the candidate target design local path at least comprises 3 continuous network identifications;
step S322, matching the local path of each to-be-detected design connection path in the first difference set with the candidate target design local path of the corresponding design component position in the candidate target design local path set, and if matching is successful, displaying the successfully-matched local matching path in the to-be-detected design connection path according to a fourth presentation manner.
5. The system of claim 3, wherein:
the fifth presentation mode includes a sixth presentation mode and a seventh presentation mode, the sixth presentation mode is the same as or different from the second presentation mode, and in the step S32, displaying other local paths in the to-be-detected design connection path in which the local matching path exists according to the fifth presentation mode includes:
step S323, each network identification in other local paths in the designed connection path to be detected with the local matching path and the previous network identification and the next network identification of the network identification form a network identification group to be detected { E }k,Fk}, Ek,FkThe network identifiers are two network identifiers of a kth network identifier group to be detected, the value range of K is 1 to K, and K is the total number of the network identifier group to be detected;
step S324, each network identification group to be detected and the network identification group { P) at the corresponding position in the target design connection path tables,Qs}, Ps,QsMatching two network identifications of the S-th network identification group, wherein the value range of S is 1 to S, and if { E } existsk,Fk}={Ps,QsAnd no E is presentk= Ps,Fk≠QsAnd no E is presentk≠ Ps,Fk=QsThen will { Ek,FkIs presented in a sixth presentation, otherwise, will { E }k,FkIn a seventh presentation.
6. The system of claim 4, wherein:
the r row of the target design connection path table comprises
Figure 343105DEST_PATH_IMAGE002
Figure 463508DEST_PATH_IMAGE004
For the network identifier corresponding to the nth column of the R-th row, a value range of N is 1 to N, N is the number of identifiers during the target design period, a value range of R is 1 to R, and R is the total number of rows of the connection paths in the target design connection path table, the S321 includes:
step S3211, initializing r =1, X =3, Y = N-2, and leaving the candidate set W empty;
step S3212, the step of
Figure 226934DEST_PATH_IMAGE006
Figure 90985DEST_PATH_IMAGE008
Figure 374198DEST_PATH_IMAGE010
Adding into W, adding
Figure 931082DEST_PATH_IMAGE012
Figure 666956DEST_PATH_IMAGE014
Figure 85431DEST_PATH_IMAGE016
Adding the mixture into W;
step S3213, determining whether X is less than N-1 and Y is greater than 2, if yes, setting X = X +1 and Y = Y-1, returning to step S3212, and if X is equal to N-1 and Y is equal to 2, executing step S3214;
step S3214, determining whether R is less than R, if R is less than R, setting R = R +1, X =3, and Y = N-2, returning to execute step S3212, and if R is equal to R, determining current W as the candidate target design local path set.
7. The system of claim 3, wherein:
step S3 further includes step S33, if there is a network identifier in the connection path to be detected, the connection path and the previous network identifier in the connection path form a part of the local matching path, and the connection path and the next network identifier form a part of the non-local matching path; or, the network identifier and the previous network identifier in the path form a part of a non-local matching path, and form a part of a local matching path with the next network identifier, and then the network identifier is presented in an eighth presentation mode.
8. The system of claim 1, wherein:
the system further includes a network identifier mapping table, where the network identifier mapping table is used to store a mapping relationship between the network identifier in the first display area and the network identifier in the target design connection path table, and the network identifier in the first display area and the network identifier in the target design connection path table are converted and unified based on the network identifier mapping table before the step S2 is executed.
9. The system of claim 1, wherein:
the first display area further comprises M-1 pin column areas, the network column areas and the pin column areas are arranged alternately, the j-th pin column area is used for displaying pin identifiers connected with the j-th column network and the j + 1-th column network which are at least located in the same row, the value range of j is 1-M-1, and when the processor executes the computer program, the following steps are further realized:
and step S4, presenting all the pin column areas in a first presentation mode.
10. The system of claim 3, wherein:
the first display area further comprises M-1 pin column areas, the network column areas and the pin column areas are arranged alternately, the j-th pin column area is used for displaying pin identifiers connected with the j-th column network and the j + 1-th column network which are at least located in the same row, the value range of j is 1-M-1, and when the processor executes the computer program, the following steps are further realized:
and step S5, displaying the detection design connection path successfully matched with the target design connection path in the detection design connection path and the pin column region in the local matching path successfully matched in a ninth display mode, and displaying the detection design connection path unsuccessfully matched and the pin column region in the local path unsuccessfully matched in a tenth display mode, wherein the tenth display mode is the same as or different from the second display mode.
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