CN113990902B

CN113990902B - Display panel and display device

Info

Publication number: CN113990902B
Application number: CN202111207173.7A
Authority: CN
Inventors: 王铸; 石领; 闫政龙
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2026-01-27
Anticipated expiration: 2041-10-15
Also published as: CN113990902A

Abstract

A display panel and a display device are provided, wherein the display panel comprises a display area and a non-display area surrounding the display area, the display area comprises a first display area and a second display area located on at least one side of the first display area, the second display area comprises a first area and a second area which are arranged at intervals, the first area and the second area are arranged along a first direction, the first display area is located between the first area and the second area, the display panel comprises a substrate, a circuit structure layer and a light-emitting structure layer, the circuit structure layer is sequentially stacked on the substrate, the circuit structure layer comprises a plurality of driving circuits and a plurality of data signal lines extending along a second direction, the light-emitting structure layer comprises a plurality of light-emitting elements, the data signal lines are arranged to provide data signals for the driving circuits, the driving circuits are arranged to drive the light-emitting elements to emit light, the first direction and the second direction intersect, the light-emitting elements are located in the first display area and the second display area, and the driving circuits are located in the first area and the second area.

Description

Display panel and display device

Technical Field

The embodiment of the disclosure relates to the technical field of display, in particular to a display panel and a display device.

Background

Organic LIGHT EMITTING Diodes (OLED) and Quantum-dot LIGHT EMITTING Diodes (QLED) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high reaction speed, light weight, flexibility, low cost, and the like. With the continuous development of Display technology, a Flexible Display device (Flexible Display) using an OLED or a QLED as a light emitting element and a thin film transistor (Thin Film Transistor, abbreviated as TFT) for signal control has become a mainstream product in the current Display field.

At present, the concept of a full-screen mobile phone is widely focused on the mobile phone market, and is also a development direction of future mobile phones. In the full-screen mobile phone, the camera can be hidden, so that the front visible area is almost the screen, and a user can obtain a better display effect.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

In a first aspect, the present disclosure provides a display panel including a display region and a non-display region surrounding the display region, the display region including a first display region and a second display region located at least one side of the first display region, the second display region including a first region and a second region disposed at intervals, the first display region being located between the first region and the second region;

The display panel comprises a substrate, a circuit structure layer and a light emitting structure layer, wherein the circuit structure layer and the light emitting structure layer are sequentially stacked on the substrate, the circuit structure layer comprises a plurality of driving circuits and a plurality of data signal lines extending along a second direction, the light emitting structure layer comprises a plurality of light emitting elements, the data signal lines are used for providing data signals for the driving circuits, the driving circuits are used for driving the light emitting elements to emit light, and the first direction and the second direction are intersected;

The light emitting element is located in the first display area and the second display area, and the driving circuit is located in the first area and the second area.

In some possible implementations, a length of the first display area along the second direction is less than or equal to a length of the second display area along the second direction.

In some possible implementations, a length of the driving circuit along the first direction is smaller than a length of a light emitting element connected to the driving circuit along the first direction.

In some possible implementations, the driving circuit includes a first driving circuit and a second driving circuit;

The first driving circuit is connected with a first light-emitting element, the second driving circuit is connected with a second light-emitting element, the first light-emitting element is a light-emitting element positioned in the second display area, and the second light-emitting element is a light-emitting element positioned in the first display area.

In some possible implementations, the driving circuit includes first through seventh transistors, the light emitting element includes an anode, an organic light emitting layer, and a cathode, a second pole of a sixth transistor of the driving circuit is connected to the anode of the light emitting element;

There is no overlapping area between the orthographic projection of the second pole of the sixth transistor of the driving circuit on the substrate and the orthographic projection of the anode of the light emitting element connected with the driving circuit on the substrate.

In some possible implementations, the circuit structure layer further includes a plurality of first switches between the second pole of the sixth transistor of the first driving circuit and the anode of the first light emitting element;

The first driving circuit is connected with the first light-emitting element through the first switching part, the orthographic projection of the first switching part on the substrate is at least partially overlapped with the orthographic projection of the second pole of the sixth transistor of the first driving circuit connected with the first switching part on the substrate, and the orthographic projection of the anode of the first light-emitting element connected with the first switching part on the substrate is at least partially overlapped;

the first transfer portion is made of metal.

In some possible implementations, the circuit structure layer further includes a plurality of second switching portions between a second pole of a sixth transistor of the second driving circuit and an anode of a second light emitting element;

The second driving circuit is connected with the second light-emitting element through the second switching part, the orthographic projection of the second switching part on the substrate is at least partially overlapped with the orthographic projection of the second pole of the sixth transistor of the second driving circuit connected with the second switching part on the substrate, and the orthographic projection of the anode of the second light-emitting element connected with the second connecting part on the substrate is at least partially overlapped;

The second adapting part is made of transparent conductive material.

In some possible implementations, the second transition is disposed in the same layer as the first transition, or in a different layer.

In some possible implementations, when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the second display area further includes a third area, the third area is located between the first area and the second area, and the third area is enclosed outside the first display area;

the first region and the second region are symmetrically disposed along a midline of the third region.

In some possible implementations, the circuit structure layer further includes N columns of first dummy drive circuits;

The first dummy driving circuits with N columns are located in the third area, N is a positive integer greater than or equal to M, and M is the number of columns of light emitting elements in the first display area;

the length of the first dummy driving circuit along the first direction is greater than or equal to the length of the driving circuit along the first direction.

In some possible implementations, the first region and the third region are symmetrically disposed along a midline of the second region.

In some possible implementations, the first region includes S first sub-regions sequentially arranged along a first direction;

adjacent first subregions are spaced apart.

In some possible implementations, the circuit structure layer further includes at least one column of second dummy drive circuits located between adjacent first sub-regions.

In some possible implementations, the second region includes T second sub-regions arranged sequentially along the first direction;

Adjacent second subregions are spaced apart.

In some possible implementations, the circuit structure layer further includes at least one column of third dummy drive circuits located between adjacent second sub-regions.

In some possible implementations, s=t.

In some possible implementations, the data signal line is located in the first region and the second region;

the driving circuits in the same column are connected with the same data signal line.

In some possible implementations, the circuit structure layer further includes a plurality of first power lines extending in a second direction, the first power lines being located within the first region and the second region;

when the driving circuits in the same column are all first driving circuits, the first driving circuits in the same column are connected with the same first power line, and when the driving circuits in the same column comprise the first driving circuits and second driving circuits, the first driving circuits on two sides of the second driving circuits are respectively connected with different first power lines.

In some possible implementations, the circuit structure layer further includes a plurality of second power lines, the second power lines being located on a side of the first power lines remote from the substrate;

the second driving circuits positioned in the same column are connected with the same second power line;

the voltage value of the signal of the second power line is larger than that of the signal of the first power line.

In some possible implementations, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in the first area and the second area and extends along the second direction.

In some possible implementations, when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, each second power line comprises a first power section, a second power section, a third power section, a fourth power section and a fifth power section which are sequentially connected, wherein the first power section, the third power section and the fifth power section extend along the second direction, and the second power section and the fourth power section extend along the first direction;

For each second power line, the first power segment and the fifth power segment are located in the third region;

for a second power line connected to a second driving circuit located in a first region, a second power supply section and a fourth power supply section are located in the first region and the third region, and a third power supply section is located in the first region;

For a second power line connected to a second driving circuit located in a second region, a second power supply section and a fourth power supply section are located in the second region and the third region, and a third power supply section is located in the second region.

In some possible implementations, the display panel further includes a first power supply connection line and a second power supply connection line in the non-display region, the first power supply connection line and the second power supply connection line being disposed in a same layer and in a same layer as the second power supply line;

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power supply connecting lines are respectively connected with two ends of at least one second power supply line positioned in the first area, and the second power supply connecting lines are respectively connected with two ends of at least one second power supply line positioned in the second area;

When the length of the first display area along the second direction is smaller than that of the second display area along the second direction, the first power supply connecting wire is respectively connected with a first power supply section and a fifth power supply section of at least one second power supply wire connected with a second driving circuit located in the first area, and the second power supply connecting wire is respectively connected with a first power supply section and a fifth power supply section of at least one second power supply wire connected with a second driving circuit located in the second area.

In some possible implementations, the display area includes oppositely disposed first and second sides and oppositely disposed third and fourth sides;

The first power supply connecting wire comprises a first connecting section, a second connecting section, a third connecting section, a fourth connecting section and a fifth connecting section which are sequentially connected, wherein the first connecting section and the second connecting section are positioned on the first side of the display area, the third connecting section is positioned on the third side of the display area, and the fourth connecting section and the fifth connecting section are positioned on the second side of the display area;

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting section is connected with one end of at least one second power line positioned in the first area, and the fifth connecting part is connected with the other end of at least one second power line positioned in the first area;

When the length of the first display area along the second direction is smaller than that of the second display area along the second direction, the first connecting section is connected with at least one first power section of a second power line connected with a second driving circuit located in the first area, and the fifth connecting section is connected with at least one fifth power section of the second power line connected with a second driving circuit located in the first area.

In some possible implementations, the second power connection line includes a sixth connection section, a seventh connection section, an eighth connection section, a ninth connection section, and a tenth connection section connected in sequence, the sixth connection section and the seventh connection section being located on a first side of the display area, the eighth connection section being located on a fourth side of the display area, the ninth connection section and the tenth connection section being located on a second side of the display area, the sixth connection section, the eighth connection section, and the tenth connection section extending in the second direction, the seventh connection section and the ninth connection section extending in the first direction;

when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting section is connected with one end of at least one second power line positioned in the second area, and the tenth connecting part is connected with the other end of at least one second power line positioned in the second area;

when the length of the first display area along the second direction is smaller than that of the second display area along the second direction, the sixth connecting section is connected with at least one first power section of a second power line connected with a second driving circuit located in the second area, and the tenth connecting section is connected with at least one fifth power section of the second power line connected with the second driving circuit located in the second area.

In some possible implementations, the circuit structure layer includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer;

The first power line is positioned on the first conductive layer and/or the second conductive layer, the second power line and the first switching part are positioned on the third conductive layer, and the second switching part is positioned on the fourth conductive layer;

the first conductive layer, the second conductive layer and the third conductive layer are metal conductive layers, and the fourth conductive layer is a transparent conductive layer.

In some possible implementations, the circuit structure layer includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer;

The first power line is positioned on the first conductive layer and/or the second conductive layer, and the second power line, the first switching part and the second switching part are positioned on the third conductive layer;

The first conductive layer and the second conductive layer are metal conductive layers.

In some possible implementations, the first display area is a transparent display area;

The resolution of the first display area is the same as the resolution of the second display area, or the resolution of the first display area is different from the resolution of the second display area.

In a second aspect, the present disclosure further provides a display device including the display panel.

In some possible implementations, a light-sensitive sensor is also included and is located within the first display area of the display panel.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

Fig. 1A is a schematic structural diagram of a display panel according to an embodiment of the disclosure;

fig. 1B is another schematic structural diagram of a display panel according to an embodiment of the disclosure;

FIG. 2A is a cross-sectional view of the display panel provided in FIG. 1A;

FIG. 2B is a cross-sectional view of the display panel provided in FIG. 1B;

fig. 3 is a schematic layout view of light emitting elements of a display panel according to an exemplary embodiment;

fig. 4 is a schematic layout view of light emitting elements of a display panel according to another exemplary embodiment;

FIG. 5 is an equivalent circuit schematic diagram of a driving circuit;

FIG. 6 is a timing diagram of the operation of the driving circuit;

fig. 7 is a dimension comparison diagram of a driving circuit and a reference driving circuit in a display panel according to an exemplary embodiment;

Fig. 8A is a schematic structural diagram of a display panel according to an exemplary embodiment;

fig. 8B is a schematic structural diagram of a display panel according to another exemplary embodiment;

fig. 9 is a cross-sectional view of a display panel provided by an exemplary embodiment;

FIG. 10 is a schematic illustration of the arrangement of the first transition in each first sub-area provided by an exemplary embodiment;

fig. 11 is an enlarged view of region R of fig. 10;

Fig. 12A is a schematic structural view of a display panel according to still another exemplary embodiment;

fig. 12B is a schematic structural view of a display panel according to still another exemplary embodiment;

fig. 13 is a schematic structural view of a second power line according to an exemplary embodiment;

fig. 14 is a schematic structural view of a first power connection line according to an exemplary embodiment;

Fig. 15 is a schematic structural diagram of a second power connection line according to an exemplary embodiment.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits a detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may be referred to in general

In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, they may be fixedly connected or detachably connected or integrally connected, they may be mechanically connected or electrically connected, they may be directly connected or indirectly connected through an intermediate member, or they may be in communication with the inside of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

A display panel comprises a transparent display area, a data signal wire needs to bypass the transparent display area for wiring, and the wiring difficulty of the data signal wire is increased.

Fig. 1A is a schematic structural view of a display panel according to an embodiment of the disclosure, fig. 1B is a schematic structural view of a display panel according to an embodiment of the disclosure, fig. 2A is a cross-sectional view of the display panel according to fig. 1A, and fig. 2B is a cross-sectional view of the display panel according to fig. 1B. As shown in fig. 1 and 2, a display panel provided by an embodiment of the present disclosure may include a display area AA and a non-display area (not shown in the drawings) surrounding the display area. The display area AA comprises a first display area A1 and a second display area A2 positioned on at least one side of the first display area A1, wherein the second display area A2 comprises a first area R1 and a second area R2 which are arranged at intervals, the first area R1 and the second area R2 are arranged along a first direction D1, and the first display area A1 is positioned between the first area R1 and the second area R2.

In one exemplary embodiment, the display panel may include a substrate 10 and a circuit structure layer 20 and a light emitting structure layer 30 sequentially stacked on the substrate. The circuit structure layer may include a plurality of driving circuits PA and a plurality of data signal lines D extending in the second direction D2, and the light emitting structure layer may include a plurality of light emitting elements, the data signal lines D being configured to supply data signals to the driving circuits PA, the driving circuits PA being configured to drive the light emitting elements to emit light, the first direction D1 and the second direction D2 intersecting.

The light emitting elements are located in the first display area A1 and the second display area A2, and the driving circuit PA is located in the first region R1 and the second region R2.

In one exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass, metal foil, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

In one exemplary embodiment, the display panel may further include a timing controller, a data driving circuit, a scan driving circuit, and a light emitting driving circuit located in the non-display region. The display panel may further include a plurality of scan signal lines and a plurality of light emitting signal lines located in the display region.

In one exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for a specification of the data driving circuit to the data driving circuit, may supply a clock signal, a scan start signal, etc. suitable for a specification of the scan driving circuit to the scan driving circuit, and may supply a clock signal, an emission stop signal, etc. suitable for a specification of the light emitting driving circuit to the light emitting driving circuit.

In one exemplary embodiment, the data driving circuit may generate the data voltage to be supplied to the data signal line D using the gray value and the control signal received from the timing controller. For example, the data driving circuit may sample the gray value with a clock signal and apply a data voltage corresponding to the gray value to the data signal line in pixel row units.

In one exemplary embodiment, the scan driving circuit may generate the scan signal to be supplied to the scan signal line by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan driving circuit may sequentially supply a scan signal having an on-level pulse to the scan signal lines. The scan driving circuit may be configured in the form of a shift register, and may generate the scan signal in such a manner that the scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal.

In one exemplary embodiment, the light emission driving circuit may generate the emission signal to be supplied to the light emission signal line by receiving a clock signal, an emission stop signal, and the like from the timing controller. The light emission driving circuit may sequentially supply the emission signal having the off-level pulse to the light emission signal lines. For example, the light emission driving circuit may be configured in the form of a shift register, and may generate the light emission signal in such a manner that the light emission stop signal supplied in the form of a cut-off level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal. Each subpixel may be connected to a corresponding data signal line, a corresponding scan signal line, and a corresponding light emitting signal line.

In one exemplary embodiment, the intersection of the first direction and the second direction means that the angle between the first direction and the second direction is about 70 degrees to 90 degrees. The first direction and the second direction may lie in the same plane. For example, the first direction may be a direction parallel to an extending direction of the scan signal line, and the second direction may be a direction parallel to an extending direction of the data signal line. Fig. 1 illustrates an example in which an angle between the first direction and the second direction is 90 degrees.

In one exemplary embodiment, the shape of the light emitting element may be any one or more of triangle, square, rectangle, diamond, trapezoid, parallelogram, pentagon, hexagon, and other polygons in one exemplary embodiment, and the disclosure is not limited herein.

In one exemplary embodiment, fig. 3 is a schematic layout diagram of light emitting elements of a display panel provided in one exemplary embodiment, and fig. 4 is a schematic layout diagram of light emitting elements of a display panel provided in another exemplary embodiment. As shown in fig. 3 and 4, the light emitting element may be any one of a red (R) light emitting element, a green (G) light emitting element, a blue (B) light emitting element, and a white light emitting element, and the disclosure is not limited thereto. When the display panel includes red (R), green (G) and blue (B) light emitting elements, the three light emitting elements may be arranged in a horizontal, vertical or delta arrangement. When the display panel includes red (R), green (G), blue (B) and white light emitting elements, the four light emitting elements may be arranged in a horizontal, vertical or array manner, which is not limited herein. Fig. 3 illustrates an example in which three light emitting elements are arranged horizontally in parallel, and fig. 4 illustrates an example in which four light emitting elements are arranged in an array.

In an exemplary embodiment, the area of each driving circuit may be the same, so that the load of each driving circuit is ensured to be the same, and the risk of abnormal display may be avoided to a greater extent.

In some exemplary embodiments, the display area includes an arcuate display boundary. Illustratively, the boundaries of the display area may be rounded rectangles, which are not limited in any way by the present disclosure.

In one exemplary embodiment, the first display region may be a light transmissive display region. The light-transmitting display area can display or transmit light.

In an exemplary embodiment, the shape of the first display area may be any one or more of rectangular, polygonal, circular, and elliptical in a plane parallel to the display panel. Fig. 1 illustrates a rectangle.

In an exemplary embodiment, the area of the first display region may be larger than the area of the second display region, or the area of the first display region may be equal to the area of the second display region, or the area of the first display region may be smaller than the area of the second display region, fig. 1 is illustrated by taking the example that the area of the first display region is smaller than the area of the second display region.

In one exemplary embodiment, the resolutions of the first display region and the second display region may be the same or may be different. The resolution (Pixels Per Inch, abbreviated as PPI) refers to the number of pixels in a unit area, which may be referred to as pixel density, and the higher the PPI value, the higher the density of the display panel, and the more detailed the display panel.

In one exemplary embodiment, the resolution of the second display region may be greater than the resolution of the first display region, i.e., the number of light emitting elements included in the second display region is greater than the number of light emitting elements included in the first display region in a unit area, or the resolution of the second display region may be less than the resolution of the first display region, i.e., the number of light emitting elements included in the second display region is less than the number of light emitting elements included in the first display region in a unit area, or the resolution of the second display region may be equal to the resolution of the first display region, i.e., the number of light emitting elements included in the second display region is equal to the number of light emitting elements included in the first display region in a unit area.

In one exemplary embodiment, the boundary of the display area AA may include at least one arc shape. Illustratively, as shown in fig. 1, the display area AA may be rounded rectangular in shape, which is not limited in any way by the present disclosure.

In one exemplary embodiment, the driving circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 5 is an equivalent circuit schematic diagram of a driving circuit. As shown in fig. 5, the driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, high-level power supply line VDD, and low-level power supply line VSS).

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the high-level power line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, i.e., a second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the turn-on level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.

In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 with the second electrode.

In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines an amount of driving current flowing between the high-level power supply line VDD and the low-level power supply line VSS according to a potential difference between a control electrode and the first electrode thereof.

In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the driving circuit.

In an exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the high-level power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting element. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When the on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 emit light by forming a driving current path between the high-level power supply line VDD and the low-level power supply line VSS.

In one exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element. When the on-level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 transmits an initialization voltage to the anode of the light emitting element to initialize or release the amount of charge accumulated in the anode of the light emitting element.

In an exemplary embodiment, the cathode of the light emitting element is connected to the low-level power line VSS, the signal of the low-level power line VSS is a low-level signal, and the signal of the high-level power line VDD is a high-level signal continuously supplied. The first scanning signal line S1 is a scanning signal line in the display line driving circuit, the second scanning signal line S2 is a scanning signal line in the previous display line driving circuit, that is, for the nth display line, the first scanning signal line S1 is S (n), the second scanning signal line S2 is S (n-1), the second scanning signal line S2 of the present display line and the first scanning signal line S1 in the previous display line driving circuit are the same signal line, so that signal lines of the display panel can be reduced, and a narrow frame of the display panel can be realized.

In one exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or may be N-type transistors. The transistors of the same type are adopted in the driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to seventh transistors T1 to T7 may include a P-type transistor and an N-type transistor. The P-type transistor is turned on when a low level is applied to the gate electrode of the P-type transistor, and is turned off when a high level is applied to the gate electrode of the P-type transistor. These two levels are also commonly used to turn transistors on and off, respectively, so the higher of the two is also commonly referred to as the high level and the lower is referred to as the low level.

In an exemplary embodiment, the first to seventh transistors T1 to T7 may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the Oxide thin film transistor adopts Oxide (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility, quick charge and the like, and the oxide thin film transistor has the advantages of low leakage current and the like. In an exemplary embodiment, the low-temperature polysilicon thin film transistor and the oxide thin film transistor may be integrated on one display substrate, and a low-temperature polysilicon oxide (Low Temperature Polycrystalline Oxide, abbreviated as LTPO) display substrate may be formed, advantages of both may be utilized, high resolution (Pixel Per Inch, abbreviated as PPI) may be realized, low frequency driving may be performed, power consumption may be reduced, and display quality may be improved.

In one exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, and the initial signal line INIT extend in a first direction, and the low-level power supply line VSS and the high-level power supply line VDD data signal line D extend in a second direction.

In one exemplary embodiment, the light emitting element may be an Organic Light Emitting Diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. The anode is connected with the driving circuit through the via hole, the organic light-emitting layer is connected with the anode, the cathode is connected with the organic light-emitting layer, and the organic light-emitting layer emits light rays with corresponding colors under the driving of the anode and the cathode.

In one exemplary embodiment, the organic light emitting Layer may include a Hole injection Layer (Hole Injection Layer, HIL) a Hole transport Layer (Hole Transport Layer, HTL), an electron blocking Layer (Electron Block Layer, EBL), a light emitting Layer (EMITTING LAYER, EML), a Hole Blocking Layer (HBL), an electron transport Layer (Electron Transport Layer, ETL), and an electron injection Layer (Electron Injection Layer, EIL) stacked. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be common layers connected together, the electron injection layers of all the sub-pixels may be common layers connected together, the hole transport layers of all the sub-pixels may be common layers connected together, the hole blocking layers of all the sub-pixels may be common layers connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In an exemplary embodiment, the anode may be made of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In an exemplary embodiment, the cathode may employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

Fig. 6 is a timing diagram of the operation of the driving circuit. The exemplary embodiment of the present disclosure will be described below by way of an operation of the driving circuit illustrated in fig. 5, which includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C, and 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, high-level power supply line VDD, and low-level power supply line VSS), and the 7 transistors are P-type transistors.

In one exemplary embodiment, the operation of the driving circuit may include:

The first stage, called a reset stage, is where the signal of the second scanning signal line S2 is a low level signal, and the signals of the first scanning signal line S1 and the light emitting signal line E are high level signals. The signal of the second scanning signal line S2 is a low level signal, so that the first transistor T1 is turned on, the signal of the initial signal line INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal line S1 and the light emitting signal line E are high level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage.

In the second phase, referred to as a data writing phase or a threshold compensation phase, the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs a data voltage. At this stage, since the second terminal of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low level signal to turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on such that the data voltage outputted from the data signal line D is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and a difference between the data voltage outputted from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, the voltage of the second terminal (second node N2) of the storage capacitor C is vd—vth|, vd is the data voltage outputted from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on to supply the initial voltage of the initial signal line INIT to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, empty the pre-stored voltage therein, complete the initialization, and ensure that the OLED does not emit light. The signal of the second scanning signal line S2 is a high level signal, and turns off the first transistor T1. The signal of the light-emitting signal line E is a high level signal, and turns off the fifth transistor T5 and the sixth transistor T6.

The third stage, referred to as a light-emitting stage, is that the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light emitting signal line E is a low level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage outputted from the high level power supply line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, thereby driving the OLED to emit light.

During driving of the driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata- |vth|, the driving current of the third transistor T3 is:

I=K*(Vgs-Vth)²＝K*[(Vdd-Vd+|Vth|)-Vth]²＝K*[(Vdd-Vd]²

where I is a driving current flowing through the third transistor T3, that is, a driving current for driving the OLED, K is a constant, vgs is a voltage difference between the gate electrode and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vd is a data voltage output from the data signal line D, and Vdd is a power supply voltage output from the high-level power supply line Vdd.

The display panel comprises a display area and a non-display area surrounding the display area, wherein the display area comprises a first display area and a second display area located on at least one side of the first display area, the second display area comprises a first area and a second area which are arranged at intervals, the first area and the second area are arranged along a first direction, the first display area is located between the first area and the second area, the display panel comprises a substrate, a circuit structure layer and a light-emitting structure layer which are sequentially stacked on the substrate, the circuit structure layer comprises a plurality of driving circuits and a plurality of data signal lines extending along a second direction, the light-emitting structure layer comprises a plurality of light-emitting elements, the data signal lines are arranged to provide data signals for the driving circuits, the driving circuits are arranged to drive the light-emitting elements to emit light, the first direction and the second direction intersect, the light-emitting elements are located in the first display area and the second display area, and the driving circuits are located in the first area and the second area. According to the embodiment of the disclosure, the driving circuit is located in the first area and the second area, so that the data signal lines do not need to avoid the first display area, and the layout of the data signal lines is simplified.

In one exemplary embodiment, the length of the first display area A1 along the second direction D2 is less than or equal to the length of the second display area A2 along the second direction D2. Fig. 1A and 2A illustrate an example in which the length of the first display area A1 along the second direction D2 is smaller than the length of the second display area A2 along the second direction D2. Fig. 1B and 2B illustrate an example in which the length of the first display area A1 along the second direction D2 is equal to the length of the second display area A2 along the second direction D2.

In an exemplary embodiment, the length of any one of the driving circuits in the first direction is smaller than the length of the light emitting element to which the driving circuit is connected in the first direction.

In one exemplary embodiment, fig. 7 is a dimension comparison diagram of a driving circuit and a reference driving circuit in a display panel according to one exemplary embodiment. Wherein the reference driving circuit CPA refers to a driving circuit in the display panel of all areas of the second display area. The exemplary embodiment provides a driving circuit in a display panel, which is obtained by performing equal-proportion compression on a reference driving circuit CPA. The equal-ratio compression may include equal-ratio compression in a first direction or equal-ratio compression in row and column directions. As shown in fig. 7, l3=l1×k, l4=l2. Wherein l1 is the length of the reference driving circuit CPA along the first direction, l2 is the length of the reference driving circuit CPA along the second direction, l3 is the length of the driving circuit PA along the first direction, l4 is the length of the driving circuit PA along the second direction, k is the compression ratio, 0< k <1.

In an exemplary embodiment, the length of the light emitting element along the first direction is X micrometers, and the length of the driving circuit along the first direction is X-a micrometers, wherein the value of a is determined according to the size of the first display area.

In one exemplary embodiment, fig. 8A is a schematic structural diagram of a display panel provided in one exemplary embodiment, and fig. 8B is a schematic structural diagram of a display panel provided in another exemplary embodiment. As shown in fig. 8, the driving circuit may include a first driving circuit PA1 and a second driving circuit PA2. The first driving circuit PA1 is connected to the first light emitting element, and the second driving circuit PA2 is connected to the second light emitting element. The first light-emitting element is a light-emitting element located in the second display area, and the second light-emitting element is a light-emitting element located in the first display area. Fig. 8A illustrates an example in which the length of the first display area A1 along the second direction D2 is smaller than the length of the second display area A2 along the second direction D2. Fig. 8B illustrates an example in which the length of the first display area A1 along the second direction D2 is equal to the length of the second display area A2 along the second direction D2.

In one exemplary embodiment, fig. 9 is a cross-sectional view of a display panel provided by one exemplary embodiment. As shown in fig. 9, there is no overlapping area between the front projection of the second pole 64 of the sixth transistor T6 of the driving circuit on the substrate 10 and the front projection of the anode 31 of the light emitting element connected to the driving circuit on the substrate 10.

In an exemplary embodiment, the circuit structure layer 20 may further include an active layer 61, a gate electrode 62, and a first electrode 63 of the sixth transistor T6, first and second plates C1 and C2 of the storage capacitor, and a high-level power line VDD.

In one exemplary embodiment, the light emitting structure layer 30 may further include a pixel defining layer 34, an organic light emitting layer 32, and a cathode 33.

In one exemplary embodiment, the pixel defining layer may be made of an organic material such as polyimide, acryl, or polyethylene terephthalate.

In an exemplary embodiment, as shown in fig. 9, the circuit structure layer 20 further includes a plurality of first switching parts VL1, and the first switching parts VL1 are located between the second pole 61 of the sixth transistor of the first driving circuit and the anode 31 of the first light emitting element.

In an exemplary embodiment, the first driving circuit is connected to the first light emitting element through a first connection portion, and an orthographic projection of the first connection portion on the substrate overlaps at least a portion of an orthographic projection of a second pole of a sixth transistor of the first driving circuit connected to the first connection portion on the substrate, and an orthographic projection of an anode of the first light emitting element connected to the first connection portion overlaps at least a portion of the orthographic projection on the substrate.

In one exemplary embodiment, the first transfer portion may be made of a material including metal. The first switching part may be made of metal to reduce impedance and ensure brightness uniformity of the second display area.

In one exemplary embodiment, the circuit structure layer may further include a plurality of second switching parts between the second poles of the sixth transistors of the second driving circuit and the anodes of the second light emitting elements.

In an exemplary embodiment, the second driving circuit is connected to the second light emitting element through a second switching portion, and an orthographic projection of the second switching portion on the substrate is at least partially overlapped with an orthographic projection of a second pole of a sixth transistor of the second driving circuit connected to the second switching portion on the substrate, and an orthographic projection of an anode of the second light emitting element connected to the second connecting portion on the substrate is at least partially overlapped.

In one exemplary embodiment, the second adapter portion is made of a material including a transparent conductive material. The second switching part is made of transparent conductive material, so that the light transmittance of the second display area can be ensured.

In an exemplary embodiment, the second transfer portion is disposed in the same layer as the first transfer portion, or in a different layer, which is not limited in this disclosure.

In an exemplary embodiment, as shown in fig. 1A and 2A, when the length of the first display area A1 along the second direction is smaller than the length of the second display area A2 along the second direction, the second display area A2 may further include a third region R3, the third region R3 being located between the first region R1 and the second region R2, and the third region R3 being enclosed outside the first display area A1.

In an exemplary embodiment, the first region R1 and the second region R2 are symmetrically disposed along a center line of the third region R3.

In one exemplary embodiment, as shown in fig. 2A and 8A, the circuit structure layer may further include N columns of the first dummy driving circuits DPA1. The N columns of the first dummy driving circuits are located in the third region R3, where N is a positive integer greater than or equal to M, and M is a column number of the light emitting elements in the first display region.

In one exemplary embodiment, the first dummy driving circuit of each column is not connected to any light emitting element. The display effect of the display panel is improved by arranging the first dummy driving circuit to ensure the uniformity of driving display by the driving circuit. The value of N may be determined according to the size of the first display area in the display panel, which is not limited in the present disclosure.

In one exemplary embodiment, a length of the first dummy driving circuit in the first direction is greater than or equal to a length of the driving circuit in the first direction. Illustratively, the length of the first dummy drive circuit in the first direction is equal to the length of the drive circuit in the first direction. The length of the first dummy driving circuit along the first direction is equal to the length of the driving circuit along the first direction, so that the manufacturing process of the display panel can be simplified, and the manufacturing cost of the display panel can be saved.

In an exemplary embodiment, as shown in fig. 8A and 8B, the first region includes S first sub-regions r1_1 to r1_s sequentially arranged along the first direction, wherein adjacent first sub-regions are spaced apart, S is a positive integer greater than or equal to 2, and fig. 8 is illustrated by taking s=3 as an example.

In an exemplary embodiment, the number of columns of driving circuits included in each first sub-region may be the same.

In an exemplary embodiment, fig. 10 is a schematic layout diagram of the first switching part in each first sub-area provided in an exemplary embodiment, and fig. 11 is an enlarged view of the area R in fig. 10, and as shown in fig. 8, 10 and 11, the circuit structure layer may further include at least one column of second dummy driving circuits DPA2 located between adjacent first sub-areas.

In an exemplary embodiment, the second dummy driving circuit of each column is not connected to any light emitting element. According to the display device, the second dummy driving circuit is arranged between the adjacent first subareas, so that the uniformity of the deviation of the driving circuit and the light-emitting element connected with the driving circuit can be better maintained, the uniformity of display of the display panel can be ensured, and the display effect of the display panel is improved. Each first sub-region and the adjacent second dummy driving circuit can be used as a circulation unit, and the sizes and the arrangement of all the first switching parts in each circulation unit are the same, so that the manufacturing process of the display panel can be simplified, the realization of the first switching parts can be facilitated, and the overlong sizes of the first switching parts are avoided.

In an exemplary embodiment, as shown in fig. 8A and 8B, the second region R2 includes T second sub-regions r2_1 to r2_t sequentially arranged in the first direction, wherein adjacent second sub-regions are spaced apart, and T is a positive integer greater than or equal to 2. Fig. 8 illustrates an example of t=3.

In some possible implementations, the circuit structure layer further includes at least one column of third dummy driving circuits DPA3 located between adjacent second sub-regions.

In an exemplary embodiment, the third dummy driving circuit of each column is not connected to any light emitting element. According to the display device, the third dummy driving circuit is arranged between the adjacent first subareas, so that the uniformity of the deviation of the driving circuit and the light-emitting element connected with the driving circuit can be better maintained, the uniformity of display of the display panel can be ensured, and the display effect of the display panel is improved. Referring to fig. 10 and 11, each second sub-region and the adjacent third dummy driving circuit may be used as a circulation unit, and the sizes and arrangements of all the first switching parts in each circulation unit are the same, so that not only can the manufacturing process of the display panel be simplified, but also the realization of the first switching parts can be facilitated, and the overlong size of the first switching parts is avoided.

In one exemplary embodiment, s=t.

In one exemplary embodiment, as shown in fig. 1, the data signal line D may be located at the first region R1 and the second region R2. The driving circuits in the same column are connected with the same data signal line.

In one exemplary embodiment, fig. 12A is a schematic structural view of a display panel provided in yet another exemplary embodiment, and fig. 12B is a schematic structural view of a display panel provided in yet another exemplary embodiment. As shown in fig. 12A and 12B, the circuit structure layer further includes a plurality of first power lines VDD1 extending in the second direction, and the first power lines VDD1 are located in the first region R1 and the second region R2. Fig. 12A and 12B illustrate s=2, and t=2 as an example. Fig. 12A illustrates an example in which the length of the first display area along the second direction is smaller than the length of the second display area along the second direction. Fig. 12B illustrates an example in which the length of the first display area along the second direction is equal to the length of the second display area along the second direction.

In an exemplary embodiment, when the driving circuits in the same column are all first driving circuits, the first driving circuits in the same column are connected to the same first power line, and when the driving circuits in the same column include the first driving circuits and the second driving circuits, the first driving circuits on both sides of the second driving circuits are respectively connected to different first power lines.

In one exemplary embodiment, the first power line is a high-level power line to which the first driving circuit is connected.

In an exemplary embodiment, as shown in fig. 12, the circuit structure layer may further include a plurality of second power lines VDD2, the second power lines VDD2 being located at a side of the first power line VDD1 remote from the substrate 10.

In one exemplary embodiment, the second power line VDD2 is a high-level power line to which the second driving circuit is connected.

In an exemplary embodiment, as shown in fig. 12A and 12B, the second driving circuits located in the same column are connected to the same second power line.

In one exemplary embodiment, the voltage value of the signal of the second power line VDD2 is greater than the voltage value of the signal of the first power line VDD 1.

In an exemplary embodiment, the second driving circuit is connected to the second light emitting element through the second switching portion, the second switching portion is made of a transparent conductive material, and due to the fact that the resistance of the transparent conductive material is large, display of the first light emitting element and display of the second light emitting element are possibly uneven.

In one exemplary embodiment, as shown in fig. 12B, when the length of the first display area in the second direction is equal to the length of the second display area in the second direction, the second power line is located in the first region R1 and the second region and extends in the second direction.

In an exemplary embodiment, fig. 13 is a schematic structural diagram of a second power line according to an exemplary embodiment. As shown in fig. 12A and 13, when the length of the first display area in the second direction is smaller than the length of the second display area in the second direction, each of the second power lines includes a first power supply segment Va, a second power supply segment Vb, a third power supply segment Vc, a fourth power supply segment Vd, and a fifth power supply segment Ve, which are sequentially connected, the first power supply segment Va, the third power supply segment Vc, and the fifth power supply segment Ve extending in the second direction, and the second power supply segment Vb and the fourth power supply segment Vd extending in the first direction.

In one exemplary embodiment, the first power supply segment Va and the fifth power supply segment Ve are located in the third region for each of the second power supply lines.

In one exemplary embodiment, for the second power line connected to the second driving circuit located in the first region, the second power segment Vb and the fourth power segment Vd are located in the third region and the first region, and the third power segment Vc is located in the first region.

In one exemplary embodiment, for the second power line connected to the second driving circuit located in the second region, the second power segment Vb and the fourth power segment Vd are located in the second region and the third region, and the third power segment Vc is located in the second region.

In an exemplary embodiment, fig. 14 is a schematic structural diagram of a first power connection line provided in an exemplary embodiment, and fig. 15 is a schematic structural diagram of a second power connection line provided in an exemplary embodiment. As shown in fig. 12, 14 and 15, the display panel may further include a first power connection line L1 and a second power connection line L2 located in the non-display region.

In one exemplary embodiment, the first and second power supply connection lines L1 and L2 may be disposed in the same layer and in the same layer as the second power supply line.

In an exemplary embodiment, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power connection lines L1 are respectively connected to two ends of at least one second power line located in the first area, and the second power connection lines L2 are respectively connected to two ends of at least one second power line located in the second area.

In one exemplary embodiment, the first power connection line L1 may be connected to a first power section and a fifth power section of at least one second power line connected to the second driving circuit located in the first region, respectively. The second power connection line L2 is connected to the first power section and the fifth power section of at least one second power line connected to the second driving circuit located in the second area, respectively.

In one exemplary embodiment, the display area includes first and second sides disposed opposite each other and third and fourth sides disposed opposite each other.

In one exemplary embodiment, as shown in fig. 14, the first power connection line L1 includes a first connection section La, a second connection section Lb, a third connection section Lc, a fourth connection section Ld, and a fifth connection section Le, which are sequentially connected.

In one exemplary embodiment, the first connection section La and the second connection section Lb are located at a first side of the display area, the third connection section Lc is located at a third side of the display area, and the fourth connection section Ld and the fifth connection section Le are located at a second side of the display area.

In one exemplary embodiment, the first, third and fifth connection sections La, lc and Le extend in the second direction, and the second and fourth connection sections Lb and Ld extend in the first direction.

In an exemplary embodiment, as shown in fig. 12B, when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connection section is connected to one end of at least one second power line located in the first area, and the fifth connection section is connected to the other end of at least one second power line located in the first area.

In one exemplary embodiment, when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the first connection section La is connected to the first power section of at least one second power line connected to the second driving circuit located in the first area, and the fifth connection section Le is connected to the fifth power section of at least one second power line connected to the second driving circuit located in the first area.

In an exemplary embodiment, as shown in fig. 15, the second power connection line includes a sixth connection section Lf, a seventh connection section Lg, an eighth connection section Lh, a ninth connection section Li, and a tenth connection section Lj, which are connected in order.

In one exemplary embodiment, the sixth connection section Lf and the seventh connection section Lg are positioned at a first side of the display area, the eighth connection section Lh is positioned at a fourth side of the display area, and the ninth connection section Li and the tenth connection section Lj are positioned at a second side of the display area.

In one exemplary embodiment, the sixth, eighth and tenth connection sections Lf, lh and Lj extend in the second direction, and the seventh and ninth connection sections Lg and Li extend in the first direction.

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting section is connected with one end of at least one second power line positioned in the second area, and the tenth connecting part is connected with the other end of at least one second power line positioned in the second area.

In one exemplary embodiment, when the length of the first display area along the second direction is smaller than the length of the second display area along the second direction, the sixth connection section Lf is connected to the first power section of at least one second power line connected to the second driving circuit located in the second area, and the tenth connection section Lj is connected to the fifth power section of at least one second power line connected to the second driving circuit located in the second area.

In one exemplary embodiment, the circuit structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer. The first power line is positioned on the first conductive layer and/or the second conductive layer, the second power line and the first switching part are positioned on the third conductive layer, and the second switching part is positioned on the fourth conductive layer.

In one exemplary embodiment, the first, second, and third conductive layers may be metal conductive layers.

In one exemplary embodiment, the fourth conductive layer may be a transparent conductive layer.

In one exemplary embodiment, the circuit structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer, and the circuit structure layer may further include a buffer layer, an active layer, a fourth insulating layer, a first metal layer, a fifth insulating layer, a second metal layer, and a sixth insulating layer disposed between the substrate and the first conductive layer and sequentially stacked on the substrate.

In one exemplary embodiment, the active layer may include an active layer of a plurality of transistors, and the first metal layer may include gate electrodes of the plurality of transistors and a first plate of a storage capacitor. The second metal layer may include a second plate of the plurality of transistors. The conductive layer may further include first and second poles of a plurality of transistors.

In an exemplary embodiment, the circuit structure layer may further include a planarization layer disposed on a side of the fourth conductive layer remote from the substrate.

In one exemplary embodiment, as shown in FIG. 9, the circuit structure layer may further include a first conductive layer, a first insulating layer 26, a second conductive layer, a second insulating layer 27, and a third conductive layer. The first power line VDD1 is located in the first conductive layer and/or the second conductive layer, and the second power line, the first switching portion VL1 and the second switching portion are located in the third conductive layer.

In one exemplary embodiment, the first conductive layer and the second conductive layer are metallic conductive layers.

In an exemplary embodiment, the circuit structure layer may further include a buffer layer 22, an active layer, a third insulating layer 23, a first metal layer, a fourth insulating layer 24, a second metal layer, and a fifth insulating layer 25 disposed between the substrate and the first conductive layer and sequentially stacked on the substrate 10.

In one exemplary embodiment, the active layer may include active layers of a plurality of transistors, and the first metal layer may include gate electrodes of the plurality of transistors and a first plate C1 of a storage capacitor. The second metal layer may include a second plate C2 of the plurality of transistors.

In one exemplary embodiment, the first conductive layer may further include first and second poles of a plurality of transistors.

In an exemplary embodiment, the circuit structure layer may further include a planarization layer 28 disposed on a side of the third conductive layer remote from the substrate.

In one exemplary embodiment, the active layer may be an amorphous silicon layer, a polysilicon layer, or may be a metal oxide layer. The metal oxide layer may be formed using an oxide containing indium and tin, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium and tin, an oxide containing indium and zinc, an oxide containing silicon and indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, or may be a double layer, or may be a plurality of layers.

In an exemplary embodiment, the first metal layer, the second metal layer, the first conductive layer, and the second conductive layer may be made of any one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), may be a single-layer structure, or a multi-layer composite structure such as Mo/Cu/Mo, or the like.

In one exemplary embodiment, the first, second, third, fourth, fifth, and sixth insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

In an exemplary embodiment, the planarization layer may use an organic material such as polyimide, acryl, or polyethylene terephthalate.

In one exemplary embodiment, as shown in fig. 9, the display panel may further include an encapsulation layer 40 and spacers 50.

In one exemplary embodiment, the encapsulation layer 40 is disposed on a side of the light emitting structure layer 30 away from the substrate 10, and the spacer 50 is disposed on a side of the encapsulation layer 40 away from the substrate 10.

In one exemplary embodiment, the encapsulation layer 40 may take a laminate structure of inorganic material/organic material/inorganic material, with the organic material layer disposed between two inorganic material layers. The packaging layer may include a first packaging layer, a second packaging layer and a third packaging layer, which are stacked, wherein the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is disposed between the first packaging layer and the third packaging layer, so that external moisture cannot enter the light emitting device.

The embodiment of the disclosure also provides a display device, which comprises a display panel.

In an exemplary embodiment, the display device may be any product or component having a display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, and a display. The drawings in the present disclosure relate only to structures to which embodiments of the present disclosure relate, and other structures may be referred to as general designs.

The display panel provided by any one of the foregoing embodiments has similar implementation principles and implementation effects, and is not described herein.

In one exemplary embodiment, the display device may further include a light sensing sensor, and the light sensing sensor is located in the first display area of the display panel.

In one exemplary embodiment, the first display region may be rectangular, and an area of an orthographic projection of the light-sensing sensor on the substrate may be less than or equal to an area of an inscribed circle of the first display region. That is, the size of the region where the light sensing sensor is located may be less than or equal to the size of the inscribed circle of the first display region. For example, the size of the area where the light sensing sensor is located is equal to the size of the inscribed circle of the first display area, that is, the shape of the area where the light sensing sensor is located may be a circle, and correspondingly, the area where the light sensing sensor is located may also be referred to as a light hole.

In the drawings for describing embodiments of the present disclosure, thicknesses and dimensions of layers or microstructures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

While the embodiments disclosed in the present disclosure are described above, the embodiments are only employed for facilitating understanding of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and changes in form and details can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is to be determined by the appended claims.

Claims

1. A display panel, comprising: a display area and a non-display area surrounding the display area, characterized in that: the display area comprises: a first display area and a second display area located on at least one side of the first display area; the second display area comprises: a first region and a second region spaced apart, the first region and the second region being arranged along a first direction, and the first display area being located between the first region and the second region;

The display panel includes: a substrate and a circuit structure layer and a light-emitting structure layer sequentially stacked on the substrate; the circuit structure layer includes: a plurality of driving circuits and a plurality of data signal lines extending along a second direction; the light-emitting structure layer includes: a plurality of light-emitting elements; the data signal lines are configured to provide data signals to the driving circuits, the driving circuits are configured to drive the light-emitting elements to emit light, and the first direction and the second direction intersect;

The light-emitting element is located in the first display area and the second display area, and the driving circuit is located in the first area and the second area; the data signal line is located in the first area and the second area, and the area of the display panel other than the first area and the second area is not provided with driving circuit and data signal line.

2. The display panel according to claim 1, wherein the length of the first display area along the second direction is less than or equal to the length of the second display area along the second direction.

3. The display panel according to claim 1 or 2, wherein the length of the driving circuit along the first direction is less than the length of the light-emitting element connected to the driving circuit along the first direction.

4. The display panel according to claim 3, wherein the driving circuit comprises: a first driving circuit and a second driving circuit;

The first driving circuit is connected to the first light-emitting element, and the second driving circuit is connected to the second light-emitting element. The first light-emitting element is located in the second display area, and the second light-emitting element is located in the first display area.

5. The display panel according to claim 4, wherein the driving circuit comprises: a first transistor to a seventh transistor; the light-emitting element comprises: an anode, an organic light-emitting layer, and a cathode; and the second electrode of the sixth transistor of the driving circuit is connected to the anode of the light-emitting element;

The orthographic projection of the second electrode of the sixth transistor of the driving circuit onto the substrate does not overlap with the orthographic projection of the anode of the light-emitting element connected to the driving circuit onto the substrate.

6. The display panel according to claim 5, wherein the circuit structure layer further comprises: a plurality of first transition portions, wherein the first transition portions are located between the second electrode of the sixth transistor of the first driving circuit and the anode of the first light-emitting element;

The first driving circuit is connected to the first light-emitting element through the first adapter. The orthographic projection of the first adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the first driving circuit connected to the first adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the first light-emitting element connected to the first connection on the substrate.

The materials used to manufacture the first adapter include: metal.

7. The display panel according to claim 6, wherein the circuit structure layer further comprises: a plurality of second transition portions, the second transition portions being located between the second electrode of the sixth transistor of the second driving circuit and the anode of the second light-emitting element;

The second driving circuit is connected to the second light-emitting element through the second adapter. The orthographic projection of the second adapter on the substrate at least partially overlaps with the orthographic projection of the second electrode of the sixth transistor of the second driving circuit connected to the second adapter on the substrate, and at least partially overlaps with the orthographic projection of the anode of the second light-emitting element connected to the second connection on the substrate.

The materials used to manufacture the second adapter include: transparent conductive materials.

8. The display panel according to claim 7, wherein the second transition portion is disposed on the same layer as the first transition portion, or disposed on a different layer.

9. The display panel according to claim 7, wherein when the length of the first display area along the second direction is less than the length of the second display area along the second direction, the second display area further includes: a third region, the third region being located between the first region and the second region, the third region surrounding the first display area;

The first region and the second region are symmetrically arranged along the centerline of the third region.

10. The display panel according to claim 9, wherein the circuit structure layer further comprises: N columns of first dummy driving circuits;

The N columns of the first dummy driving circuits are located in the third region, where N is a positive integer greater than or equal to M, and M is the number of columns of light-emitting elements in the first display area;

11. The display panel according to claim 2, wherein the first region comprises: S first sub-regions arranged sequentially along a first direction;

The interval between adjacent first sub-regions is set.

12. The display panel according to claim 11, wherein the circuit structure layer further comprises: at least one column of second dummy driving circuits located between adjacent first sub-regions.

13. The display panel according to claim 2, wherein the second region comprises: T second sub-regions arranged sequentially along a first direction;

The interval between adjacent second sub-regions is set.

14. The display panel according to claim 13, wherein the circuit structure layer further comprises: at least one column of third dummy driving circuits located between adjacent second sub-regions.

15. The display panel according to claim 13, wherein S=T.

16. The display panel according to claim 2, wherein the driving circuits located in the same column are connected to the same data signal line.

17. The display panel according to claim 9, wherein the circuit structure layer further comprises: a plurality of first power lines extending along a second direction; the first power lines are located in the first region and the second region;

When all the drive circuits in the same column are first drive circuits, the first drive circuits in the same column are connected to the same first power line. When the drive circuits in the same column include a first drive circuit and a second drive circuit, the first drive circuits located on both sides of the second drive circuit are connected to different first power lines.

18. The display panel according to claim 17, wherein the circuit structure layer further comprises: a plurality of second power lines; the second power lines are located on the side of the first power lines away from the substrate;

The second drive circuits located in the same column are connected to the same second power supply line;

The voltage value of the signal on the second power line is greater than the voltage value of the signal on the first power line.

19. The display panel according to claim 18, wherein when the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the second power line is located in the first area and the second area, and extends along the second direction.

20. The display panel according to claim 18, wherein when the length of the first display area along the second direction is less than the length of the second display area along the second direction, each second power line comprises: a first power segment, a second power segment, a third power segment, a fourth power segment, and a fifth power segment connected in sequence; the first power segment, the third power segment, and the fifth power segment extend along the second direction, and the second power segment and the fourth power segment extend along the first direction;

For the second power line connected to the second drive circuit located in the first region, the second power segment and the fourth power segment are located in the first region and the third region, and the third power segment is located in the first region;

For the second power line connected to the second drive circuit located in the second region, the second power segment and the fourth power segment are located in the second region and the third region, and the third power segment is located in the second region.

21. The display panel according to claim 19 or 20, wherein the display panel further comprises: a first power connection line and a second power connection line located in the non-display area; the first power connection line and the second power connection line are disposed on the same layer, and are disposed on the same layer as the second power line;

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first power connection line is connected to both ends of at least one second power line located in the first area, and the second power connection line is connected to both ends of at least one second power line located in the second area.

When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the first region; the second power connection line is respectively connected to the first power segment and the fifth power segment of a second power line that is connected to the second driving circuit located in the second region.

22. The display panel according to claim 21, wherein the display area comprises: a first side and a second side disposed opposite to each other, and a third side and a fourth side disposed opposite to each other;

The first power connection cable includes: a first connection segment, a second connection segment, a third connection segment, a fourth connection segment, and a fifth connection segment connected in sequence; the first connection segment and the second connection segment are located on a first side of the display area, the third connection segment is located on a third side of the display area, and the fourth connection segment and the fifth connection segment are located on a second side of the display area; the first connection segment, the third connection segment, and the fifth connection segment extend along a second direction, and the second connection segment and the fourth connection segment extend along a first direction;

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the first connecting segment is connected to one end of at least one second power line located in the first area, and the fifth connecting segment is connected to the other end of at least one second power line located in the first area.

When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the first connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the first region, and the fifth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the first region.

23. The display panel according to claim 21, wherein the second power connection line comprises: a sixth connection segment, a seventh connection segment, an eighth connection segment, a ninth connection segment, and a tenth connection segment connected in sequence; the sixth connection segment and the seventh connection segment are located on a first side of the display area, the eighth connection segment is located on a fourth side of the display area, and the ninth connection segment and the tenth connection segment are located on a second side of the display area; the sixth connection segment, the eighth connection segment, and the tenth connection segment extend along a second direction, and the seventh connection segment and the ninth connection segment extend along a first direction;

When the length of the first display area along the second direction is equal to the length of the second display area along the second direction, the sixth connecting segment is connected to one end of at least one second power line located in the second region, and the tenth connecting segment is connected to the other end of at least one second power line located in the second region.

When the length of the first display area along the second direction is less than the length of the second display area along the second direction, the sixth connecting segment is connected to at least one first power segment of a second power line connected to a second driving circuit located in the second region, and the tenth connecting segment is connected to at least one fifth power segment of a second power line connected to a second driving circuit located in the second region.

24. The display panel according to claim 21, wherein the circuit structure layer comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer;

The first power line is located in the first conductive layer and/or the second conductive layer; the second power line and the first adapter are located in the third conductive layer; the second adapter is located in the fourth conductive layer;

The first conductive layer, the second conductive layer, and the third conductive layer are metallic conductive layers, and the fourth conductive layer is a transparent conductive layer.

25. The display panel according to claim 21, wherein the circuit structure layer comprises: a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer;

The first power line is located in the first conductive layer and/or the second conductive layer; the second power line, the first adapter, and the second adapter are located in the third conductive layer;

The first conductive layer and the second conductive layer are metallic conductive layers.

26. The display panel according to claim 1, wherein the first display area is a transparent display area;

27. A display device, characterized in that it comprises: a display panel as described in any one of claims 1 to 26.

28. The display device according to claim 27, further comprising: a photosensor, wherein the photosensor is located within a first display area of the display panel.