CN115941776B - Dynamic adjustment method, device, electronic device and storage medium for port arbitration - Google Patents
Dynamic adjustment method, device, electronic device and storage medium for port arbitration Download PDFInfo
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- CN115941776B CN115941776B CN202211364381.2A CN202211364381A CN115941776B CN 115941776 B CN115941776 B CN 115941776B CN 202211364381 A CN202211364381 A CN 202211364381A CN 115941776 B CN115941776 B CN 115941776B
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Abstract
The invention provides a dynamic adjustment method and device for port arbitration, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring a port arbitration table of a target chip; initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip; transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained; and adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion. The invention can dynamically adjust the arbitration priority of each port and improve the utilization rate of the PCIe bus.
Description
Technical Field
The present invention relates to the field of computer servers, and in particular, to a method and apparatus for dynamically adjusting port arbitration, an electronic device, and a storage medium.
Background
To achieve the increasing demands for functionality and services, servers are increasingly being equipped with PCIe devices, but the PCIe bus of the processor CPU is limited and the number of extensible PCIe devices is limited. PCIE SWITCH chips enable expansion of the PCIe bus to be used more in current server designs.
PCIE SWITCH in the design of the server, one port is generally used as an uplink port to be connected with a CPU PCIe bus, and a plurality of downlink ports are expanded to be connected with PCIe terminal equipment (Endpoint EP) or an uplink port of the next stage PCIE SWITCH to realize expansion of the PCIe bus.
PCIE SWITCH there are multiple downstream ports and one upstream port, and when multiple downstream ports send messages to the upstream port at the same time, PCIE SWITCH needs to solve the arbitration problem, i.e. which downstream port passes preferentially.
Therefore, how to adjust the arbitration priority of each port and improve the PCIe bus utilization is a technical problem that needs to be solved currently.
Disclosure of Invention
The invention provides a dynamic adjustment method, a device, electronic equipment and a storage medium for port arbitration, which are used for solving the defects in the prior art, realizing dynamic adjustment of arbitration priority of each port and improving the utilization rate of a PCIe bus.
The invention provides a dynamic adjustment method for port arbitration, which comprises the following steps:
Acquiring a port arbitration table of a target chip;
initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
Transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained;
And adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
According to the method for dynamically adjusting port arbitration provided by the invention, the initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip comprises the following steps:
detecting whether a downlink port of the target chip is connected with terminal equipment or not to obtain a detection result of the downlink port;
changing the port number in the port arbitration table of the downlink port into a target reserved value under the condition that the detection result is that the terminal equipment is not connected;
during arbitration, the port arbitration table is initialized based on the target reservation value.
According to the method for dynamically adjusting port arbitration provided by the invention, in the arbitration process, the port arbitration table is initialized based on the target reserved value, and the method comprises the following steps:
in the arbitration process, under the condition that an arbitration target is a first time slice written with the target reserved value, skipping the first time slice corresponding to the target reserved value;
transferring the arbitration target to a second time slice until the time slices are traversed to finish the initialization of the port arbitration table;
Wherein the second time slice is the next time slice of the first time slice in the port arbitration table.
According to the method for dynamically adjusting port arbitration provided by the invention, transaction data of each downlink port in the working state of the target chip is obtained in real time, and the method comprises the following steps:
monitoring each terminal device of each downlink port in the working state of the target chip to exchange data;
And obtaining a data exchange result at fixed time intervals to obtain the transaction data of each downlink port.
According to the method for dynamically adjusting port arbitration provided by the invention, the time slice duty ratio of the port arbitration table of the target downlink port is adjusted based on the first target proportion, and the method comprises the following steps:
Confirming the balance proportion of time slices of the port arbitration table of the target downlink port to all time slices of the port arbitration table of the target chip;
and adjusting the balance proportion to the first target proportion so as to adjust the time slice occupation ratio of the port arbitration table of the target downlink port.
According to the method for dynamically adjusting port arbitration provided by the invention, before the port arbitration table of the target chip is obtained, the method further comprises the following steps:
connecting an uplink port of the target chip with a server bus, and connecting a downlink port of the target chip with a plurality of target devices;
The target device comprises the terminal device and/or a target chip of the next stage.
According to the method for dynamically adjusting port arbitration provided by the invention, before the time slices of the port arbitration table of the target downlink port are confirmed to occupy the balanced proportion of all the time slices of the port arbitration table of the target chip, the method further comprises:
Confirming the maximum supported port number of the target chip, and carrying out one-to-one correspondence on each downlink port and the port number;
and acquiring the balance proportion of the time slices of the port numbers, and completing the balance configuration of the port numbers based on the balance proportion.
The invention also provides a dynamic adjusting device for port arbitration, which comprises:
The acquisition module is used for acquiring the port arbitration table of the target chip;
The initialization module is used for initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
The real-time module is used for acquiring transaction data of each downlink port in the working state of the target chip in real time, acquiring transaction total data based on the transaction data of each downlink port, and acquiring a first target proportion of the transaction data in the transaction total data;
And the adjusting module is used for adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for dynamically adjusting port arbitration according to any one of the above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of dynamic adjustment of port arbitration as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a method of dynamically adjusting port arbitration as described in any of the above.
According to the port arbitration dynamic adjustment method, the device, the electronic equipment and the storage medium, the port arbitration table of the target chip is obtained, then the port arbitration table is initialized based on the equipment connection condition of PCIE SWITCH downlink ports, the transaction data of each downlink port in PCIE SWITCH working state is obtained in real time, the transaction total data is obtained based on the transaction data of each downlink port, the first target proportion of the transaction data to the transaction total data is obtained, and the time slice occupation ratio of the port arbitration table of the target downlink port is adjusted based on the first target proportion. The invention can adjust the time slice occupation ratio of the port arbitration table through the first target proportion of the transaction data of the downlink port occupying the transaction total data, thereby dynamically adjusting the arbitration priority of each port and improving the utilization rate of the PCIe bus.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for dynamically adjusting port arbitration according to the present invention;
fig. 2 is a schematic diagram of connection between an uplink port and a downlink port of PCIE SWITCH provided in the present invention;
FIG. 3 is a second flow chart of the method for dynamically adjusting port arbitration according to the present invention;
FIG. 4 is a schematic diagram of a dynamic adjustment device for port arbitration according to the present invention;
Fig. 5 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Firstly, it should be noted that the execution body of the dynamic adjustment method for port arbitration provided by the present invention may be an electronic device, a component in the electronic device, an integrated circuit, or a chip. The electronic device may be a mobile electronic device or a non-mobile electronic device. By way of example, the mobile electronic device may be a cell phone, tablet computer, notebook computer, palm top computer, ultra-mobile personal computer (UMPC), netbook or Personal Digital Assistant (PDA) etc., and the non-mobile electronic device may be a server, network attached storage (Network Attached Storage, NAS) or personal computer (personal computer, PC) etc., the invention is not limited in particular. The following describes each step of the present invention in detail by executing the method for dynamically adjusting port arbitration provided by the present invention with a computer.
Referring to fig. 1, fig. 1 is a flowchart of a method for dynamically adjusting port arbitration according to the present invention, including steps 110, 120, 130, and 140.
Step 110, obtaining a port arbitration table of a target chip;
Step 120, initializing the port arbitration table based on the device connection condition of the downlink port of the target chip;
130, acquiring transaction data of each downlink port in the working state of the target chip in real time, acquiring transaction total data based on the transaction data of each downlink port, and acquiring a first target proportion of the transaction data to the transaction total data;
And 140, adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
Specifically, in the above step 110, the target chip is PCIE SWITCH (PERIPHERAL COMPONENT INTERCONNECT EXPRESS SWITCH, a high-speed serial computer expansion bus standard converter), that is, a chip connecting the upstream CPU PCIe bus and the downstream device. Referring to fig. 2, PCIe switch210 generally uses one port as an upstream port in a server design to connect with CPU PCIe bus 220, and extends a plurality of downstream ports to connect with PCIe terminal devices (Endpoint EP) or upstream ports of a next stage PCIE SWITCH to implement PCIe bus extension. As shown in fig. 2, the PCIE SWITCH extends a PCIe bus to 4 devices, each connected to 4 PCIe devices 230,4, which can communicate with the CPU.
PCIE SWITCH there is a port arbitration table within PCIE SWITCH, which is divided into 128 phases (time slices), each Phase is filled with a port number, and according to the order of Phase0 to Phase127, switch processes a PCIe transaction of the corresponding port at the current Phase, and after a certain time, moves to the next Phase.
For different PCIE SWITCH designs, a designer needs to set a port arbitration table according to the downlink port allocation condition, and specific configuration is carried out on the port arbitration of PCIE SWITCH in a firmware burning mode.
In this embodiment, the arbitration table PCIE SWITCH has an offline default value recorded in the Switch by the accessory burning mode, where the default value is set by a developer, and the number of ports that are maximally supported by PCIE SWITCH in the current design is generally configured in the arbitration table in an equalizing manner.
Next, in step 120, the port arbitration table is initialized according to the device connection condition of the downstream port PCIE SWITCH. The purpose of the initialization is to avoid consuming time for connecting ports of the device.
The initialization process is as follows: first, it is detected whether a downstream port has a PCIe device connected. When one or more downstream ports are not connected with PCIe equipment, the Switch changes the corresponding port number in the port arbitration table into a reserved value (the reserved value does not conflict with the value of any port number, and when Swtich moves to the Phase written with the reserved value in the arbitration process, the Phase is immediately skipped to move to the next Phase), so that the time consumption of the Switch on the port which does not work can be avoided.
In step 130, transaction data of each downlink port in the working state of PCIE SWITCH is obtained in real time, and then transaction total data is obtained based on the transaction data of each downlink port, so as to obtain a first target proportion of the transaction data to the transaction total data.
For example, the total data of all ports is calculated to obtain a value M, and then the total data of each downstream port is obtained, for example, port 1, port 2, port 3 and port 4 are respectively denoted as M 1、m2、m3 and M 4. Where m=m 1+m2+m3+m4. Then, the ratio A 1、A2、A3、A4 of M 1、m2、m3 and M 4 to M was calculated.
Finally, the time slice duty cycle of the port arbitration table of the target downstream port is adjusted by a 1、A2、A3、A4, via step 140.
It should be noted that, the first target ratio a 1、A2、A3、A4 may be the ratio of the time slices Phase of the ports 1, 2, 3 and 4 to the total ports, i.e. the whole port arbitration table.
Note that, in this embodiment, the number of time slices Phase inside PCIE SWITCH is 128, so that the number of time slices in the balanced configuration of the maximum support port a 1、A2、A3、A4 in the operating state is 32.
When the amount of the object data of the downstream port 1 is 50% of the total amount of the object data of the downstream port, that is, the first target proportion is 50%, the Switch will be dynamically adjusted accordingly, the balance proportion of the arbitration table of the port number which is originally set in a balance mode is updated to 25% of the port 1 which is 50% of all phases, that is, 32 time slices of the downstream port 1 are adjusted to 64 time slices, and other ports are updated in the same way.
According to the port arbitration dynamic adjustment method provided by the embodiment of the invention, the port arbitration table of the target chip is obtained, then the port arbitration table is initialized based on the equipment connection condition of PCIE SWITCH downlink ports, the transaction data of each downlink port in the PCIE SWITCH working state is obtained in real time, the transaction total data is obtained based on the transaction data of each downlink port, the first target proportion of the transaction data to the transaction total data is obtained, and the time slice occupation ratio of the port arbitration table of the target downlink port is adjusted based on the first target proportion. The invention can adjust the time slice occupation ratio of the port arbitration table through the first target proportion of the transaction data of the downlink port occupying the transaction total data, thereby dynamically adjusting the arbitration priority of each port and improving the utilization rate of the PCIe bus.
In some embodiments, initializing the port arbitration table based on a device connection condition of a downstream port of the target chip includes:
detecting whether a downlink port of the target chip is connected with terminal equipment or not to obtain a detection result of the downlink port;
changing the port number in the port arbitration table of the downlink port into a target reserved value under the condition that the detection result is that the terminal equipment is not connected;
during arbitration, the port arbitration table is initialized based on the target reservation value.
The present implementation provides an embodiment of port arbitration table initialization.
Firstly, whether a downlink port of PCIE SWITCH is connected with a terminal device needs to be detected, so that a detection result of yes and a detection result of no are obtained.
When the detection result is "no", that is, it is detected that one or more downlink ports of PCIE SWITCH are not connected to the terminal device, PCIE SWITCH changes the corresponding port number in the port arbitration table to a reserved value. For example, when the port 1 is not connected to the terminal device, PCIE SWITCH changes the port 1 to the target reserved value, and the reserved value may be set to a value that does not conflict with any port.
When Swtich moves to the Phase written with the reserved value port in the arbitration process, the Phase is skipped immediately and moved to the next Phase until all phases of the ports are traversed, and the initialization of the port arbitration table is completed.
Optionally, during the arbitration, initializing the port arbitration table based on the target reservation value includes:
in the arbitration process, under the condition that an arbitration target is a first time slice written with the target reserved value, skipping the first time slice corresponding to the target reserved value;
transferring the arbitration target to a second time slice until the time slices are traversed to finish the initialization of the port arbitration table;
Wherein the second time slice is the next time slice of the first time slice in the port arbitration table.
The present embodiment further refines the initialization process of the port arbitration table. In the arbitration process, in the case that the arbitration target is the first time slice of the port written with the target reservation value, the first time slice is skipped, and the arbitration target is transferred to the next time slice, namely, the second time slice. If the second time slice still has the target reserved value written, the second time slice is skipped, the arbitration target is transferred to the next time slice, namely the third time slice, until all time slices are traversed, and the initialization of the port arbitration table is completed.
According to the dynamic adjustment method for port arbitration provided by the embodiment of the invention, whether the downlink port of PCIE SWITCH is connected with the terminal equipment is detected, the target reserved value is set for the downlink port according to the detection result, and the time slice of the port written with the target reserved value is skipped in the arbitration process, so that the time consumption of the port which is not connected with the terminal equipment can be avoided, the port arbitration efficiency is improved, and the server performance is improved.
In some embodiments, the acquiring, in real time, transaction data of each downlink port in the target chip working state includes:
monitoring each terminal device of each downlink port in the working state of the target chip to exchange data;
And obtaining a data exchange result at fixed time intervals to obtain the transaction data of each downlink port.
Specifically, the embodiment provides an implementation process of acquiring PCIE SWITCH port data in real time under the working state.
It can be understood that, in this embodiment, the data exchange process between the terminal devices of each downlink port in the working state PCIE SWITCH may be monitored in real time. The result of the data exchange is obtained every fixed time. The fixed time is selected to be one second, that is, the result of data exchange is acquired every second, and the fixed time can be determined according to practical situations and is not limited in any way. For example, the monitoring of data exchange between the port 1 and the ports 2, 3, etc. includes data transmission, data reception, etc. the monitoring results of the data exchange are summarized to obtain the object data of the port 1 in the working state.
According to the port arbitration dynamic adjustment method provided by the embodiment of the invention, the transaction data of each downlink port is obtained by acquiring the data exchange result of each downlink port at fixed time intervals, so that the time slice of the port is dynamically adjusted according to the proportion of the transaction data of the port to the total transaction data, and the arbitration policy is updated according to the real-time transaction data of each port, and the PCIe bus utilization rate is improved.
In some embodiments, the adjusting the time slice duty cycle of the port arbitration table of the target downstream port based on the first target ratio includes:
Confirming the balance proportion of time slices of the port arbitration table of the target downlink port to all time slices of the port arbitration table of the target chip;
and adjusting the balance proportion to the first target proportion so as to adjust the time slice occupation ratio of the port arbitration table of the target downlink port.
It can be appreciated that this embodiment provides an implementation procedure for dynamically adjusting the downlink port arbitration.
The present embodiment is illustrated with respect to the downstream port 2. First, if the maximum supported number of the downstream ports of PCIE SWITCH is confirmed to be 4, the number of time slices Phase of the equal allocation per port is 32, that is, the proportion of the time slices of the downstream port 2 to the total time slices is 25%.
According to the first target proportion obtained in the above embodiment, the proportion of the object data representing the downstream port 2 to the total of all the downstream port object data is, for example, 50%. The proportion of the time slices of the downlink port 2 which are distributed uniformly to the whole time slices is adjusted from 25 to 50 percent. In popular terms, the time slice duty ratio and the object data duty ratio are unified, so that the time slice duty ratio can be dynamically adjusted according to the object quantity of the target port, the time slice utilization rate is reasonably improved, and the bus utilization rate is further improved.
According to the port arbitration dynamic adjustment method provided by the embodiment of the invention, the port time slice duty ratio and the object data duty ratio which are configured in an equalizing way are unified, and the arbitration priority of the corresponding port is dynamically adjusted according to the real-time traffic of different terminal equipment under the same Switch in the working process of the server, so that the PCIe bus utilization rate can be improved, and the server performance is improved.
In some embodiments, before the obtaining the port arbitration table of the target chip, the method further includes:
connecting an uplink port of the target chip with a server bus, and connecting a downlink port of the target chip with a plurality of target devices;
The target device comprises the terminal device and/or a target chip of the next stage.
In this embodiment, in the connection configuration process of the upstream port and the downstream port of PCIE SWITCH, PCIE SWITCH generally uses one port as an upstream port to connect with a CPU PCIe bus in a server design, and extends a plurality of downstream ports to connect with a PCIe terminal device (Endpoint EP) or an upstream port of a next stage PCIE SWITCH to implement expansion of the PCIe bus. PCIE SWITCH expands a PCIe bus into 4 PCIe devices each connected to 4 PCIe devices, all of which can communicate with the CPU.
In some embodiments, before the confirming that the time slices of the port arbitration table of the target downstream port account for the balanced proportion of all the time slices of the port arbitration table of the target chip, the method further includes:
Confirming the maximum supported port number of the target chip, and carrying out one-to-one correspondence on each downlink port and the port number;
and acquiring the balance proportion of the time slices of the port numbers, and completing the balance configuration of the port numbers based on the balance proportion.
It can be understood that this embodiment is a configuration process of each downlink port. Firstly, the maximum supported port number of PCIE SWITCH needs to be confirmed, the number of the ports which are generally supported is 4, each downlink port is corresponding to the port number, the connection condition of the terminal equipment is convenient to confirm later, the port number is changed into a target reserved value according to the connection condition, and therefore the port arbitration strategy is updated according to different configurations in the arbitration process, and time waste is avoided. After the balanced configuration of each downlink port is completed, the arbitration policy can be updated according to the real-time transaction amount of each downlink port, so that the PCIe bus utilization rate is improved.
Referring to fig. 3, fig. 3 is a flowchart of a method for dynamically adjusting port arbitration according to the present invention, including steps 310, 320, 330, 340 and 350.
Step 310, initializing PCIe after starting or resetting;
step 320, PCLE SWITCH, obtaining the in-place condition of the downlink port equipment;
Step 330, setting an initial value of a port arbitration table according to the in-place condition of the equipment;
step 340, PCLE SWITCH monitors the transaction amount of each downlink port in real time;
and step 350, PCLE SWITCH, correspondingly modifying the proportion of each port occupying Phase in the arbitration table according to the proportion of the transaction amount of each port.
The following describes the port arbitration dynamic adjustment device provided by the present invention, and the port arbitration dynamic adjustment device described below and the port arbitration dynamic adjustment method described above can be referred to correspondingly.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a dynamic adjustment device for port arbitration according to the present invention, including the following modules:
An obtaining module 410, configured to obtain a port arbitration table of the target chip;
An initialization module 420, configured to initialize the port arbitration table based on a device connection condition of a downstream port of the target chip;
The real-time module 430 is configured to obtain, in real time, transaction data of each downlink port in the working state of the target chip, obtain total transaction data based on the transaction data of each downlink port, and obtain a first target proportion of the transaction data in the total transaction data;
And an adjustment module 440, configured to adjust the time slice duty ratio of the port arbitration table of the target downstream port based on the first target proportion.
Specifically, in the above acquisition module 410, the target chip PCIE SWITCH is a chip that connects the upstream CPU PCIe bus and the downstream device. Referring to fig. 2, in the design of a server, PCIe Switch generally uses one port as an uplink port to connect with a CPU PCIe bus, and extends a plurality of downlink ports to connect with PCIe terminal devices (Endpoint EP) or an uplink port of a next stage PCIE SWITCH to implement expansion of the PCIe bus. As shown in fig. 2, the PCIE SWITCH extends a PCIe bus to 4 PCIe devices each connected to 4 devices, each of which may communicate with the CPU.
PCIE SWITCH there is a port arbitration table within PCIE SWITCH, which is divided into 128 phases (time slices), each Phase is filled with a port number, and according to the order of Phase0 to Phase127, switch processes a PCIe transaction of the corresponding port at the current Phase, and after a certain time, moves to the next Phase.
For different PCIE SWITCH designs, a designer needs to set a port arbitration table according to the downlink port allocation condition, and specific configuration is carried out on the port arbitration of PCIE SWITCH in a firmware burning mode.
In this embodiment, the arbitration table PCIE SWITCH has an offline default value recorded in the Switch by the accessory burning mode, where the default value is set by a developer, and the number of ports that are maximally supported by PCIE SWITCH in the current design is generally configured in the arbitration table in an equalizing manner.
Next, in the initialization module 420, the port arbitration table is initialized according to the device connection condition of the downstream port PCIE SWITCH. The purpose of the initialization is to avoid consuming time for connecting ports of the device.
The initialization process is as follows: first, it is detected whether a downstream port has a PCIe device connected. When one or more downstream ports are not connected with PCIe equipment, the Switch changes the corresponding port number in the port arbitration table into a reserved value (the reserved value does not conflict with the value of any port number, and when Swtich moves to the Phase written with the reserved value in the arbitration process, the Phase is immediately skipped to move to the next Phase), so that the time consumption of the Switch on the port which does not work can be avoided.
In the real-time module 430, transaction data of each downlink port in the working state of PCIE SWITCH is obtained in real time, and then transaction total data is obtained based on the transaction data of each downlink port, so as to obtain a first target proportion of the transaction data to the transaction total data.
For example, the total data of all ports is calculated to obtain a value M, and then the total data of each downstream port is obtained, for example, port 1, port 2, port 3 and port 4 are respectively denoted as M 1、m2、m3 and M 4. Where m=m 1+m2+m3+m4. Then, the ratio A 1、A2、A3、A4 of M 1、m2、m3 and M 4 to M was calculated.
Finally, the time slice duty cycle of the port arbitration table of the target downstream port is adjusted by the adjustment module 440 using a 1、A2、A3、A4.
It should be noted that, the first target ratio a 1、A2、A3、A4 may be the ratio of the time slices Phase of the ports 1, 2, 3 and 4 to the total ports, i.e. the whole port arbitration table.
Note that, in this embodiment, the number of time slices Phase inside PCIE SWITCH is 128, so that the number of time slices in the balanced configuration of the maximum support port a 1、A2、A3、A4 in the operating state is 32.
When the amount of the object data of the downstream port 1 is 50% of the total amount of the object data of the downstream port, that is, the first target proportion is 50%, the Switch will be dynamically adjusted accordingly, the balance proportion of the arbitration table of the port number which is originally set in a balance mode is updated to 25% of the port 1 which is 50% of all phases, that is, 32 time slices of the downstream port 1 are adjusted to 64 time slices, and other ports are updated in the same way.
According to the port arbitration dynamic adjustment device provided by the embodiment of the invention, the port arbitration table of the target chip is obtained, then the port arbitration table is initialized based on the equipment connection condition of PCIE SWITCH downlink ports, the transaction data of each downlink port in the PCIE SWITCH working state is obtained in real time, the transaction total data is obtained based on the transaction data of each downlink port, the first target proportion of the transaction data to the transaction total data is obtained, and the time slice occupation ratio of the port arbitration table of the target downlink port is adjusted based on the first target proportion. The invention can adjust the time slice occupation ratio of the port arbitration table through the first target proportion of the transaction data of the downlink port occupying the transaction total data, thereby dynamically adjusting the arbitration priority of each port and improving the utilization rate of the PCIe bus.
In some embodiments, the initialization module is specifically configured to:
detecting whether a downlink port of the target chip is connected with terminal equipment or not to obtain a detection result of the downlink port;
changing the port number in the port arbitration table of the downlink port into a target reserved value under the condition that the detection result is that the terminal equipment is not connected;
during arbitration, the port arbitration table is initialized based on the target reservation value.
In some embodiments, the initialization module is further to:
in the arbitration process, under the condition that an arbitration target is a first time slice written with the target reserved value, skipping the first time slice corresponding to the target reserved value;
transferring the arbitration target to a second time slice until the time slices are traversed to finish the initialization of the port arbitration table;
Wherein the second time slice is the next time slice of the first time slice in the port arbitration table.
Specifically, the function of the initialization module is: firstly, whether a downlink port of PCIE SWITCH is connected with a terminal device needs to be detected, so that a detection result of yes and a detection result of no are obtained.
When the detection result is "no", that is, it is detected that one or more downlink ports of PCIE SWITCH are not connected to the terminal device, PCIE SWITCH changes the corresponding port number in the port arbitration table to a reserved value. For example, when the port 1 is not connected to the terminal device, PCIE SWITCH changes the port 1 to the target reserved value, and the reserved value may be set to a value that does not conflict with any port.
When Swtich moves to the Phase written with the reserved value port in the arbitration process, the Phase is skipped immediately and moved to the next Phase until all phases of the ports are traversed, and the initialization of the port arbitration table is completed.
Further, in the arbitration process, in the case that the arbitration target is the first time slice of the port written with the target reservation value, the first time slice is skipped, and the arbitration target is transferred to the next time slice, namely, the second time slice. If the second time slice still has the target reserved value written, the second time slice is skipped, the arbitration target is transferred to the next time slice, namely the third time slice, until all time slices are traversed, and the initialization of the port arbitration table is completed.
According to the dynamic port arbitration adjusting device provided by the embodiment of the invention, whether the downlink port of PCIE SWITCH is connected with the terminal equipment is detected, the target reserved value is set for the downlink port according to the detection result, and the time slice of the port written with the target reserved value is skipped in the arbitration process, so that the time consumption of the port which is not connected with the terminal equipment can be avoided, the port arbitration efficiency is improved, and the server performance is improved.
In some embodiments, the real-time module is specifically configured to:
monitoring each terminal device of each downlink port in the working state of the target chip to exchange data;
And obtaining a data exchange result at fixed time intervals to obtain the transaction data of each downlink port.
It can be understood that, in this embodiment, the data exchange process between the terminal devices of each downlink port in the working state PCIE SWITCH may be monitored in real time. The result of the data exchange is obtained every fixed time. For example, the monitoring of data exchange between the port 1 and the ports 2, 3, etc. includes data transmission, data reception, etc. the monitoring results of the data exchange are summarized to obtain the object data of the port 1 in the working state.
According to the port arbitration dynamic adjustment device provided by the embodiment of the invention, the transaction data of each downlink port is obtained by acquiring the data exchange result of each downlink port at fixed time intervals, so that the time slice of the port is dynamically adjusted according to the proportion of the transaction data of the port to the total transaction data, and the arbitration policy is updated according to the real-time transaction data of each port, and the PCIe bus utilization rate is improved.
In some embodiments, the adjustment module is specifically configured to:
Confirming the balance proportion of time slices of the port arbitration table of the target downlink port to all time slices of the port arbitration table of the target chip;
and adjusting the balance proportion to the first target proportion so as to adjust the time slice occupation ratio of the port arbitration table of the target downlink port.
It can be appreciated that this embodiment provides an implementation procedure for dynamically adjusting the downlink port arbitration.
The present embodiment is illustrated with respect to the downstream port 2. First, if the maximum supported number of the downstream ports of PCIE SWITCH is confirmed to be 4, the number of time slices Phase of the equal allocation per port is 32, that is, the proportion of the time slices of the downstream port 2 to the total time slices is 25%.
According to the first target proportion obtained in the above embodiment, the proportion of the object data representing the downstream port 2 to the total of all the downstream port object data is, for example, 50%. The proportion of the time slices of the downlink port 2 which are distributed uniformly to the whole time slices is adjusted from 25 to 50 percent. In popular terms, the time slice duty ratio and the object data duty ratio are unified, so that the time slice duty ratio can be dynamically adjusted according to the object quantity of the target port, the time slice utilization rate is reasonably improved, and the bus utilization rate is further improved.
According to the port arbitration dynamic adjustment device provided by the embodiment of the invention, the port time slice duty ratio and the object data duty ratio which are configured in an equalizing way are unified, and the arbitration priority of the corresponding port is dynamically adjusted according to the real-time traffic of different terminal equipment under the same Switch in the working process of the server, so that the PCIe bus utilization rate can be improved, and the server performance is improved.
In some embodiments, the apparatus further comprises a connection module, specifically for:
connecting an uplink port of the target chip with a server bus, and connecting a downlink port of the target chip with a plurality of target devices;
The target device comprises the terminal device and/or a target chip of the next stage.
In this embodiment, in the connection configuration process of the upstream port and the downstream port of PCIE SWITCH, PCIE SWITCH generally uses one port as an upstream port to connect with a CPU PCIe bus in a server design, and extends a plurality of downstream ports to connect with a PCIe terminal device (Endpoint EP) or an upstream port of a next stage PCIE SWITCH to implement expansion of the PCIe bus. PCIE SWITCH expands a PCIe bus into 4 PCIe devices each connected to 4 PCIe devices, all of which can communicate with the CPU.
In some embodiments, the apparatus further comprises a configuration module, specifically configured to:
Confirming the maximum supported port number of the target chip, and carrying out one-to-one correspondence on each downlink port and the port number;
and acquiring the balance proportion of the time slices of the port numbers, and completing the balance configuration of the port numbers based on the balance proportion.
It can be understood that this embodiment is a configuration process of each downlink port. Firstly, the maximum supported port number of PCIE SWITCH needs to be confirmed, the number of the ports which are generally supported is 4, each downlink port is corresponding to the port number, the connection condition of the terminal equipment is convenient to confirm later, the port number is changed into a target reserved value according to the connection condition, and therefore the port arbitration strategy is updated according to different configurations in the arbitration process, and time waste is avoided. After the balanced configuration of each downlink port is completed, the arbitration policy can be updated according to the real-time transaction amount of each downlink port, so that the PCIe bus utilization rate is improved.
Fig. 5 illustrates a physical schematic diagram of an electronic device, as shown in fig. 5, which may include: processor 510, communication interface (Communications Interface) 520, memory 530, and communication bus 540, wherein processor 510, communication interface 520, memory 530 complete communication with each other through communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a method of dynamic adjustment of port arbitration, the method comprising:
Acquiring a port arbitration table of a target chip;
initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
Transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained;
And adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
Further, the logic instructions in the memory 530 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing a method for dynamically adjusting port arbitration provided by the above methods, the method comprising:
Acquiring a port arbitration table of a target chip;
initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
Transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained;
And adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method for dynamically adjusting port arbitration provided by the above methods, the method comprising:
Acquiring a port arbitration table of a target chip;
initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
Transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained;
And adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for dynamically adjusting port arbitration, comprising:
Acquiring a port arbitration table of a target chip;
initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
Transaction data of all downlink ports in the working state of the target chip are obtained in real time, transaction total data is obtained based on the transaction data of all downlink ports, and a first target proportion of the transaction data in the transaction total data is obtained;
adjusting the time slice duty ratio of a port arbitration table of the target downlink port based on the first target proportion;
The initializing the port arbitration table based on the device connection condition of the downlink port of the target chip includes:
detecting whether a downlink port of the target chip is connected with terminal equipment or not to obtain a detection result of the downlink port;
changing the port number in the port arbitration table of the downlink port into a target reserved value under the condition that the detection result is that the terminal equipment is not connected;
initializing the port arbitration table based on the target reservation value during arbitration;
wherein initializing the port arbitration table based on the target reservation value during arbitration comprises:
in the arbitration process, under the condition that an arbitration target is a first time slice written with the target reserved value, skipping the first time slice corresponding to the target reserved value;
transferring the arbitration target to a second time slice until the time slices are traversed to finish the initialization of the port arbitration table;
Wherein the second time slice is the next time slice of the first time slice in the port arbitration table;
The adjusting the time slice duty ratio of the port arbitration table of the target downlink port based on the first target proportion includes:
Confirming the balance proportion of time slices of the port arbitration table of the target downlink port to all time slices of the port arbitration table of the target chip;
and adjusting the balance proportion to the first target proportion so as to adjust the time slice occupation ratio of the port arbitration table of the target downlink port.
2. The method for dynamically adjusting port arbitration according to claim 1, wherein the acquiring transaction data of each downlink port in the working state of the target chip in real time includes:
monitoring each terminal device of each downlink port in the working state of the target chip to exchange data;
And obtaining a data exchange result at fixed time intervals to obtain the transaction data of each downlink port.
3. The method for dynamically adjusting port arbitration according to claim 1, wherein before the obtaining the port arbitration table of the target chip, the method further comprises:
connecting an uplink port of the target chip with a server bus, and connecting a downlink port of the target chip with a plurality of target devices;
The target device comprises the terminal device and/or a target chip of the next stage.
4. The method for dynamically adjusting port arbitration according to claim 1, wherein before the time slices of the port arbitration table of the target downstream port are confirmed to occupy the balanced proportion of all the time slices of the port arbitration table of the target chip, the method further comprises:
Confirming the maximum supported port number of the target chip, and carrying out one-to-one correspondence on each downlink port and the port number;
and acquiring the balance proportion of the time slices of the port numbers, and completing the balance configuration of the port numbers based on the balance proportion.
5. A dynamic adjustment device for port arbitration, comprising:
The acquisition module is used for acquiring the port arbitration table of the target chip;
The initialization module is used for initializing the port arbitration table based on the equipment connection condition of the downlink port of the target chip;
The real-time module is used for acquiring transaction data of each downlink port in the working state of the target chip in real time, acquiring transaction total data based on the transaction data of each downlink port, and acquiring a first target proportion of the transaction data in the transaction total data;
The adjusting module is used for adjusting the time slice occupation ratio of the port arbitration table of the target downlink port based on the first target proportion;
wherein the device is further for:
detecting whether a downlink port of the target chip is connected with terminal equipment or not to obtain a detection result of the downlink port;
changing the port number in the port arbitration table of the downlink port into a target reserved value under the condition that the detection result is that the terminal equipment is not connected;
initializing the port arbitration table based on the target reservation value during arbitration;
The device is also for:
in the arbitration process, under the condition that an arbitration target is a first time slice written with the target reserved value, skipping the first time slice corresponding to the target reserved value;
transferring the arbitration target to a second time slice until the time slices are traversed to finish the initialization of the port arbitration table;
Wherein the second time slice is the next time slice of the first time slice in the port arbitration table;
The device is also for:
Confirming the balance proportion of time slices of the port arbitration table of the target downlink port to all time slices of the port arbitration table of the target chip;
and adjusting the balance proportion to the first target proportion so as to adjust the time slice occupation ratio of the port arbitration table of the target downlink port.
6. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method for dynamically adjusting port arbitration according to any one of claims 1 to 4 when the program is executed by the processor.
7. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements a method of dynamic adjustment of port arbitration according to any of claims 1 to 4.
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| US7020146B2 (en) * | 2001-08-30 | 2006-03-28 | Sun Microsystems, Inc. | Broadcast arbitration in a multi-domain device |
| CN105867835A (en) * | 2015-01-23 | 2016-08-17 | 深圳市硅格半导体有限公司 | Storage apparatus data service quality management method and storage apparatus |
| CN111950879A (en) * | 2020-07-31 | 2020-11-17 | 奥星制药设备（石家庄）有限公司 | Queuing arbitration method and device for processes and terminal equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101520714A (en) * | 2009-04-17 | 2009-09-02 | 福建星网锐捷网络有限公司 | Method and system for multi-channel data transmission |
| CN102033832A (en) * | 2010-12-02 | 2011-04-27 | 杭州国芯科技股份有限公司 | Access control method of synchronous dynamic memory |
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