CN118899334A - An enhancement-mode gallium nitride high electron mobility transistor with JFET structure - Google Patents
An enhancement-mode gallium nitride high electron mobility transistor with JFET structure Download PDFInfo
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Abstract
The invention belongs to the field of microelectronics, and particularly relates to an enhanced gallium nitride high electron mobility transistor with a JFET structure. According to the enhancement type GaN HEMT, the JFET structure connected with the grid electrode and the source electrode is introduced, when bias is applied to the grid electrode, the JFET clamps the barrier layer under the grid electrode, grid voltage is completely applied to the JFET, when the JFET reaches the turn-off voltage, the grid bias is applied to the barrier layer and enables the two-dimensional electron gas channel to be conducted, the threshold voltage is controlled by the turn-off voltage of the JFET structure, decoupling of the threshold voltage and reverse conducting voltage is achieved, and the threshold voltage is greatly improved. The structure of the invention can obviously improve the threshold voltage and simultaneously reduce the reverse conduction voltage of the device and the reverse conduction loss; when the fast switching operation is carried out, charges induced by the p-type doped gallium nitride layer can be rapidly released through the JFET connected between the grid sources, so that the stability of the threshold voltage of the device is improved; and the adopted process is compatible with the traditional process.
Description
Technical Field
The invention belongs to the field of microelectronics, in particular to an enhancement type gallium nitride high electron mobility transistor with a JFET structure, which is a semiconductor transistor capable of effectively improving the threshold voltage and the threshold voltage stability of a device.
Background
The gallium nitride-based high electron mobility transistor (High Electron Mobility Transistor, HEMT) has the excellent characteristics of high critical breakdown electric field, high electron saturation velocity, good heat conduction performance, radiation resistance, good chemical stability and the like, is particularly suitable for the fields of high current, low power consumption and high frequency and high voltage, and is becoming the primary choice of a high-voltage power switch module. To ensure safe operation of the power electronics system, a normally-off feature is very necessary, namely the implementation of an enhanced (E-mode) GaN HEMT.
In recent years, several methods of implementing enhancement-mode gallium nitride field effect transistors have been proposed, such as using a Cascode structure, a recessed gate structure, fluoride ion implantation, and a p-doped gallium nitride layer. Among them, gallium nitride field effect transistors having a p-type doped gallium nitride layer (p-GaN) have been widely commercialized thanks to simple process implementation, good reliability, and excellent performance.
The structure of a conventional enhanced p-GaN HEMT is shown in fig. 1, and mainly comprises a substrate, a gallium nitride buffer layer, a gallium nitride channel layer, an aluminum gallium nitride barrier layer, a p-type doped gallium nitride layer, and a source electrode, a drain electrode and a gate electrode formed on the aluminum gallium nitride barrier layer; the source electrode and the drain electrode form ohmic contact with the AlGaN barrier layer, and the grid electrode forms ohmic contact with the p-type doped gallium nitride layer.
In 2013 HaoWang et al used high work function tungsten instead of nickel as the gate metal, tungsten forming a higher schottky barrier with p-GaN. The gate bias of this structure drops more in p-GaN, increasing the threshold voltage from 1.23V to 3.03V. In the same year, the team proposed a source-connected p-GaN HEMT structure that increased the width of the schottky barrier depletion region, increasing the threshold voltage from 0.93V to 2.44V. In 2022, shun-Wei Tang et al proposed a method of regrowing a p-GaN layer after recessing the AlGaN barrier in the gate region; the threshold voltage of the p-GaN HEMT fabricated using this method increases from 1.5V to 2.7V. In 2023, yue Hao groups formed a thin oxide interlayer on top of the p-GaN layer by using oxygen plasma treatment in combination with oxygen atmosphere annealing to raise the threshold voltage from 1.8V to 3.9V; however, these methods still have two problems.
In one aspect, in power conversion with an inductive load, the power switch needs to provide a freewheeling path so that current in the inductive load can pass energy from source to drain without interruption; the reverse turn-on capability of the GaN HEMT is controlled by the gate due to the lack of the body diode; thus, the reverse turn-on voltage V RT of the GaN HEMT is essentially related to the threshold voltage V th and the gate voltage V GS. The method inevitably increases the reverse conduction voltage while increasing the threshold voltage, thereby introducing serious reverse conduction loss.
On the other hand, for a schottky-contact p-GaN HEMT, the p-GaN region below the schottky barrier is not electrically connected to any electrode. This results in the p-GaN region being floating and free carrier exchange with the outside is impossible. Therefore, when a fast switching operation is performed, since charges induced by floating the p-GaN region cannot be rapidly removed, a threshold voltage of the p-GaN gate GaN HEMT may drift, resulting in deterioration of the threshold voltage stability of the device.
Disclosure of Invention
In order to solve the problems or the shortcomings, the invention provides an enhancement type gallium nitride high electron mobility transistor with a JFET structure, which is characterized in that a JFET structure for connecting a grid electrode and a source electrode is introduced into an enhancement type GaN HEMT, when bias is applied to the grid electrode, the JFET clamps a barrier layer under the grid electrode, grid voltage is completely applied to the JFET, and when the JFET reaches an off voltage, the grid bias is applied to the barrier layer and enables a two-dimensional electron gas channel to be conducted. The structure of the invention can obviously improve the threshold voltage and simultaneously reduce the reverse conduction voltage of the device and the reverse conduction loss; when the fast switching operation is carried out, charges induced by the p-type doped gallium nitride layer can be rapidly released through the JFET connected between the grid sources, and the stability of the threshold voltage of the device is improved.
An enhancement type gallium nitride high electron mobility transistor containing a JFET structure sequentially comprises a substrate 101, a buffer layer 102, a channel layer 103 and a barrier layer 104 from bottom to top.
A source electrode 108, an insulating medium layer 105, a p-type doped gallium nitride layer 106 and a drain electrode 111 are arranged above the barrier layer 104; wherein the source 108 forms an ohmic contact with the barrier layer 104 and the p-doped gallium nitride layer 106 and the drain 111 forms an ohmic contact with the barrier layer 104.
The p-type doped gallium nitride layer 106 is divided into two parts, one part is positioned above the insulating dielectric layer 105, and the other part is positioned on the right side of the insulating dielectric layer 105 and above the barrier layer 104; in the p-type doped gallium nitride layer 106 located at the upper portion of the insulating dielectric layer 105, an n-type doped gallium nitride region 107 is also provided.
A second gate 110 is disposed above the n-type doped gallium nitride region 107, and the second gate 110 forms an ohmic contact with the n-type doped gallium nitride region 107.
The distance d between the right side of the insulating dielectric layer 105 and the p-type doped gallium nitride layer 106 is provided with a first grid 109 and d >0 above, and the first grid 109 and the p-type doped gallium nitride layer 106 form schottky contact; and the first gate 109 and the second gate 110 are metal-interconnected to form a gate G.
The n-doped gallium nitride region 107 and the p-doped gallium nitride layer 106 and the second gate 110 form a junction field effect transistor JFET structure that communicates the source 108 and the first gate 109.
A passivation layer 112 is covered between the source 108 and the second gate 110, between the second gate 110 and the first gate 109, and between the first gate 109 and the drain 111 of the entire device surface.
Further, the n-doped gan region 107, the p-doped gan layer 106 and the second gate 110 form a JFET structure of the junction field effect transistor connecting the source 108 and the first gate 109, as shown in fig. 3, which clamps the voltage of the p-doped gan layer 106 below the first gate 109 and provides a path for discharging the induced charges in the p-doped gan region 106.
Further, the n-type doped gallium nitride region 107 is doped by ion implantation to form a multi-n-well region or uniformly doped.
Further, the substrate 101 is made of one or a combination of sapphire, si, siC, alN, gaN and diamond.
Further, the buffer layer 102 and the channel layer 103 are made of one or a combination of a plurality of GaN, alN, alGaN, inGaN, inAlN materials.
Further, the material adopted by the barrier layer 104 is Al xGa1-x N, wherein x is more than or equal to 0 and less than or equal to 1.
Further, the insulating dielectric layer 105 is made of one or a combination of several of Al 2O3、HfO2, znO and SiO 2.
Further, the passivation layer 112 is made of one of SiO 2、Si3N4.
The beneficial effects of the invention are as follows: 1) The invention introduces a JFET structure connecting a grid electrode and a source electrode on the basis of the traditional p-GaN HEMT, when the grid electrode is biased, the JFET clamps the voltage of a part of p-type gallium nitride doped layer 106 below a first grid electrode 109, the grid voltage is completely applied to the JFET, and when the JFET reaches an off voltage, the grid bias is applied to a barrier layer and enables a two-dimensional electron gas channel to be conducted. The threshold voltage is controlled by the turn-off voltage of the JFET structure, so that decoupling of the threshold voltage and reverse turn-on voltage is realized, and the threshold voltage is greatly improved. 2) The introduction of the JFET structure provides a path for discharging induced charges of the p-GaN region, and improves the stability of the threshold voltage of the device. 3) The preparation process is simple and feasible, is compatible with the traditional process, and can be used for industrial production.
Drawings
Fig. 1 is a schematic diagram of a conventional p-GaN HEMT structure.
Fig. 2 is a schematic diagram of a GaN HEMT structure including a JFET structure according to example 1.
Fig. 3 is a schematic diagram of the JFET structure of the present invention.
Fig. 4 is a schematic diagram of a GaN HEMT structure including a JFET structure according to example 2.
Fig. 5 is a graph comparing the transfer characteristic curves of example 1 and a conventional p-GaN HEMT.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
Example 1
An enhancement mode gallium nitride high electron mobility transistor with JFET structure, the device structure is shown in figure 2, comprising from bottom to top: a substrate (101), a buffer layer (102), a channel layer (103), and a barrier layer (104); a source electrode (108), an insulating medium layer (105), a p-type doped gallium nitride layer (106) and a drain electrode (111) are arranged above the barrier layer (104); wherein the source (108) forms an ohmic contact with the barrier layer (104) and the p-doped gallium nitride layer (106), and the drain (111) forms an ohmic contact with the barrier layer (104).
The p-type doped gallium nitride layer (106) is divided into two parts, one part is positioned above the insulating medium layer (105), and the other part is positioned on the right side of the insulating medium layer (105) and above the barrier layer (104); an n-type doped gallium nitride region (107) is further arranged in the p-type doped gallium nitride layer (106) positioned on the upper portion of the insulating medium layer (105). A second grid electrode (110) is arranged above the n-type doped gallium nitride region (107), and the second grid electrode (110) and the n-type doped gallium nitride region (107) form ohmic contact. The right side of the insulating medium layer (105) is provided with a d position, a first grid electrode (109) is arranged above the p-type doped gallium nitride layer (106), d is more than 0, and the first grid electrode (109) and the p-type doped gallium nitride layer (106) form Schottky contact; and the first gate (109) and the second gate (110) are metal-interconnected to form a gate G. The n-doped gallium nitride region (107) and the p-doped gallium nitride layer (106) and the second gate (110) form a Junction Field Effect Transistor (JFET) structure that communicates the source (108) and the first gate (109).
A passivation layer (112) is covered between the source electrode (108) and the second gate electrode (110), between the second gate electrode (110) and the first gate electrode (109) and between the first gate electrode (109) and the drain electrode (111) on the whole device surface.
In the embodiment, the substrate (101) is a silicon substrate, and the crystal orientation is 111; the buffer layer (102) is made of gallium nitride; the channel layer (103) is made of gallium nitride; the barrier layer (104) is made of aluminum gallium nitride; the insulating medium layer (105) is made of silicon dioxide; the passivation layer (112) is made of silicon nitride.
Table 1: example 1 device parameters with conventional p-GaN HEMT
As can be seen from table 1, the threshold voltage of the conventional p-GaN HEMT device is 0.94V, and the threshold voltage of embodiment 1 of the present invention is raised to 4.20V, which is about 4 times higher than that of the conventional p-GaN HEMT device. Fig. 5 is a graph comparing transfer characteristic curves of a JFET GaN HEMT device and a conventional enhancement p-GaN HEMT device structure according to an embodiment of the present invention, and the result fully shows the advantage of increasing the threshold voltage according to the present invention. The JFET between the grid sources provides a path for discharging induced charges of the p-GaN region, and the stability of the threshold voltage of the device is improved.
Example 2
Compared with embodiment 1, the device of this embodiment adopts ion implantation to form multiple n-well under the second gate (110) to form n-type doped gallium nitride region, and the other structures are the same as embodiment 1, as shown in fig. 4.
According to the embodiment, the novel GaN HEMT device structure is formed by introducing the JFET structure for connecting the grid electrode and the source electrode into the enhanced GaN HEMT, when the grid electrode is biased, the JFET clamps the barrier layer under the grid electrode, the grid voltage is completely applied to the JFET, when the JFET reaches the turn-off voltage, the grid bias is applied to the barrier layer and enables the two-dimensional electron gas channel to be conducted, the threshold voltage is controlled by the turn-off voltage of the JFET structure, decoupling of the threshold voltage and reverse conducting voltage is achieved, and the threshold voltage is greatly improved. The structure of the invention can obviously improve the threshold voltage and simultaneously reduce the reverse conduction voltage of the device and the reverse conduction loss; when the fast switching operation is carried out, charges induced by the p-type doped gallium nitride layer can be rapidly released through the JFET connected between the grid sources, so that the stability of the threshold voltage of the device is improved; the process is simple and feasible, is compatible with the traditional process, and can be used for industrial production.
Claims (8)
1. An enhanced gallium nitride high electron mobility transistor comprising a JFET structure, characterized by:
The semiconductor device comprises a substrate (101), a buffer layer (102), a channel layer (103) and a barrier layer (104) from bottom to top in sequence;
A source electrode (108), an insulating medium layer (105), a p-type doped gallium nitride layer (106) and a drain electrode (111) are arranged above the barrier layer (104); wherein the source electrode (108) forms ohmic contact with the barrier layer (104) and the p-type doped gallium nitride layer (106), and the drain electrode (111) forms ohmic contact with the barrier layer (104);
The p-type doped gallium nitride layer (106) is divided into two parts, one part is positioned above the insulating medium layer (105), and the other part is positioned on the right side of the insulating medium layer (105) and above the barrier layer (104); an n-type doped gallium nitride region (107) is further arranged in the p-type doped gallium nitride layer (106) positioned at the upper part of the insulating medium layer (105);
A second grid electrode (110) is arranged above the n-type doped gallium nitride region (107), and the second grid electrode (110) and the n-type doped gallium nitride region (107) form ohmic contact;
The right side distance of the insulating medium layer (105) is d, a first grid (109) is arranged above the p-type doped gallium nitride layer (106), d is more than 0, and the first grid (109) and the p-type doped gallium nitride layer (106) form Schottky contact; and the first grid electrode (109) and the second grid electrode (110) are subjected to metal interconnection to form a grid electrode G;
The n-type doped gallium nitride region (107), the p-type doped gallium nitride layer (106) and the second grid electrode (110) form a Junction Field Effect Transistor (JFET) structure communicated with the source electrode (108) and the first grid electrode (109);
A passivation layer (112) is covered between the source electrode (108) and the second gate electrode (110), between the second gate electrode (110) and the first gate electrode (109) and between the first gate electrode (109) and the drain electrode (111) on the whole device surface.
2. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein:
The Junction Field Effect Transistor (JFET) structure realizes clamping of the voltage of the p-type gallium nitride doped layer 106 below the first grid 109 and provides a path for discharging induced charges in the p-type doped gallium nitride region (106).
3. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the doping mode of the n-type doped gallium nitride region (107) is ion implantation to form a multi-n-well region or uniform doping.
4. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the substrate (101) is made of one or a combination of more of sapphire, si, siC, alN, gaN and diamond;
5. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the buffer layer (102) and the channel layer (103) are made of one or a combination of more than one of GaN, alN, alGaN, inGaN, inAlN.
6. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the barrier layer (104) is made of Al xGa1-x N, wherein x is more than or equal to 0 and less than or equal to 1.
7. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the insulating medium layer (105) is made of one or a combination of more of Al 2O3、HfO2, znO and SiO 2.
8. The enhancement mode gallium nitride high electron mobility transistor comprising a JFET structure of claim 1, wherein: the passivation layer (112) is made of SiO 2 or Si 3N4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119730341A (en) * | 2024-12-19 | 2025-03-28 | 深圳平湖实验室 | Transistor structure and electronic equipment |
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| CN115315814A (en) * | 2020-04-09 | 2022-11-08 | 高通股份有限公司 | Multi-gate High Electron Mobility Transistor (HEMT) with tuned recess depth gate for improved device linearity |
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| CN119730341A (en) * | 2024-12-19 | 2025-03-28 | 深圳平湖实验室 | Transistor structure and electronic equipment |
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