CN121690184A

CN121690184A - A GPIO level conversion circuit

Info

Publication number: CN121690184A
Application number: CN202511659657.3A
Authority: CN
Inventors: 许道海; 赵乐; 曾世杰; 孟杰
Original assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Current assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Priority date: 2025-11-13
Filing date: 2025-11-13
Publication date: 2026-03-17

Abstract

This application provides a GPIO level conversion circuit, belonging to the field of level conversion technology. The input signal VI is processed by an inverter in the first delay branch to obtain a signal in phase with the input signal, which is then output to the first level conversion branch. The first level conversion branch processes the in-phase input signal VI and outputs a signal with a stable duty cycle to the output terminal VO. The input signal VI is then processed by an inverter in the second delay branch to obtain a signal out of phase with the input signal, which is then output to the second level conversion branch. The second level conversion branch processes the out-of-phase input signal VI and outputs a signal with a stable duty cycle to the output terminal VO. Therefore, the rising and falling edges of the output signal in the level conversion circuit maintain a consistent delay, thereby compensating for the duty cycle of the output pulse and ensuring the stability of the output signal's duty cycle.

Description

GPIO level conversion circuit

Technical Field

The application belongs to the technical field of level conversion, and particularly relates to a GPIO level conversion circuit.

Background

The GPIO is a programmable pin in an integrated circuit, the core function of the GPIO is to realize the input or output of digital signals through software control, a user can dynamically switch pin modes according to requirements, adjust control logic, adapt to different peripheral equipment and realize level conversion between the inside of the integrated circuit and the peripheral equipment. The circuit that realizes the level shift function is called a level shift circuit.

The existing level conversion circuit has the basic working principle of level conversion, when a low level is input, namely the input voltage of the input end of the level conversion circuit is zero, a control signal with a high level is output through an inverter, the high level control signal controls the conduction output voltage of an NMOS tube to be zero, and when a high level is input, namely the input voltage of the input end of the level conversion circuit is a power supply voltage, the NMOS tube is conducted so as to pull the grid voltage of a PMOS tube low and output the high level, so that the level conversion function from VDD1 to VDD2 is realized.

The control signal output by the existing level conversion circuit has delay relative to the input signal, so that the output falling edge has falling delay time, but the rising edge does not have rising delay time, so that the duty ratio of the output signal of the output end is reduced, and the stability of the output duty ratio of the GPIO is affected.

Disclosure of Invention

In view of the above, the present application proposes a GPIO level conversion circuit. The rising edge and the falling edge of the output signal in the level conversion circuit can be enabled to keep consistent delay, so that the duty ratio of the output pulse is compensated, and the stability of the duty ratio of the output signal is ensured.

An embodiment of the present application provides a level shift circuit, including:

The level conversion module and the signal delay module;

the level conversion module comprises a first level conversion branch and a second level conversion branch which are formed by at least two P-type MOS tubes and N-type MOS tubes;

the leading-out output ends of the first level conversion branch and the second level conversion branch are the output ends of the level conversion circuit;

the signal delay module comprises a first delay branch and a second delay branch, wherein the first delay branch comprises at least two inverters, and the second delay branch comprises at least three inverters;

The output end of the first delay branch is connected with the input end of the first level conversion branch, the output end of the second delay branch is connected with the output end of the second level conversion branch, and the input ends of the first delay branch and the second delay branch are connected with input signals.

Preferably, the first level shifting branch includes:

the first P-type MOS tube M1 and the third N-type MOS tube M3;

the drain electrode of the first P-type MOS tube M1 is connected with a second power supply VDD2, and the source electrode of the first P-type MOS tube M1 is connected with the drain electrode of the third N-type MOS tube M3 in series;

The source electrode of the first P-type MOS tube M1 is connected with the grid electrode of the third P-type MOS tube M2 in the second level conversion branch, and the grid electrode leading-out terminal of the first P-type MOS tube M1 is the output end of the level conversion circuit;

The drain electrode of the third N-type MOS tube M3 is connected with the source electrode of the first P-type MOS tube M1, the grid electrode of the third N-type MOS tube M3 is connected with the output end of the first delay branch, and the source electrode of the third N-type MOS tube M3 is grounded.

Preferably, the second level shifting branch includes:

the second P type MOS tube M2 and the fourth N type MOS tube M4;

The drain electrode of the second P-type MOS tube M2 is connected with a second power supply VDD2, the source electrode of the second P-type MOS tube M2 is connected with the drain electrode of the fourth N-type MOS tube M4 in series, and a lead-out terminal between the source electrode of the second P-type MOS tube M2 and the drain electrode of the fourth N-type MOS tube M4 is used as the output end of a second level conversion branch circuit to be connected with the output end of a level conversion circuit;

the drain electrode of the fourth N-type MOS tube M4 is connected with the source electrode of the second P-type MOS tube M2, the grid electrode of the fourth N-type MOS tube M4 is connected with the output end of the second delay branch, and the source electrode of the fourth N-type MOS tube M4 is grounded.

Preferably, the first delay branch includes:

the fourth inverter INV4, the fifth inverter INV5, the fifth P-type MOS transistor M5 and the sixth N-type MOS transistor M6;

the input end of the fourth inverter INV4 is connected with the input signal VI of the power supply, the output end of the fourth inverter INV4 is connected with the gates of the fifth P-type MOS transistor M5 and the sixth N-type MOS transistor M6, and is connected with the input end of the fifth inverter INV 5.

Preferably, the first delay branch further includes:

The output end of the fifth inverter INV5 is used as the output end of the first delay branch and is connected with the grid electrode of the third N-type MOS tube M3 in the first level conversion branch;

the grid electrodes of the fifth P-type MOS tube M5 and the sixth N-type MOS tube M6 are connected, the drain electrode of the fifth P-type MOS tube M5 is connected with a power supply, and the source electrode of the sixth N-type MOS tube M6 is grounded.

Preferably, the second delay branch includes:

the first, second and third inverters INV1, INV2 and INV3;

The input end of the third inverter INV3 is connected with the input signal VI of the power supply, and the output end of the third inverter INV3 is connected with the input end of the second inverter INV 2.

Preferably, the second delay branch further includes:

The output end of the second inverter INV2 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the gate of the fourth N-type MOS transistor M4 in the second level conversion branch.

Preferably, the fourth inverter INV4 and the fifth inverter INV5 in the first delay branch are connected to the first power supply VDD1;

the first inverter INV1, the second inverter INV2 and the third inverter INV3 in the first delay branch are connected to the first power supply VDD1.

Based on the same inventive concept, the embodiment of the application also provides a GPIO level conversion circuit, which comprises a level conversion circuit and at least two inverters connected in series to form an input branch;

The input end of the input branch is connected with input current, the output end of the input branch is connected with the input end of the level conversion circuit, and the output end of the level conversion branch is respectively connected with the input end of the third inverting branch and the input end of the fourth inverting branch;

the output end of the third inverting branch is connected with the grid electrode of a seventh P-type MOS tube, the drain electrode of the seventh P-type MOS tube is connected with a second power supply VDD2, the source electrode of the seventh P-type MOS tube is connected with the drain electrode of an eighth N-type MOS tube, a leading-out terminal between the source electrode of the seventh P-type MOS tube and the drain electrode of the eighth N-type MOS tube is used as the PAD output end of the GPIO level conversion circuit, and the source electrode of the eighth N-type MOS tube is grounded;

The output end of the fourth inverting branch is connected with the grid electrode of the eighth N-type MOS tube, the drain electrode of the eighth N-type MOS tube is connected with the source electrode of the seventh P-type MOS tube, and the drain electrode leading-out terminal of the eighth N-type MOS tube is used as the PAD output end of the GPIO level conversion circuit.

Preferably, the third inverting branch includes not less than three inverters, and the three inverters are connected in series, each of the third inverting branch being connected with the second power supply VDD 2;

The fourth inverting branch includes not less than three inverters, and the three inverters are connected in series, and each of the inverters in the fourth inverting branch is connected to the second power supply VDD 2.

The input end input signal VI of the application processes the VI input signal through the inverter in the first delay branch to obtain a signal in phase with the input signal, outputs the signal to the first level conversion branch, processes the input signal in phase with the VI through the first level conversion branch, and outputs a signal with stable duty ratio to the output end VO. The input end input signal VI is processed by an inverter in the second delay branch circuit to obtain a signal which is opposite to the input signal and is output to the second level conversion branch circuit, and the signal which is opposite to the VI is processed by the second level conversion branch circuit and is output to the output end VO. Therefore, the rising edge and the falling edge of the output signal in the level conversion circuit can be kept consistent in delay, the duty ratio of the output pulse is compensated, and the stability of the duty ratio of the output signal is ensured.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a block diagram of a level shifter circuit according to an embodiment of the present application;

FIG. 2 illustrates a level shift circuit topology according to an embodiment of the present application;

FIG. 3 shows a level shifter circuit package structure according to an embodiment of the present application;

FIG. 4 shows a topology of a GPIO level switch circuit in accordance with an embodiment of the present application;

FIG. 5 is a schematic diagram of the output duty cycle of a prior level shifter circuit of the present application;

fig. 6 shows a schematic diagram of an output duty cycle of a GPIO level conversion circuit according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that the terms "first," "second," and the like herein are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate an azimuth or a positional relationship based on that shown in the drawings.

Referring to fig. 5, the control signal output by the conventional level conversion circuit through the inverter has a delay with respect to the input signal, so that there is a falling delay time on the output falling edge, but there is no rising delay time on the output rising edge, so that the duty ratio of the output signal on the output end is attenuated, resulting in unstable output duty ratio of the level conversion circuit.

An embodiment of the present application provides a level shifter circuit, referring to fig. 1, including:

The level conversion module and the signal delay module;

The operation of fig. 1 is described in detail below.

Referring to fig. 1, an input signal VI is processed by an inverter in a first delay branch to obtain a signal in phase with the input signal VI, and the signal is output to a first level conversion branch, and the signal in phase with the VI is processed by the first level conversion branch to output a signal with a stable duty cycle to an output VO.

The input end input signal VI is processed by an inverter in the second delay branch to obtain a signal which is opposite to the input signal and is output to the second level conversion branch, and the signal which is opposite to the VI is processed by the second level conversion branch to output a signal with a stable duty ratio to the output end VO, so that the stability of the duty ratio of the output signal is improved.

It should be noted that, in the prior art, since the inverter is used to invert the inverting input branch, there is a delay adjustment area on the falling edge of the output signal, and the rising edge rises rapidly without a delay adjustment area, the duty ratio of the output signal is reduced compared with the duty ratio of the input signal, and the duty ratio of the output signal is unstable.

In some specific embodiments, referring to fig. 2, the first level-shifting branch includes:

the first P-type MOS tube M1 and the third N-type MOS tube M3;

Specifically, referring to fig. 2, a gate of the third N-type MOS transistor M3 in the first level shift branch is an input end of the first level shift branch connected to the first delay branch, and a signal output by the first delay branch is an in-phase signal of the input end VI. The grid electrode of the third N-type MOS tube M3 receives the control signal of the first delay branch circuit to control the on-off of the third N-type MOS tube M3, and when the third N-type MOS tube M3 is conducted, the drain electrode of the third N-type MOS tube M3 further controls the grid electrode of the second P-type MOS tube M2, so that the source electrode of the second P-type MOS tube M2 is output. The grid electrode of the first P-type MOS tube M1 is the output end of the first delay branch and is connected to the output end of the level conversion circuit.

In some specific embodiments, referring to fig. 2, the second level-shifting branch includes:

the second P type MOS tube M2 and the fourth N type MOS tube M4;

Specifically, referring to fig. 2, a gate of the fourth N-type MOS transistor M4 in the second level shift branch is an input end of the second level shift branch connected to the second delay branch, and a signal output by the second delay branch is an inverted signal of the input end VI. The grid electrode of the fourth N-type MOS tube M4 receives the control signal of the second delay branch circuit to control the on-off of the fourth N-type MOS tube M4, and when the fourth N-type MOS tube M4 is conducted, the drain electrode of the fourth N-type MOS tube M4 further controls the drain electrode output of the second P-type MOS tube M2.

The basic operation principle of level shifting is explained in detail below with reference to fig. 2. The periods in the following description of the principles are symbolized by the device itself for ease of understanding.

When the input low level is vi=0, the output VB is high level through the inverter INV1, M4 is turned on, vo=0, whereas when the input high level is vi=vdd1, M3 is turned on, the gate voltage of M2 is pulled down, M2 is turned on, and the output vo=vdd2, the level conversion function from VDD1 to VDD2 is realized.

In some specific embodiments, referring to fig. 2, the first delay branch includes:

In some specific embodiments, referring to fig. 2, the second delay branch includes:

the first, second and third inverters INV1, INV2 and INV3;

In some specific embodiments, referring to fig. 2, the fourth inverter INV4 and the fifth inverter INV5 in the first delay branch are connected to the first power supply VDD1;

Specifically, VI is outputted in two-stage inversion through INV4 and INV5, i.e., VA is in phase with VI, and VI is outputted in three-stage inversion through INV3, INV2 and INV1, i.e., VB is in phase with VI. When a low level is input, i.e., vi=0, vb=vdd1, M4 is turned on, vo=0, whereas when a high level is input, i.e., vi=vdd1, va=vdd1, M3 is turned on, the gate voltage of M2 is pulled down, M2 is turned on, and vo=vdd2 is output, thereby realizing a level conversion function from VDD1 to VDD 2.

Based on the same inventive concept, another aspect of the embodiment of the present application also provides a GPIO level conversion circuit, see fig. 4, including a level conversion circuit, at least two inverters connected in series to form an input branch;

Fig. 3 is a package form of the level shift circuit of fig. 2, and the package circuit of fig. 3 is applied to fig. 4 in place of the level shift circuit structure of the load.

In some specific embodiments, referring to fig. 4, the third inverting branch includes not less than three inverters, and the three inverters are connected in series, each of the third inverting branch being connected to the second power supply VDD 2;

Specifically, referring to fig. 5, the output rising edge delay of the level conversion circuit is relatively stable, but the output falling edge delay varies with the power supply voltage, the temperature, the process angle and the like, and presents a certain discreteness, which is represented by that the duty ratio of the output signal of the level conversion circuit also presents a certain discreteness, and the discreteness of the duty ratio of the output signal of the level conversion circuit finally influences the output duty ratio of the GPIO PAD in fig. 4.

The output waveform of the level conversion circuit is shown in figure 6, because the signal delay module circuit outputs rising edges and falling edges which change along with the power supply voltage, the temperature, the process angle and the like, the rising edges and the falling edges have certain discreteness, the rising edges and the falling edges are delayed similarly, the difference between figures 5 and 6 is compared, the duration of the high level output in figure 6 is kept relatively stable, and the duty ratio of the signal output by the level conversion circuit is relatively stable. Through the signal delay module circuit, delay of the input signal VI transmitted to the VA end and delay of the input signal VI transmitted to the VB end are similar, and influence on the VO output duty ratio can be remarkably reduced.

The foregoing embodiments are merely for illustrating the technical solution of the present application, but not for limiting the same, and although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present application in essence.

Claims

1. A level shifter circuit, comprising:

The level conversion module and the signal delay module;

2. The level shifting circuit of claim 1, wherein the first level shifting branch comprises:

the first P-type MOS tube M1 and the third N-type MOS tube M3;

3. The level shifting circuit of claim 1, wherein the second level shifting branch comprises:

the second P type MOS tube M2 and the fourth N type MOS tube M4;

4. The level shifter circuit of claim 1, wherein the first delay branch comprises:

5. The level shifter circuit of claim 4, wherein the first delay branch further comprises:

6. The level shifter circuit of claim 1, wherein the second delay branch comprises:

the first, second and third inverters INV1, INV2 and INV3;

7. The level shifter circuit of claim 6, wherein the second delay branch further comprises:

8. The level shift circuit according to claim 5 or 7, wherein the fourth inverter INV4 and the fifth inverter INV5 in the first delay branch are connected to a first power supply VDD1;

9. A GPIO level conversion circuit, comprising a level conversion circuit according to any one of claims 1 to 8, at least two inverters connected in series to form an input branch;

10. The circuit of claim 9, wherein the circuit further comprises a logic circuit,

The third inverting branch comprises not less than three inverters, and the three inverters are connected in series, and each inverter in the third inverting branch is connected with a second power supply VDD 2;