CN1400660A - Semiconductor module and its manufacture - Google Patents
Semiconductor module and its manufacture Download PDFInfo
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- CN1400660A CN1400660A CN01125051A CN01125051A CN1400660A CN 1400660 A CN1400660 A CN 1400660A CN 01125051 A CN01125051 A CN 01125051A CN 01125051 A CN01125051 A CN 01125051A CN 1400660 A CN1400660 A CN 1400660A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
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Abstract
一种半导体组件及其制造方法,是使形成双面镀铜底板(1)两面之间的导通路用的通路孔(3)为半导体组件(2)的布线图案之间所共有,且将其开孔做成长孔状,沿着将该通路孔(3)对半切开的线切分后制造出半导体组件。其通路孔是在将镀铜层(10)进行腐蚀处理形成开口后,对该开口位置的底板材料(11)进行激光加工处理,形成圆形开孔,通过连续形成多个圆形开孔而形成长孔状。本发明可在通路孔共用化、且一并用树脂密封形成的半导体组件上提高通路孔导通部的可靠性,并提高半导体组件的产品合格率。
A semiconductor component and a manufacturing method thereof, wherein the via hole (3) used for forming a conduction path between two sides of a double-sided copper-plated base plate (1) is shared between the wiring patterns of the semiconductor component (2), and the The opening is made into a long hole shape, and the semiconductor component is manufactured by cutting along the line of cutting the via hole (3) in half. The via hole is formed by corroding the copper plating layer (10) to form an opening, and then performing laser processing on the bottom plate material (11) at the opening position to form a circular opening, which is formed by continuously forming a plurality of circular openings. Form long holes. The invention can improve the reliability of the conduction part of the via hole on the semiconductor component formed by sharing the via hole and sealing it with resin, and improve the product qualification rate of the semiconductor component.
Description
技术领域technical field
本发明涉及在双面镀铜底板上将多个半导体组件的布线图案排成行列状、在规定位置上安装半导体芯片后将整个底板用树脂密封、然后切分制造半导体组件的技术领域,尤其涉及在双面镀铜底板上在半导体组件的端部配置将两面之间导通用的通路孔(ビアホ-ル)、并沿对半切开通路孔的线切分后制造出的半导体组件及其制造方法。The invention relates to the technical field of arranging the wiring patterns of multiple semiconductor components in rows and columns on a double-sided copper-plated base plate, installing semiconductor chips on a specified position, sealing the entire base plate with resin, and then cutting and manufacturing semiconductor components. A semiconductor component manufactured by disposing a via hole (ビアホ-ル) for conducting conduction between the two sides on the end of the semiconductor component on a double-sided copper-plated substrate, and slicing the via hole in half along a line that cuts the via hole in half, and its manufacture method.
背景技术Background technique
以往的一并用树脂密封成形后制造的半导体组件(以下称“组件”)是在双面镀铜底板(以下称“底板”)上设置不贯通底板的通路孔或贯通底板的通路孔,以便将和配置在上面的半导体芯片等作线连接的内部端子与为了表面安装而配设在底板下面的外部端子进行电气连接。In the past, semiconductor components (hereinafter referred to as "components") manufactured after being sealed and molded with resin are provided with via holes that do not penetrate the bottom plate or via holes that penetrate the bottom plate on the double-sided copper-plated bottom plate (hereinafter referred to as “bottom plate”). Internal terminals for wire connection to semiconductor chips etc. disposed on the upper surface are electrically connected to external terminals disposed on the lower surface of the substrate for surface mounting.
而上述的通路孔是用于将多层底板内特定的2层之间进行连接的非贯通开孔,如果是4层以上的多层底板,则也称为内通路孔(インナ-ビア)。另外,与贯通孔相比,其机械强度高,且在树脂密封工序中可省略防止树脂材料进入贯通孔的工序。The aforementioned via hole is a non-through hole for connecting specific two layers in a multilayer substrate, and is also called an inner via hole (inna-via) in a multilayer substrate with more than 4 layers. In addition, the mechanical strength is higher than that of the through hole, and the step of preventing the resin material from entering the through hole can be omitted in the resin sealing step.
而且将上述通路孔等配置在组件的外周端部,以使相邻的组件之间能够共用该通路孔,且在切分树脂密封体时沿对半切开通路孔等的线来进行切分,以减少底板对组件的占有比例。And arrange the above-mentioned via holes and the like at the outer peripheral end of the module so that the via holes can be shared between adjacent modules, and when cutting the resin sealing body, cut the via holes and the like in half. , to reduce the proportion of the base plate to the components.
关于上述通路孔的形成方法,如特开平10-294400所公开的,有的是用电镀层等导体将在底板上配置形成的贯通孔堵塞,还有的是将单面的镀铜层用腐蚀法腐蚀成圆形后,以保留反面镀铜层的形式照射激光,以除去底板材料(环氧树脂、玻璃环氧树脂等),然后对经过加工的内周面进行导通处理。Regarding the formation method of the above-mentioned via holes, as disclosed in JP-P-10-294400, some of them use conductors such as electroplating layers to block the through holes formed on the bottom plate, and some of them use corrosion methods to corrode the copper plating layer on one side into a circular shape. After forming, irradiate the laser in the form of retaining the copper plating layer on the reverse side to remove the base material (epoxy resin, glass epoxy resin, etc.), and then conduct conduction treatment on the processed inner peripheral surface.
然而,上述特开平10-294400公开的封闭贯通孔的方法需要特殊技术来保证封闭过程中的机械强度等,导致制造成本上升。However, the method of sealing the through-hole disclosed in the above-mentioned Japanese Unexamined Patent Publication No. 10-294400 requires special technology to ensure mechanical strength during the sealing process, which leads to an increase in manufacturing cost.
近年来,在4、6、8层以上的所谓多层底板在采用在底板叠层时形成内通路孔的所谓装配法。In recent years, so-called multilayer substrates having 4, 6, or 8 or more layers have adopted a so-called assembly method in which internal via holes are formed when the substrates are laminated.
另外,采用从镀铜层的一面形成通路孔的方法时,首先要通过腐蚀处理将表层的镀铜层腐蚀成圆形后,照射激光以除去底板材料,且为了保留反面镀铜层而进行输出调节处理,故其步骤设定复杂微妙,且其截面形状不是完全的圆柱形,如图5(A)所示,会在周边部残留处理屑D的残渣和未削除部。结果,在对此通路孔的内部镀层以使之导通时,如图5(B)所示,不但不能有足够的接触部分使镀层与反面的镀铜层导通,而且在该接触部分会存在界面E,在将通路孔对半切开时或有外部冲击时,如图5(C)所示,接触部分会发生剥离,导致导通不良。In addition, when using the method of forming via holes from one side of the copper plating layer, the copper plating layer on the surface layer must be etched into a circular shape by etching first, and then irradiated with laser light to remove the bottom plate material, and output to retain the copper plating layer on the reverse side. In the adjustment process, the step setting is complicated and delicate, and the cross-sectional shape is not a perfect cylinder, as shown in FIG. 5(A), residues of processing chips D and uncut parts remain in the peripheral part. As a result, when the internal plating of this via hole is used to conduct it, as shown in Figure 5 (B), not only can there not be enough contact parts to make the plating layer conduct with the copper plating layer on the reverse side, but also the contact part will There is an interface E, and when the via hole is cut in half or when there is an external impact, as shown in FIG. 5(C), the contact part will be peeled off, resulting in poor conduction.
发明内容Contents of the invention
本发明正是为了解决上述问题,目的在于提供一种半导体组件及其制造方法,是在双面镀铜底板的通路孔通用化且进行总体树脂密封成形的半导体组件及其制造方法中,用通路孔可靠地形成两面之间的导通路,同时在将通路孔对半切开时,导通部的接触部分不会剥离,可靠性好、产品合格率高。The present invention is just to solve the above-mentioned problems, and the purpose is to provide a semiconductor component and its manufacturing method. The hole reliably forms a conductive path between the two sides, and at the same time, when the via hole is cut in half, the contact part of the conductive part will not be peeled off, so the reliability is good and the product qualification rate is high.
为了实现上述目的,本发明的半导体组件及其制造方法如下构成。In order to achieve the above object, the semiconductor module and its manufacturing method of the present invention are constituted as follows.
本发明的半导体组件是在双面镀铜底板1的两面之间将多个半导体组件2的布线图案排成行列状,且使形成前述底板1两面之间的导通路用的通路孔3为各个单位的半导体组件2的布线图案所共有,且将其开孔做成长孔状,在该布线图案的规定位置上安装半导体芯片20并布线后将该底板1整体用树脂密封,并沿着将该通路孔3对半切开的线上切分后制造出来的。Semiconductor component of the present invention is that the wiring patterns of a plurality of
本发明的半导体组件的制造方法是使形成双面镀铜底板1两面之间的导通路用的通路孔3为各个单位的半导体组件2的布线图案所共有,将多个半导体组件2的布线图案排列成行列状,并在规定位置上安装半导体芯片20后将该底板1整体用树脂密封,然后沿着将前述通路孔3对半切开的线切分制造出半导体组件2,其特点是,将前述通路孔3做成长孔形状。The manufacturing method of the semiconductor component of the present invention is to make the
另外,也可以在将双面镀铜底板1的一面镀铜层10的规定位置用腐蚀处理开孔后,通过激光加工处理将该开孔位置的底板材料11削除以形成圆形开孔31,并通过连续地形成多个圆形开孔31而形成长孔状的开孔。In addition, after the prescribed position of the
还可以在树脂密封工序中在阴模40与树脂密封用的树脂25a之间夹入氟树脂薄膜40d。In the resin sealing step, a
上述附图标记是为了便于理解本发明而附加的,不言而喻,本发明不限于附图所示的形态。The above reference numerals are added to facilitate understanding of the present invention, and it goes without saying that the present invention is not limited to the forms shown in the drawings.
附图说明Description of drawings
图1是表示本实施形态的半导体组件外观的立体图。FIG. 1 is a perspective view showing the appearance of a semiconductor package according to this embodiment.
图2是本实施形态的配置有通路孔的底板的外观图。Fig. 2 is an external view of a base plate provided with via holes according to the present embodiment.
图3是表示本实施形态的通路孔形成顺序的剖视图。Fig. 3 is a cross-sectional view showing the procedure of forming via holes in the present embodiment.
图4是表示本实施形态的树脂密封工序(A)、树脂密封工序的局部放大(B)及切断工序(C)的剖视图。4 is a cross-sectional view showing a resin sealing step (A), a partially enlarged resin sealing step (B) and a cutting step (C) of the present embodiment.
图5是表示传统通路孔的剖视图。Fig. 5 is a sectional view showing a conventional via hole.
具体实施方式Detailed ways
以下结合附图详细说明本发明的半导体组件及其制造方法的实施形态。图1是表示本实施形态的半导体组件外观的立体图。图2是本实施形态的配置有通路孔的底板的外观图。图3是表示本实施形态的通路孔形成顺序的剖视图。图4是表示本实施形态的树脂密封工序(A)、树脂密封工序的局部放大(B)及切断工序(C)的剖视图。图5是表示传统通路孔的剖视图。Embodiments of the semiconductor device and its manufacturing method of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a perspective view showing the appearance of a semiconductor package according to this embodiment. Fig. 2 is an external view of a base plate provided with via holes according to the present embodiment. Fig. 3 is a cross-sectional view showing the procedure of forming via holes in the present embodiment. 4 is a cross-sectional view showing a resin sealing step (A), a partially enlarged resin sealing step (B) and a cutting step (C) of the present embodiment. Fig. 5 is a sectional view showing a conventional via hole.
本实施形态1个单位的组件如图1所示,由装载在底板1上的平台21上的半导体芯片20、配置在该平台21周围的线连接用内部端子22、连接半导体芯片20的电极20a和内部端子22的导线23、底板1背面的外部端子24、在组件2的端部将内部端子22与外部端子24导通用的经过对半切开的长孔状通路孔3构成,且整体用树脂密封。以上结构与传统结构相同,故省略详细说明。As shown in FIG. 1 , one unit of the present embodiment consists of a semiconductor chip 20 mounted on a platform 21 on a
以下详细说明本发明的半导体组件及其制造方法中的要点、即通路孔3的实施形态。The main points of the semiconductor device and its manufacturing method of the present invention, that is, the embodiment of the
如图2所示,首先对一面的镀铜层10进行腐蚀处理,在规定位置上形成规定个数的长孔状开口部30。本实施形态的该开口部30尺寸为直径0.15mm、长度0.35mm,其配置位置如此设定:当在后道工序中将配置图案排列成行列状时位于该图案的端部,当沿通路孔3的长度方向的中心线切断时,位于为相邻的组件2所共有的位置。另外,为了进一步提高散热效果,也可在组件2的内面配置散热用通路孔32(图2中双点划线所示部位)。As shown in FIG. 2 , firstly, the
然后,如图3(A)所示,首先照射经过输出调节的激光,使激光接触开口部30长度方向的一端,且不能损坏另一面(反面)的镀铜层10,以除去树脂层11,形成大致圆柱形的开孔31a。接着如图(B)所示,使激光接触开口部30的长度方向另一端,除去树脂层11,以形成大致圆柱形的开孔31b。最后如图(C)所示,用激光照射上述经过照射的位置之间的中间部,除去残余的树脂层11,以形成开孔31c。结果,3个开孔31a、31b、31c就连成1个长孔状通路孔3。然后用电解电镀法在通路孔3的内部进行导通处理。在该工序中,本实施形态的通路孔3如图3(C)所示,其截面为研钵状,但因其为长孔形状,故能保证较多的接触面积。Then, as shown in Fig. 3 (A), at first irradiate the laser through the output adjustment, make the laser contact one end of the longitudinal direction of the
本实施形态的激光加工是用装有电镀系统的激光打孔机进行高速(譬如1000孔/1秒)处理。The laser processing of this embodiment is performed at a high speed (for example, 1000 holes/1 second) by a laser drilling machine equipped with an electroplating system.
然后用传统的照相法在底板1上进行印相、显影、溶解处理,由此在规定位置上形成规定数量的布线图案,即平台21、内部端子22及外部端子24等,并在平台21上装载半导体芯片20,再进行导线连接。Then print, develop, and dissolve on the
然后将整个底板1放入铸型模4中,并充填密封用的树脂25a,形成树脂密封体25。在该铸型模4的阴模40的底面40a上,截面为V字形的凸条部40b排成格子状,该凸条部40b的棱线40c与连接底板1上的通路孔3中心的线上下对齐。用该凸条部40b在树脂密封体25的上面形成与通路孔3上下对齐的排成格子状的V字槽25b(以下称V字槽。另外,为了有利于阴模40与树脂25a之间的脱模性,在该阴模40的底面40a夹入了氟树脂薄膜40d。Then the
最后将整个底板1从铸型模4脱下并固定在切断装置5上,用切断刀50沿着V字槽25b切断,切分成每1单位的组件2。此时,由于切断刀50的厚度不到通路孔3的圆周部,因此该通路孔3被分割后能够作为导通装置而将各相邻组件2的内部端子22与外部端子连接。而且由于该通路孔3的分割面与组件2的树脂密封体25的切断面大致一致,故底板1的部分不会从组件2的外周轮廓伸出,可实现小型化。Finally, the
采用上述本发明的半导体组件及其制造方法时,由于通路孔做成长孔状开口,故提高了通路孔内周面的导通处理时导通部的物理性连接强度,同时通路孔对半切开时的剥离性等亦较好,提高了组件电气连接的可靠性。When adopting the above-mentioned semiconductor component of the present invention and its manufacturing method, since the via hole is made as a long-hole-shaped opening, the physical connection strength of the conduction portion during the conduction process on the inner peripheral surface of the via hole is improved, and the via hole is cut in half simultaneously. The peelability when opening is also good, which improves the reliability of the electrical connection of the component.
这一点有助于提高组件制造时的产品合格率,可提高生产效率,降低制造成本。This helps to improve the product qualification rate during component manufacturing, which can improve production efficiency and reduce manufacturing costs.
Claims (4)
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