CN206040643U - Electrostatic Discharge ESD Protection Structure and Chip Containing It - Google Patents

Abstract

The utility model discloses a static electricity discharge ESD protection architecture and contain its chip, ESD protection architecture includes: a substrate. Side by side first to the 6th trap region on the substrate, first first kind doped region in the first trap region, first second type doped region and first second type bars oxygen district, the 7th second type doped region, the 7th first kind doped region and second first kind bars oxygen district and the 8th first kind doped region in the second trap region, the second type doped region of first and second trap region handing -over department, third first kind doped region in the third trap region, fourth second type doped region in the fourth trap region, the 8th second type doped region, second type bars oxygen district, the 9th second type doped region and the 9th first kind doped region in the 5th trap region, the 6th first kind doped region, the 6th second type doped region and first first kind bars oxygen district in the 6th trap region, the 5th first kind doped region of the 5th and the 6th trap region handing -over department. Its ESD protection effect and low breech lock risk that has the ideal.

Description

Electrostatic Discharge ESD Protection Structure and Chip Containing It

technical field

The utility model relates to the technical field of semiconductors, in particular to an electrostatic discharge ESD protection structure and a chip containing the same.

Background technique

ESD is currently one of the most important causes of IC product failure. This kind of damage is very severe, and in most cases it will directly burn the chip or cause irreversible damage. ESD discharge is inevitable in almost the entire process of IC manufacturing, transportation, packaging, testing and application. Designers will consider the ESD protection of the chip in the initial design of the product, so that the IC itself has a certain ability to resist ESD. .

SCR (Silicon Controlled Rectifier) has excellent hysteresis characteristics, the minimum hysteresis voltage is only about 2V, the heat generation is much lower than other devices under the same current, and it has excellent ESD protection ability. However, low hysteresis voltage (approximately 2V) is a double-edged sword in the field of ESD protection for existing complementary LVTSCRs. While ensuring high ESD leakage capability, there is a high risk of latch-up. For example, when LVTSCR is turned on by mistake due to external interference, the voltage at both ends of the device will hysteresis to about 2V. If the normal working voltage is 5V, high and low level crosstalk will occur at this time, leakage, and even directly burn the chip.

Therefore, the current ESD protection structure still needs to be improved.

Utility model content

The utility model aims to solve one of the technical problems in the related art at least to a certain extent. For this reason, an object of the utility model is to propose an electrostatic discharge ESD protection structure, which has an ideal ESD protection capability, can simultaneously eliminate the risk of SCR latch-up, or can be integrated in the existing CMOS process, No additional mask and production steps are required.

In one aspect of the utility model, the utility model provides an electrostatic discharge ESD protection structure. According to an embodiment of the present invention, the electrostatic discharge ESD protection structure includes: a substrate; first to sixth well regions formed side by side on the substrate; a first well region disposed in the first well region The first type doped region, the first second type doped region and the first second type gate oxide region; the seventh second type doped region, the seventh first type doped region arranged in the second well region The impurity region and the second first type gate oxide region and the eighth first type doped region; the second second type doped region arranged at the junction of the first well region and the second well region; arranged at the junction of the first well region and the second well region; The third first type doped region in the third well region; the fourth second type doped region arranged in the fourth well region; the eighth second type doped region arranged in the fifth well region The second type doped region, the second second type gate oxide region, the ninth second type doped region and the ninth first type doped region; the sixth first type doped region arranged in the sixth well region The impurity region, the sixth second-type doped region and the first first-type gate oxide region; the fifth first-type doped region arranged at the junction of the fifth well region and the sixth well region.

The inventors found that the electrostatic discharge ESD protection structure of the present utility model has ideal ESD protection capability, can effectively eliminate the risk of SCR latch-up, and can be integrated in the existing CMOS process without adding additional photomasks and production step. In addition, the electrostatic discharge ESD protection structure of the present invention is provided with a MOS structure with a shunt effect, so that it is more difficult to trigger the SCR, and the above-mentioned MOS structure increases the distance between the two ends of the SCR on the layout, making the hysteresis voltage higher than 5V, which eliminates the risk of latch-up. At the same time, the above-mentioned MOS structure itself has strong ESD protection capability, which can largely compensate for the decrease in ESD protection performance of the SCR due to the increase in the hysteresis voltage.

In another aspect of the utility model, the utility model provides a chip. According to an embodiment of the present invention, the chip includes the aforementioned ESD protection structure. All the features and advantages of the electrostatic discharge ESD protection structure described above are applicable to this chip, and will not be repeated here.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure diagram of an electrostatic discharge ESD protection structure according to an embodiment of the present invention.

Fig. 2 shows a schematic cross-sectional structure diagram of an electrostatic discharge ESD protection structure according to another embodiment of the present invention.

Fig. 3 shows a schematic cross-sectional structure diagram of an electrostatic discharge ESD protection structure according to another embodiment of the present invention.

FIG. 4 shows a schematic cross-sectional structure diagram of an electrostatic discharge ESD protection structure according to yet another embodiment of the present invention.

Fig. 5 shows a schematic cross-sectional structure diagram of an electrostatic discharge ESD protection structure according to another embodiment of the present invention.

FIG. 6 shows a schematic diagram of an external circuit of the electrostatic discharge ESD protection structure shown in FIG. 5 .

FIG. 7 shows an equivalent circuit diagram of the electrostatic discharge ESD protection structure shown in FIG. 5 .

FIG. 8 shows a schematic diagram of an IV curve of the electrostatic discharge ESD protection structure shown in FIG. 5 .

detailed description

Embodiments of the present utility model are described in detail below. The embodiments described below are exemplary, and are only used to explain the present utility model, but should not be construed as limiting the present utility model. If no specific technique or condition is indicated in the examples, it shall be carried out according to the technique or condition described in the literature in this field or according to the product specification. The reagents or instruments used were not indicated by the manufacturer, and they were all commercially available conventional products.

In one aspect of the utility model, the utility model provides an electrostatic discharge ESD protection structure. According to an embodiment of the present utility model, referring to FIG. 1, the electrostatic discharge ESD protection structure includes: a substrate 100; a first well region 101, a second well region 102, and a third well region 103 formed side by side on the substrate 100 , the fourth well region 104, the fifth well region 105 and the sixth well region 106; the first first-type doped region 112, the first second-type doped region 113 and the second a second type gate oxide region 114; the seventh second type doped region 131, the seventh first type doped region 132, the second first type gate oxide region 133 and the eighth The first type doped region 134; the second second type doped region 115 arranged at the junction of the first well region 101 and the second well region 102; the third first type doped region arranged in the third well region 103 the impurity region 119; the fourth second-type doped region 121 arranged in the fourth well region 104; the eighth second-type doped region 135 arranged in the fifth well region 105, the second second-type gate Oxygen region 136, ninth second-type doped region 137 and ninth first-type doped region 138; sixth first-type doped region 127, sixth second-type doped region The impurity region 128 and the first first type gate oxide region 126 ; the fifth first type doped region 125 disposed at the junction of the fifth well region 105 and the sixth well region 106 . The inventors found that the electrostatic discharge ESD protection structure of the present utility model has ideal ESD protection capability, can effectively eliminate the risk of SCR latch-up, and can be integrated in the existing CMOS process without adding additional photomasks and production step. In addition, the electrostatic discharge ESD protection structure of the present invention is provided with a MOS structure with a shunt effect, so that it is more difficult to trigger the SCR, and the above-mentioned MOS structure increases the distance between the two ends of the SCR on the layout, making the hysteresis voltage higher than 5V, which eliminates the risk of latch-up. At the same time, the above-mentioned MOS structure itself has strong ESD protection capability, which can largely compensate for the decrease in ESD protection performance of the SCR due to the increase in the hysteresis voltage.

It should be noted that, in the description methods used herein, "first type doped region" and "second type doped region" and "first type gate oxide region" and "second type gate oxide region" in " Both "first type" and "second type" refer to different conductivity types, namely P type or N type.

According to the embodiment of the present invention, the conductivity types of the first-type doped region and the second-type doped region are not particularly limited, as long as they do not affect the realization of their functions, those skilled in the art can select according to needs. In some embodiments of the present invention, the first-type doped region is an N-type doped region, and the second-type doped region is a P-type doped region.

According to the embodiment of the present invention, the conductivity types of the substrate and the first to sixth well regions are not particularly limited, as long as the corresponding functions of the ESD protection structure can be realized, those skilled in the art can select according to needs. In some embodiments of the present utility model, the substrate 100 is a P-type substrate, the first well region 101, the third well region 103 and the fifth well region 105 are N-type, the second well region 102, the fourth well region 104 and the sixth well region 106 are P-type. Those skilled in the art can understand that, in some other embodiments of the present invention, the conductivity types of the substrate and the first to sixth well regions may also be opposite to those described above.

According to an embodiment of the present invention, referring to FIG. 2 , the electrostatic discharge ESD protection structure further includes: a first field oxygen isolation region 111 and a fifth field oxygen isolation region 111 arranged on the sides of the first well region 101 and the sixth well region 106 District 129.

According to an embodiment of the present invention, referring to FIG. 3, the electrostatic discharge ESD protection structure further includes: a second field oxygen isolation region 118 arranged at the junction of the second well region 102 and the third well region 103; The third field oxygen isolation region 120 at the junction of the region 103 and the fourth well region 104 ; and the fourth field oxygen isolation region 122 disposed at the junction of the fourth well region 104 and the fifth well region 105 .

According to an embodiment of the present utility model, referring to FIG. 4, the first first type doped region 112, the first second type doped region 113, the first second type gate oxide region 114, the third first type doped region 119 , the second second-type gate oxide region 136 , the ninth second-type doped region 137 , and the ninth first-type doped region 138 are all connected to the power supply (VDD).

According to an embodiment of the present invention, referring to FIG. 4, the fourth second type doped region 121, the sixth second type doped region 128, the sixth first type doped region 127, the first first type gate oxide 126 , the seventh second-type doped region 131 , the seventh first-type doped region 132 , and the second first-type gate oxide region 133 are all connected to the ground (GND).

According to an embodiment of the present invention, referring to FIG. 4 , the eighth first-type doped region 134 and the eighth second-type doped region 135 are connected to a bonding pad.

In the following, the substrate 100 is a P-type substrate (Psub), the first well region 101, the third well region 103 and the fifth well region 105 are N-type (NW), and the second well region 102, the fourth well region 104 and The sixth well region 106 is P-type (PW), and the first type doped region is an N+ doped region, and the second type doped region is an ESD protection structure of a P+ doped region as an example to describe in detail the ESD protection of the present utility model The specific structure and working principle of the structure. details as follows:

Referring to Fig. 5, this ESD protection structure comprises P-type substrate (100), generates six parallel well regions on P-type substrate, is respectively the first N well region (101), the first P well region (102) , the second N well region (103), the second P well region (104), the third N well region (105), and the third P well region (106). The first N+ doped region (112), the first P+ doped region (113) and the first PMOS gate oxide region (114) are arranged in the first N well region, and the seventh P+ doped region is arranged in the first P well region. The impurity region (131), the seventh N+ doping region (132), the second NMOS gate oxide region (133) and the eighth N+ doping region. A second P+ doping region (115) is provided at the junction of the first N well region and the first P well region. A third N+ doping region (119) is arranged in the second N well region, and a fourth P+ doping region (121) is arranged in the second P well region. An eighth P+ doped region (135), a second PMOS gate oxide region, a ninth P+ doped region (137) and a ninth N+ doped region (138) are arranged in the third N well region. A sixth N+ doping region (127), a sixth P+ doping region (128) and a first NMOS gate oxide region (126) are arranged in the third P well region. A fifth N+ doping region (125) is provided at the junction of the third N well region and the third P well region. A first field oxygen isolation region (111) and a fifth field oxygen isolation region (129) are respectively arranged on the side of the first N well region and the third P well region. A second field oxygen isolation region (118) is provided at the junction of the first P well region and the second N well region, and a third field oxygen isolation region (120) is provided at the junction of the second P well region and the second N well region. ), a fourth field oxygen isolation region (122) is provided at the junction of the second P well region and the third N well region.

6 is a schematic diagram of an external circuit of the ESD protection structure shown in FIG. 5, the first N+ doped region, the first P+ doped region, the first PMOS gate oxide region, the third N+ doped region, and the second PMOS gate oxide region , the ninth P+ doped region, and the ninth N+ doped region are connected to the power supply (VDD) through contact holes. The fourth P+ doped region, the sixth P+ doped region, the sixth N+ doped region, the first NMOS gate oxide region, the seventh P+ doped region, the seventh N+ doped region, and the second NMOS gate oxide region all pass through The contact hole is connected to ground (GND). The eighth N+ doped region and the eighth P+ doped region are connected to a bonding pad (Bonding Pad) through a contact hole.

FIG. 7 is an equivalent circuit diagram of the ESD protection structure shown in FIG. 5 . The emitter, base and collector of the parasitic PNP transistor Q11 are respectively composed of a first P+ doping region (113), a first N well region (101) and a first P well region (102). The emitter, the base and the collector of the parasitic NPN transistor Q12 are respectively composed of the second N+ doped region (116), the first P well region (102) and the first N well region (101). The emitter, the base and the collector of the parasitic PNP transistor Q13 are respectively composed of the fifth P+ doping region (124), the third N well region (105) and the third P well region (106). The emitter, base and collector of the parasitic NPN transistor Q14 are respectively composed of the sixth N+ doped region (127), the third P well region (106) and the third N well region (105). The source level, the gate, the drain and the substrate of the PMOS transistor M11 are respectively composed of the first P+ doped region (113), the first PMOS gate oxide region (114), the second P+ doped region (115) and the first N Well region (101) composition. The source level of the NMOS transistor M12, the gate, the drain and the substrate are respectively composed of the sixth N+ doped region (127), the first NMOS gate oxide region (126), the fifth N+ doped region (125) and the third P Well region (106) composition. R11 refers to the N well resistance between the first N+ doping region (112) and the first P+ doping region (113), R12 refers to the sixth N+ doping region (127) and the sixth P+ doping region (128 ) between the P-well resistors. R13 refers to the N well resistance between the fourth N+ doping region (123) and the fifth N+ doping region (125). R14 refers to the P well resistance between the second P+ doping region (115) and the third P+ doping region (117). R15 refers to the N well resistance between the fourth N+ doping region (123) and the fifth P+ doping region (124). R16 refers to the P well resistance between the second N+ doping region (116) and the third P+ doping region (117). The anode and cathode of the diode D11 are formed by the fifth P+ doped region (124) and the fourth N+ doped region (123) respectively, and the anode and cathode of the diode D12 are respectively formed by the third P+ doped region (117) and the second N+ The doped region (116) constitutes. The source level, the gate, the drain and the substrate of the PMOS transistor M21 are respectively composed of the ninth P+ doped region (137), the second PMOS gate oxide region (136), the eighth P+ doped region (135) and the third N Well region (105) composition. The source level of the NMOS transistor M22, the gate, the drain and the substrate are respectively composed of the seventh N+ doped region (132), the second NMOS gate oxide region (133), the eighth N+ doped region (134) and the second P well region (102). R21 refers to the equivalent P well resistance between the second P+ doping region (115) and the eighth N+ doping region (134), and R22 refers to the fifth N+ doping region (125) and the eighth P+ doping region The equivalent N-well resistance between (135).

Specifically, when the pad is subjected to static electricity, the following four types of ESD discharge may occur. Various ESD discharge types The ESD protection structure shown in Figure 5 below works as follows:

(1) The pad releases positive electricity to GND: When ESD occurs, the static electricity will directly reach the drain terminal (134) of M22, and at the same time pass through the emitter junction of R22 and Q13, and reach the drain terminal (125) of M12 and the collector of Q14 (105). The breakdown voltage of the drain terminal of M22 is slightly lower than the breakdown voltage of the drain terminal of M12, and far lower than the breakdown voltage of the collector junction of Q14. Static electricity will be released from the drain terminal of M22 to GND first, and the pad voltage will continue to increase during this process. Large, when the voltage increases to near the breakdown voltage of the drain terminal of M12, static electricity will be released from the drain terminal (125) of M12 to PW (106), and then flow to GND through R12. When the voltage on R12 is higher than 0.7V, the emitter junction of Q14 is turned on, because the collector (105) of Q14 is at a high potential, prompting Q14 to enter the amplification region, and the current of the collector (105) increases obviously. The collector current increases, resulting in an increase in the emitter (124) current of Q13 and an increase in the voltage drop of R22, and the increase in the emitter current will prompt an increase in the collector (106) current of Q13. At the same time, the increase of the collector current of Q13 will cause a higher voltage drop across R12, so that the emitter junction of Q14 is further turned on, forming a complete positive feedback process. The end result is that the SCR latches up for an extremely short period of time. M22 has a shunt phenomenon when the initial ESD occurs, causing the SCR to require a larger trigger current and reducing the risk of latch-up. The size of R22 can be properly adjusted to maintain the SCR hysteresis voltage at a level slightly higher than the operating voltage to eliminate the risk of latch-up. At the same time, since an NMOS is connected in parallel next to the SCR, it can supplement the ESD protection capability of the SCR lost due to the increase of the hysteresis voltage. Ultimately, the ESD protection structure of the present invention has ideal ESD protection performance.

(2) The pad releases negative electricity to GND: at this time, D12 is turned on positively, which is very suitable for ESD discharge.

(3) The pad releases positive electricity to VDD: at this time, D11 is positively turned on, which is very suitable for ESD discharge.

(4) The pad releases negative electricity to VDD: When ESD occurs, the static electricity will directly reach the drain terminal (135) of M21, and at the same time pass through the emitter junction of R21 and Q12, and reach the drain terminal of M11 (115) and the collector of Q14 ( 102). The breakdown voltage of the drain terminal of M21 is slightly lower than the breakdown voltage of the drain terminal of M11, and far lower than the breakdown voltage of the collector junction of Q11. Static electricity will be released from the drain terminal of M21 to VDD first, and the pad voltage will continue to increase during this process. Large, when the voltage increases to near the breakdown voltage of the drain of M11, static electricity will be released from the drain (115) of M11 to NW (101), and then flow to VDD through R11. When the voltage on R11 is higher than 0.7V, the emitter junction of Q11 is turned on, and because the collector (102) of Q11 is at a low potential, Q11 is prompted to enter the amplification region, and the current of the collector (102) increases obviously. The collector current increases, resulting in an increase in the emitter (116) current of Q12 and an increase in the voltage drop of R21, and the increase in the emitter current will promote the increase in the collector (101) current of Q12. At the same time, the increase of the collector current of Q12 will cause a higher voltage drop across R11, so that the emitter junction of Q11 is further turned on, forming a complete positive feedback process. The end result is that the SCR latches up for an extremely short period of time. M21 has a shunt phenomenon when the initial ESD occurs, causing the SCR to require a larger trigger current and reducing the risk of latch-up. The size of R21 can be properly adjusted to maintain the SCR hysteresis voltage at a level slightly higher than the operating voltage to eliminate the risk of latch-up. At the same time, since a PMOS is connected in parallel next to the SCR, it can supplement the ESD protection capability of the SCR lost due to the increase of the hysteresis voltage. Ultimately, the ESD protection structure of the present invention has ideal ESD protection performance. .

FIG. 8 is a schematic diagram of the IV curve of the ESD protection structure shown in FIG. 5 . Due to the MOS shunt effect, the SCR requires a larger trigger current, which reduces the risk of latch-up. Even if the SCR is falsely triggered, the hysteresis voltage will be slightly greater than the operating voltage, which can completely eliminate the risk of latch-up. At the same time, connecting MOS tubes in parallel is also an effective way to release ESD, which significantly increases the ESD protection capability of the device.

Preferably, the channel length of M22 in the present invention should be slightly lower than that of M12, and the channel length of M21 should be slightly lower than that of M11, so as to ensure the shunting effect. Appropriately adjusting the distance between the second P+ doped region (115) and the seventh P+ doped region, the distance between the fifth N+ doped region (125) and the ninth N+ doped region (138), can make the hysteresis voltage of the device slightly higher than the operating voltage to eliminate the risk of latch-up.

The ESD protection structure of the utility model can reduce or eliminate the risk of SCR ESD protection latch-up while almost not losing the ESD protection ability of the device. The structure can be integrated in an existing CMOS process without adding additional photomasks and production steps.

In another aspect of the utility model, the utility model provides a chip. According to an embodiment of the present invention, the chip includes the aforementioned ESD protection structure. All the features and advantages of the electrostatic discharge ESD protection structure described above are applicable to this chip, and will not be repeated here.

In the description of the present utility model, it should be understood that the terms "first" and "second" are only used for descriptive purposes, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the number of indicated technical features . Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present utility model, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, the first feature may be in direct contact with the first feature or the first feature and the second feature through an intermediary indirect contact. Moreover, "above", "above" and "above" the first feature on the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. "Below", "beneath" and "beneath" the first feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is less horizontally than the second feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structures, materials or features are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and should not be construed as limitations of the present invention, and those skilled in the art are within the scope of the present invention. Variations, modifications, substitutions and variations can be made to the above-described embodiments.

Claims (7)

1. a kind of Electro-static Driven Comb esd protection structure, it is characterised in that include：

Substrate；

The first to the 6th well region of the substrate is formed in side by side；

It is arranged on the first first kind doped region among first well region, the first Second Type doped region and the first Equations of The Second Kind Type grid oxygen area；

It is arranged on the 7th Second Type doped region in second well region, the 7th first kind doped region and second first kind Grid oxygen area and the 8th first kind doped region；

It is arranged on the second Second Type doped region of first well region and the second well region junction；

The 3rd first kind doped region being arranged among the 3rd well region；

The 4th Second Type doped region being arranged among the 4th well region；

It is arranged on the 8th Second Type doped region among the 5th well region, the second Second Type grid oxygen area, the 9th Equations of The Second Kind Type doped region and the 9th first kind doped region；

It is arranged on the 6th first kind doped region among the 6th well region, the 6th Second Type doped region and first first kind Type grid oxygen area；

It is arranged on the 5th first kind doped region of the 5th well region and the 6th well region junction.

2. Electro-static Driven Comb esd protection structure as claimed in claim 1, it is characterised in that the first kind doped region is N-type Doped region, the Second Type doped region are p-type doped region.

3. Electro-static Driven Comb esd protection structure as claimed in claim 1, it is characterised in that the substrate is P type substrate, described First well region, the 3rd well region and the 5th well region are N-type, and second well region, the 4th well region and the 6th well region are p-type.

4. Electro-static Driven Comb esd protection structure as claimed in claim 2, it is characterised in that also include：

It is arranged on first oxygen isolation area and the 5th oxygen isolation area in the first well region and the 6th well region side.

5. Electro-static Driven Comb esd protection structure as claimed in claim 2, it is characterised in that also include：

It is arranged on second oxygen isolation area of second well region and the 3rd well region junction；

It is arranged on the 3rd oxygen isolation area of the 3rd well region and the 4th well region junction；And

It is arranged on the 4th oxygen isolation area of the 4th well region and the 5th well region junction.

6. Electro-static Driven Comb esd protection structure as claimed in claim 1, it is characterised in that wherein, first first kind is mixed Miscellaneous area, the first Second Type doped region, the first Second Type grid oxygen area, the 3rd first kind doped region, institute State the second Second Type grid oxygen area, the 9th Second Type doped region, the 9th first kind doped region with power supply phase Even；

The 4th Second Type doped region, the 6th Second Type doped region, the 6th first kind doped region are described First first kind grid oxygen area, the 7th Second Type doped region, the 7th first kind doped region, described the two the first Type grid oxygen area is connected to the ground；

8th first kind doped region and the 8th Second Type doped region are connected with pad.

7. a kind of chip, it is characterised in that include the Electro-static Driven Comb esd protection structure as described in any one of claim 1-6.