CN211352165U - Voltage-controlled delay circuit - Google Patents

Abstract

The utility model discloses a voltage-controlled delay circuit receives first difference input signal and second difference input signal, and right first difference input signal with second difference input signal exports first difference output signal and second difference output signal after delaying, wherein, voltage-controlled delay circuit includes a plurality of cascaded delay modules, every delay module in a plurality of delay modules is adjusted according to control signal first difference input signal with the output delay time of second difference input signal exports first difference output signal and second difference output signal. The voltage-controlled delay circuit realizes the function of an active inductor through an active MOS device under the condition of ensuring that the broadband stable delay time can be generated, and a passive inductor is not needed. The area of a chip is effectively reduced, the frequency bandwidth is improved, the cost is reduced, and the adjustable delay time is realized.

Description

Voltage-controlled delay circuit

Technical Field

The utility model relates to an integrated circuit technical field, concretely relates to voltage-controlled delay circuit.

Background

With the increasing frequency of signals, the influence of the timing characteristics of the signals on the circuit performance becomes more and more important. The timing of the signals can be synchronized by compensating for the delay differences between the circuits, and the delay unit can compensate for the delay differences between the circuits. The delay locked loop (dll) is a locked loop circuit which is composed of delay units and can generate fixed delay, and has its specific advantages compared with the traditional locked loop. With the increasing requirement for delay time, the delay in the circuit is realized by software programming to the design of using a delay circuit. In the time delay circuit, the time delay circuit is developed more quickly and better due to the proposal and design of different circuit structures.

The delay locked loop mainly has two realization modes, namely an analog mode and a digital mode, and the two modes have advantages respectively. The digital mode is relatively simple, but the locked phase jitter is relatively large, so that the method is suitable for circuits with lower frequency; the analog mode is relatively complex to implement, better in performance than the digital mode, and is suitable for use in circuits with higher frequencies.

In analog integrated circuit design, a simple RC circuit is the simplest delay circuit structure. Over time, the precise delay circuit structure has developed rapidly.

The delay units can be classified according to whether the delay time is variable or not, and can also be classified according to the types of devices, namely the delay units can be divided into active delay units and passive delay units. The active delay unit generally adopts devices such as an MOS field effect transistor or a bipolar transistor, and the passive delay unit is formed by passive devices such as a passive inductor, a capacitor and a resistor. Transmission line and LC delay circuit are general passive delay unit, compare in active delay unit, passive device does not need external power just can normally work, but passive device is general bulky, is unfavorable for the integrated miniaturization of chip.

The active delay unit is a delay circuit formed by active devices such as a MOS field effect transistor or a bipolar transistor. A relatively common differential delay cell is shown in FIG. 1, which illustrates1 shows a schematic representation of the structure of a differential delay unit, differential signal V, of the type presented_in、V_ipThe drains of transistors M1 and M2 output respective V from the gate inputs of transistors M1 and M2, respectively_op、V_onThe load resistors R1 and R2 are connected between the power supply VDD and the drains of the transistors M1 and M2, respectively, to perform a voltage division function. The bias current provided by the current source Iss1 in the differential structure is constant, and is used for providing a stable direct current operating point for the whole circuit. The disadvantage is that the bandwidth is small and it cannot be applied to high frequency circuits. On the other hand, the delay time of the existing delay unit is fixed, and the delay effect is poor.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model provides a voltage-controlled delay circuit, delay time is adjustable, can produce under the circumstances that broadband and delay time are stable guaranteeing the circuit, the effectual chip area that has reduced, the cost is reduced.

According to the utility model provides a voltage-controlled delay circuit, receive first difference input signal and second difference input signal, and to first difference input signal with export first difference output signal and second difference output signal after the second difference input signal time delay; the voltage-controlled delay circuit comprises at least one delay module, and the at least one delay module adjusts output delay time of the first differential input signal and the second differential input signal according to the control signal and outputs a first differential output signal and a second differential output signal.

Preferably, the delay module includes: a bias current generating unit providing a bias current; the common source amplifier unit is connected with the bias current generation unit and delays the first differential input signal and the second differential input signal according to the bias current; the active inductance unit is connected with the common-source amplifier unit, receives the control signal, and adjusts output phases of the first differential output intermediate signal and the second differential output intermediate signal according to the control signal, wherein the first differential input intermediate signal and the first differential input intermediate signal received by the first-stage delay module are respectively a first differential input signal and a second differential input signal; the first differential output intermediate signal and the second differential output intermediate signal output by the last stage of delay module are the first differential output signal and the second differential output signal respectively.

Preferably, the bias current generating unit includes: and one end of the first current source is connected with the common source amplifier unit, and the other end of the first current source is connected with the grounding end to provide bias current.

Preferably, the common source amplifier unit includes: a first transistor, a gate of which receives the first differential input intermediate signal, and a source of which is connected to a ground terminal through the first current source; and a gate of the second transistor receives the second differential input intermediate signal, and a source of the second transistor is connected with a ground terminal through the first current source, wherein the first differential input intermediate signal and the second differential input intermediate signal are output signals of a previous stage of delay module.

Preferably, the active inductance unit includes: a third transistor having a drain connected to a power source terminal, a source connected to the drain of the first transistor, and a connection point of the third transistor and the first transistor outputting a second differential output intermediate signal; a fourth transistor having a drain connected to the power supply terminal, a source connected to the drain of the second transistor, and a connection point between the fourth transistor and the second transistor outputting a first differential output intermediate signal; a fifth transistor having a source connected to the power source terminal, a drain connected to the gate of the third transistor, and a gate receiving the control signal; and a sixth transistor, a source of which is connected to the power supply terminal and a drain of which is connected to a gate of the fourth transistor, wherein the gate of the sixth transistor receives the control signal, and the first differential output intermediate signal and the second differential output intermediate signal are input signals of a subsequent stage of the delay module.

Preferably, the first to fourth transistors have the same channel type, and the fifth and sixth transistors have the same channel type, wherein the channel types of the first and fifth transistors are opposite to each other.

Preferably, the voltage-controlled delay circuit is used in a magnetometer to generate a measurement delay.

The utility model has the advantages that: the utility model discloses a voltage-controlled delay circuit, the delay time of single-stage delay module is adjustable in the voltage-controlled delay circuit, can realize voltage-controlled delay circuit to the control of the phase delay volume of the differential signal of input, reaches the purpose of low time delay, reinforcing time delay effect.

The delay module is built by adopting an active device, if the function of an active inductor is realized by adopting an MOS device, a passive inductor is not needed, so that the aims of widening the frequency bandwidth and reducing the chip area are fulfilled.

The circuit has good delay performance, a larger frequency bandwidth is obtained, the delay value of the single-stage delay module is lower, and the characteristics of wide frequency band, low delay and adjustable delay can be better realized.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a differential delay unit;

fig. 2 is a block diagram illustrating a delay locked loop according to an embodiment of the present invention;

fig. 3 shows a block diagram of a delay module according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a delay module according to an embodiment of the present invention;

FIG. 5 shows an equivalent circuit diagram of the active inductive element of FIG. 4 and its small signal;

FIG. 6 shows an equivalent circuit diagram of the delay block of FIG. 4;

fig. 7 shows a block diagram of a phase discriminator provided by the present invention;

fig. 8 shows a circuit structure diagram of a phase discriminator provided by the present invention;

fig. 9 shows a circuit structure diagram of a filter circuit according to an embodiment of the present invention.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The present invention will be described in detail below with reference to the accompanying drawings.

Fig. 2 shows a block diagram of an implementation of a delay locked loop according to an embodiment of the present invention.

As shown in fig. 2, in the present embodiment, the delay locked loop includes a voltage controlled delay circuit 110, a phase detector 120, and a filter circuit 130.

Wherein the input terminal of the voltage-controlled delay circuit 110 receives the first differential input signal V_inAnd a second differential input signal V_ipAnd the output end outputs a pair of first differential input signals V_inAnd a second differential input signal V_ipDelayed first differential output signal V_onAnd a second differential output signal V_op。

In this embodiment, the voltage-controlled delay circuit 110 includes at least one delay module for delaying the differential input signal step by step, and each delay module generates a broadband adjustable delay for the differential input signal, so that the flexible adjustment of the delay time of each delay module can be realized, and further the control of the voltage-controlled delay circuit 110 on the phase delay amount of the differential input signal is realized, and the delay effect is enhanced.

Further, each delay module receives a first differential input signal V_inAnd a second differential input signal V_ipOr receiving the first differential input intermediate signal-x and the second differential input intermediate signal + x, outputting the first differential output intermediate signal-y and the second differential output intermediate signal + y, or outputting the first differential output signal V_onAnd a second differential output signal V_op。

It can be understood that each stage of the delay modules in the voltage-controlled delay circuit 110 are arranged in series, the output of the first stage of the delay module is coupled to the input of the second stage of the delay module, i.e. the differential input signal of the voltage-controlled delay circuit is used as the differential input signal of the first stage of the delay module, the differential output signal of the first stage of the delay module is used as the differential input signal of the second stage of the delay module, and so on, the output of the penultimate stage of the delay module is coupled to the input of the last stage of the delay module, and the differential output signal of the last stage of the delay module is used as the differential output signal of the voltage-controlled delay circuit, thereby implementing the first differential input signal_inAnd a second differential input signal V_ipThe phase delay of (3). That is, the first stage delay module receives the first differential input signal V_inAnd a second differential input signal V_ipThe delay module of the last stage outputs a first differential output signal V_onAnd a second differential output signal V_opThe input signals (the first differential input intermediate signal-x and the second differential input intermediate signal + x) of each stage of delay module between the second stage of delay module and the last stage of delay module are the output signals (the first differential output intermediate signal-y and the second differential output intermediate signal + y) of the last stage of delay module.

The phase detector 120 is connected to the voltage-controlled delay circuit 110 and receives a first differential input signal V_inA second differential input signal V_ipA first differential output signal V_onAnd a second differential output signal V_opDetecting and outputting a first differential input signal V_inAnd a first differential output signal V_onA first phase difference therebetweenValue signal V_{on_PD}And a second differential input signal V_ipAnd a second differential output signal V_opWith a second phase difference signal V between_{op_PD}。

In this embodiment, the phase detector 120 adopts a multiplier to implement the phase detection function, and the first phase difference signal V output from the phase detector 120_{on_PD}And a second phase difference signal V_{op_PD}The voltage regulator includes a low-frequency DC voltage component and a high-frequency DC voltage component.

The filter circuit 130 is respectively connected to the phase detector 120 and the voltage-controlled delay circuit 110, and receives the first phase difference signal V_{on_PD}And a second phase difference signal V_{op_PD}Based on the first phase difference signal V_{on_PD}And a second phase difference signal V_{op_PD}Generating a control signal V_ctrlAnd output to the voltage controlled delay circuit 110. The control signal V_ctrlAnd finally fed back to the voltage-controlled delay circuit 110 to adjust the output delay time of the voltage-controlled delay circuit 110.

In this embodiment, the filter circuit 130 employs a simple differential amplifier to filter the first phase difference signal V_{on_PD}And a second phase difference signal V_{op_PD}The high-frequency signal included in the delay locked loop is used for obtaining direct current bias voltage, and the direct current bias voltage is amplified and then output, so that the rapid locking of the delay locked loop is realized.

Further, the higher the low frequency gain of the filter circuit 130, the shorter the lock time of the delay locked loop.

As described above, the delay locked loop disclosed in this embodiment forms a negative feedback system, and as the phase difference between the differential output signal and the differential input signal is continuously decreased until the phase difference is decreased to, for example, 90 degrees, at this time, the voltage output by the filter circuit 130 is in a stable state, that is, the delay locked loop reaches a locked state. Differential output signal (V) output by the locked delay-locked loop_on、V_op) With respect to differential input signals (V)_in、V_ip) Is delayed by an amount equal to 1/4 clock cycles.

It is understood that the present embodiment may also control the delay amount of the differential signal during locking to be, for example, 0 degree and 180 degrees by adjusting the delay time of a single delay module.

In this embodiment, the voltage-controlled delay circuit 110 includes at least one delay module. For convenience of understanding, the voltage-controlled delay circuit 110 is illustrated by taking a voltage-controlled delay circuit with one delay module as an example. Fig. 3 shows a block diagram of a delay module provided in an embodiment of the present invention, fig. 4 shows a circuit structure diagram of a delay module provided in an embodiment of the present invention, fig. 5 shows an equivalent circuit diagram of an active inductance unit and its small signal in fig. 4, and fig. 6 shows an equivalent circuit diagram of a delay module in fig. 4.

In this embodiment, as shown in fig. 3, each delay module includes a first bias current generating unit 1101, a common source amplifier unit 1102 and an active inductance unit 1103,

as shown in fig. 4, wherein the first bias current generating unit 1101 is configured to provide a first bias current, it includes a second current source Iss 2.

The common-source amplifier unit 1102 is connected to the first bias current generating unit 1101, receives the first differential input intermediate signal-x and the second differential input intermediate signal + x, and outputs the first differential output intermediate signal-y and the second differential output intermediate signal + y according to the first bias current, the first differential input intermediate signal-x and the second differential input intermediate signal + x, for example, including a third transistor M3 and a fourth transistor M4.

The active inductor unit 1103 is connected to the common source amplifier unit 1102 and receives the control signal V_ctrlAnd according to the control signal V_ctrlThe output phases of the first differential output intermediate signal-y and the second differential output intermediate signal + y are adjusted, and include, for example, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

Specifically, the fifth transistor M5, the third transistor M3 and the second current source Iss2 are sequentially connected in series between the power source terminal VDD and the ground terminal, and the source and the drain of the seventh transistor M7 are respectively connected to the drain (i.e., the power source terminal VDD) and the gate of the fifth transistor M5. The gate of the seventh transistor M7 receives the control signal V_ctrlA fifth transistor M5 and a third transistor MThe connection node of 3 outputs the second differential output intermediate signal + y and the gate of the third transistor M3 receives the first differential input intermediate signal-x.

In the same principle, the sixth transistor M6, the fourth transistor M4 and the second current source Iss2 are sequentially connected in series between the power source terminal VDD and the ground terminal, and the source and the drain of the eighth transistor M8 are respectively connected to the drain (i.e., the power source terminal VDD) and the gate of the sixth transistor M6. The gate of the eighth transistor M8 receives the control signal V_ctrlThe connection node of the sixth transistor M6 and the fourth transistor M4 outputs the first differential output intermediate signal-y, and the gate of the fourth transistor M4 receives the second differential input intermediate signal + x. The second current source Iss2 provides bias current for the delay module and controls the signal V_ctrlBy adjusting the gate voltages of the seventh transistor M7 and the eighth transistor M8, the equivalent resistances of the linear resistors of the seventh transistor M7 and the eighth transistor M8 are adjusted.

Further, the channel types of the seventh transistor M7 and the eighth transistor M8 are opposite to the channel types of the third to sixth transistors (M3 to M6).

It should be noted that the first differential input intermediate signal-x and the second differential input intermediate signal + x received by the first stage delay module are the first differential input signal V respectively_inAnd a second differential input signal V_ipThe first differential output intermediate signal-y and the second differential output intermediate signal + y output by the last stage of delay module are respectively the first differential output signal V_onAnd a second differential output signal V_opThe first differential input intermediate signal-x and the second differential input intermediate signal + x of the input of each stage of delay module between the second stage of delay module and the last stage of delay module are the first differential output intermediate signal-y and the second differential output intermediate signal + y of the output of the last stage of delay module, respectively.

Each delay module in the voltage-controlled delay circuit 110 is an active inductor parallel peaking delay module, and the circuit structure of the delay module is bilaterally symmetrical, so that the delay module can be split into bilaterally symmetrical two-part circuits for understanding. The voltage-controlled delay circuit of the embodiment adopts an MOS device to realize the function of an active inductor, does not need a passive inductor, can widen the bandwidth and reduce the chip area.

The peaking technology refers to a bandwidth expansion technology, the inductance peaking technology is a technology for expanding bandwidth by utilizing resonance of an inductor and a capacitor, and can be divided into an inductance series peaking technology and an inductance parallel peaking technology according to different inductance positions.

Only the left circuit is functionally analyzed, and accordingly, the working principle of the right circuit is the same as that of the left circuit, and will not be described again.

Referring to fig. 5, in the single delay module, the seventh transistor M7 has no current flowing through it, which is equivalent to a linear resistor R_sThe linear resistance R_sParasitic capacitance C with the fifth transistor M5_gsAnd the serial connection introduces a zero point, thereby realizing bandwidth expansion. Further, the linear resistor R_sIs adjustable by varying the control signal V at the gate of the seventh transistor M7_ctrlThe voltage value of the resistor can further realize the aim of aligning the linear resistor R_sThe resistance value is adjusted, so that the position of a zero point is changed to change the delay time of each delay module in the voltage-controlled delay circuit, and the aims of changing the group delay time of the voltage-controlled delay circuit and realizing adjustable delay are fulfilled. It is understood that G, D, S refers to the gate, the drain and the source of the fifth transistor M5, respectively.

Further, from the small-signal equivalent circuit diagram shown in fig. 5, the following formula can be derived:

combining equation (1) and equation (2) yields:

where s represents the s domain, and s ═ σ + j ω (σ, ω are real numbers), R_sIs the equivalent resistance, Z, of the seventh transistor M7 and the eighth transistor M8 in FIG. 4_XIs an equivalent active inductor with an equivalent inductance value of about

C_gsIs a parasitic capacitance between the gate and the source of the fifth transistor M5, V_gsIs the gate-source voltage, g, of the fifth transistor M5_mV_gsIs the gate-source current, g, of the fifth transistor M5_mbV_bsIs the current between the source and the substrate of the fifth transistor M5, g_mbIs the source-liner transconductance, V_bsIs the source-substrate potential difference, R_dsIs the equivalent resistance between the drain and the source of the fifth transistor M5. V_xIs the source voltage, I, of the fifth transistor M5_xIs the input current at the source of the fifth transistor M5.

Further, an active inductor Z is arranged_xSubstituting fig. 3, an equivalent circuit diagram can be obtained as shown in fig. 6, in which the equivalent circuit diagram is composed of a first equivalent inductor Z_x1Instead of the fifth transistor M5 and the seventh transistor M7 in fig. 3, a second equivalent inductor Z is provided_x2Instead of the sixth transistor M6 and the eighth transistor M8 in fig. 4. The working principle can refer to fig. 4, and will not be described herein.

In this embodiment, the voltage-controlled delay circuit 110 includes at least one delay module. For convenience of understanding, the delay principle of the voltage-controlled delay circuit 110 is described herein by taking a voltage-controlled delay circuit with one delay module as an example. Furthermore, as can be seen from the transmission function, the delay module shown in fig. 4 or fig. 6 has 1 zero point (denoted as z)₀) And two poles (denoted p, respectively)₁And p₂) At this time, the group delay time of the voltage-controlled delay circuit is calculated by the following formula:

where ω is the operating frequency of the differential input signal due to the operating frequency ω<<z₀，ω<<p₁，ω<<p₂So the group delay of equation (4) is nearly constant, i.e.:

from equation (5), when ω is<<z₀Group delay and zero z of time delay module₀In connection with this, by changing z₀The group delay can be adjusted, i.e. by adjusting the control signal V_ctrlTo adjust the equivalent resistance R_sAnd further realizing the adjustment of the group delay time of the delay modules.

To sum up, the utility model provides a delay module with parallelly connected peaking structure has good time delay performance, can obtain bigger frequency bandwidth, and the delay value of single-stage delay module is lower, realization broadband that can be better, low time delay and time delay adjustable characteristic.

Meanwhile, each delay module does not adopt a passive device, but realizes the effect of the corresponding passive device through the equivalent of the active device, thereby effectively reducing the area of the chip and lowering the cost.

Fig. 7 shows a block diagram of the phase detector provided in the embodiment of the present invention, and fig. 8 shows a circuit structure diagram of the phase detector provided in the embodiment of the present invention.

In this embodiment, as shown in fig. 7 and 8, the bias current generating unit 1205 includes a second bias current generating unit 1201, a first source follower unit 1201, a second source follower unit 1202, a third source follower unit 1203, a fourth source follower unit 1204, and a resistor dividing unit 1206. Wherein the second bias current generating unit 1205 provides the second bias current. The first to fourth kinds of source follower units are connected to the second bias current generating unit 1205, receive the second bias current, and receive the first differential input signal V_inA second differential input signal V_ipA first differential output signal V_onAnd a second differential output signal V_opTo do so byThe first current signal Io1 and the second current signal Io2 are output to the resistor voltage divider 1206. The resistance voltage dividing unit 1206 is respectively connected to the first type source follower unit 1201 and the fourth type source follower unit 1204, and outputs a first phase difference signal V according to the first current signal Io1 and the second current signal Io2_{on_PD}And a second phase difference signal V_{op_PD}。

The second bias current generating unit 1205 is used to provide a second bias current, and includes a third, a fourth, a fifth and a sixth current source (Iss3-Iss 6). In this embodiment, a plurality of current sources are adopted to provide the second bias current for each class source follower unit respectively (wherein each current source provides the bias current for the corresponding class source follower unit respectively, and the bias currents output by the plurality of current sources are the same), so that the cooperative work of a plurality of transistors in the phase discriminator can be better realized, the requirement on the output current of the current sources can be reduced, and the current stability is ensured. It is understood that the second bias current generating unit 1205 may be provided by only one current source.

The first type of source follower unit 1201 includes ninth, tenth and eleventh transistors (M9-M11), the second type of source follower unit 1202 includes twelfth, thirteenth and fourteenth transistors (M12-M14), the third type of source follower unit 1203 includes fifteenth, sixteenth and seventeenth transistors (M15-M17), and the fourth type of source follower unit 1204 includes eighteenth, nineteenth and twentieth transistors (M18-M20). The first to fourth types of source follower units (1201-1204) are respectively connected to the second bias current generating unit 1205 to receive the second bias current.

The resistance voltage divider 1206 is respectively connected to the first type source follower 1201 to the fourth type source follower 1204, and includes a third resistor R3 and a fourth resistor R4.

Specifically, the sources of the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are all connected to the ground terminal through the third current source Iss3, the sources of the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all connected to the ground terminal through the fourth current source Iss4, and the sources of the fifteenth transistor M15, the sixteenth transistor M16, and the seventeenth transistor M17 are all connected to the ground terminal through the fourth current source Iss4The sources are all connected to the ground terminal through a fifth current source Iss5, and the sources of the eighteenth transistor M18, the nineteenth transistor M19 and the twentieth transistor M20 are all connected to the ground terminal through a sixth current source Iss 6. The drains of the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the nineteenth transistor M19, and the twentieth transistor M20 are all directly connected to the power source terminal VDD. Drains of the eleventh transistor M11 and the twelfth transistor M12 are connected to a power source terminal VDD through a third resistor R3, and a second phase difference value signal V is output between a common connection point of the third resistor R3 and the eleventh transistor M11_{op_PD}. Drains of the seventeenth transistor M17 and the eighteenth transistor M18 are connected to a power source terminal VDD through a fourth resistor R4, and a first phase difference signal V is output between a common connection point of the fourth resistor R4 and the seventeenth transistor M17_{on_PD}. And the gate of the ninth transistor M9 receives the second differential input signal V_ipThe gate of the tenth transistor M10 receives the second differential output signal V_opThe gates of the eleventh transistor M11 and the twelfth transistor M12 are connected to the power supply terminal VDD, and the gate of the thirteenth transistor M13 receives the first differential output signal V_onThe gates of the fourteenth transistor M14 and the fifteenth transistor M15 receive the first differential input signal V_inThe gate of the sixteenth transistor M16 receives the second differential output signal V_opThe gates of the seventeenth transistor M17 and the eighteenth transistor M18 are connected to the power supply terminal VDD, twentieth; the gate of the seven transistor M27 receives the first differential output signal V_onThe gate of the twentieth transistor M20 receives the second differential input signal V_ip。

In this embodiment, the phase detector has a fully symmetric structure, and therefore, may also be referred to as an xor gate phase detector, and converts current to voltage in a form of resistor voltage division. The third current source Iss3 through the sixth current source Iss6 are all used to provide bias current. The bias current provided by each current source is equally divided into two paths, and taking three consecutive transistors as an example, the bias current provided by the third current source Iss3 is provided to the source follower-like structure formed by the ninth transistor M9 and the tenth transistor M10 in one path, and is provided to the output voltage sampling module circuit formed by the eleventh transistor M11 and the third resistor R3 in the other path. Correspondingly, every three consecutive transistors in the subsequent plurality of transistors respectively form a similar source follower and an output voltage sampling module, and it should be understood that reference may be made to the ninth transistor M9 through the eleventh transistor M11, which are not described herein again.

The ninth transistor M9 to the twentieth transistor M20 are all operated in the saturation region.

The phase detector in the embodiment has a symmetrical structure, so that the output impedance of the phase detector circuit can be reduced, and the thermal breakdown resistance of the phase detector circuit can be enhanced. Meanwhile, the output accuracy of the phase difference of the differential input signals can be improved, the gain is improved, and meanwhile, the anti-interference capability of the phase discriminator circuit is enhanced.

Fig. 9 shows a circuit structure diagram of a filter circuit according to an embodiment of the present invention.

As shown in fig. 9, in the present embodiment, the filter circuit 130 includes twenty-first to twenty-fourth transistors M21 to M24 and a load capacitor C_p. The twenty-third transistor M23, the twenty-first transistor M21 and the seventh current source Iss7 are sequentially connected in series between the power source terminal VDD and the ground terminal, and the twenty-fourth transistor M24, the twenty-second transistor M22 and the seventh current source Iss7 are sequentially connected in series between the power source terminal VDD and the ground terminal. The gate of the twenty-third transistor M23 is connected to the gate of the twenty-fourth transistor M24, and to the drain of the twenty-third transistor M23, constituting a current mirror. The gate of the twenty-first transistor M21 receives the first phase difference signal V_{on_PD}. The gate of the twentieth transistor M22 receives the second phase difference value signal V_{op_PD}. The connection node of the twenty-fourth transistor M24 and the twenty-second transistor M22 passes through the load capacitor C_pIs connected with the grounding terminal to output the control signal V_ctrl。

Further, the channel types of the twenty-third transistor M23 and the twenty-fourth transistor M24 are opposite to the channel types of the twenty-first transistor M21 and the twenty-second transistor M22.

The filter circuit 130 disclosed in this embodiment is a simple differential amplifier structure in which the first phase difference is inputtedValue signal V_{on_PD}And a second phase difference signal V_{op_PD}The seventh current source Iss7 provides bias current for the filter circuit 130, and the output current I outputted from the connection node of the twenty-fourth transistor M24 and the twenty-second transistor M22 is the two output signals of the phase detector_outBy means of a load capacitor C_pCharge and discharge of (2) realize control signal V_ctrlTo output of (c).

The filter circuit 130 may filter the first phase difference signal V_{on_PD}And a second phase difference signal V_{op_PD}And the direct current bias voltage is amplified simultaneously by the medium-high frequency signal so as to realize the quick locking of the delay locking loop.

Further, the higher the low frequency gain of the filter circuit 130, the shorter the lock time of the loop.

The utility model discloses a voltage-controlled delay circuit can be applied to like in the magnetometer to produce and measure the time delay.

To sum up, the utility model discloses an among the voltage-controlled delay circuit, the delay time of single-stage delay module is adjustable, can realize voltage-controlled delay circuit to the control of the phase delay volume of the differential signal of input, reaches the purpose of low time delay, reinforcing time delay effect.

The delay module is built by adopting an active device, if the function of an active inductor is realized by adopting an MOS device, a passive inductor is not needed, so that the aims of widening the frequency bandwidth and reducing the chip area are fulfilled.

The circuit has good delay performance, a larger frequency bandwidth is obtained, the delay value of the single-stage delay module is lower, and the characteristics of wide frequency band, low delay and adjustable delay can be better realized.

In this specification, unless otherwise specified, all transistors involved are transistors of the same channel type.

It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.

Claims (7)

1. A voltage-controlled delay circuit receives a first differential input signal and a second differential input signal, delays the first differential input signal and the second differential input signal and outputs a first differential output signal and a second differential output signal;

the voltage-controlled delay circuit comprises at least one delay module, and the at least one delay module adjusts output delay time of the first differential input signal and the second differential input signal according to a control signal and outputs a first differential output signal and a second differential output signal.

2. The voltage controlled delay circuit of claim 1, wherein the delay module comprises:

a bias current generating unit providing a bias current;

the common source amplifier unit is connected with the bias current generating unit and delays the first differential input intermediate signal and the second differential input intermediate signal according to the bias current;

an active inductor unit connected with the common-source amplifier unit, receiving the control signal, and adjusting output phases of the first differential output intermediate signal and the second differential output intermediate signal according to the control signal,

the first differential input intermediate signal and the first differential input intermediate signal received by the first-stage delay module are the first differential input signal and the second differential input signal respectively;

the first differential output intermediate signal and the second differential output intermediate signal output by the last stage of delay module are the first differential output signal and the second differential output signal respectively.

3. The voltage-controlled delay circuit of claim 2, wherein the bias current generating unit comprises: and one end of the first current source is connected with the common source amplifier unit, and the other end of the first current source is connected with the grounding end to provide bias current.

4. The voltage-controlled delay circuit of claim 3, wherein the common source amplifier unit comprises:

a first transistor, a gate of which receives the first differential input intermediate signal, and a source of which is connected to a ground terminal through the first current source;

a second transistor having a gate receiving the second differential input intermediate signal and a source connected to a ground terminal through the first current source,

the first differential input intermediate signal and the second differential input intermediate signal are output signals of a previous stage delay module.

5. The voltage-controlled delay circuit of claim 4, wherein the active inductance unit comprises:

a third transistor having a drain connected to a power source terminal, a source connected to the drain of the first transistor, and a connection point of the third transistor and the first transistor outputting a second differential output intermediate signal;

a fourth transistor having a drain connected to the power supply terminal, a source connected to the drain of the second transistor, and a connection point between the fourth transistor and the second transistor outputting a first differential output intermediate signal;

a fifth transistor having a source connected to the power source terminal, a drain connected to the gate of the third transistor, and a gate receiving the control signal;

a sixth transistor having a source connected to the power supply terminal and a drain connected to the gate of the fourth transistor, the gate of the sixth transistor receiving the control signal,

the first differential output intermediate signal and the second differential output intermediate signal are input signals of a next-stage delay module.

6. The voltage-controlled delay circuit according to claim 5, wherein channel types of the first to fourth transistors are the same, channel types of the fifth and sixth transistors are the same,

wherein channel types of the first transistor and the fifth transistor are opposite.

7. The voltage-controlled delay circuit of claim 1, wherein the voltage-controlled delay circuit is used in a magnetometer to generate a measurement delay.

Images