DE1413960B2 - DIGITAL BINARY CONTROL PROTECTED AGAINST INTERNAL FAULTS - Google Patents

Description

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The invention relates to an against internal elements (input element, output element) m: error-protected digital-binary control with at least one feedback of the output element nac least one logic element with a semi-type of self-holding on the input element un; Conductor arrangement in which the semiconductor arrangement is acted upon by feeding the clock signal as a storage signal au an alternating voltage or with a pulse 5 the input element and as a continuous signal to eini-shaped voltage, such that the input of the output element, the value L of the digital-binary control signal As in the above-mentioned patent application, au pulse train is assigned and the logic, which is hereby referred to, is also led from an element permeable to this control signal, the memory can be erased in the coupling element connected downstream to which either an io one on the input a clear signal switches or: another logic element or an actuator is connected, the clock signal for the output element is interrupted, according to patent 1125 069 for use in the press control described in this application and in the case of the look-up application of the memory as a functional safeguard a memory element is provided, the element for a press control is only deleted before at least one initiator when booting the first possibility of deletion use of the press is deleted and that makes at least two.

series-connected, direct current ent- The invention is based on the object that

coupled, logical elements (input element, press control described above so that

Output element), with a feedback form that the deletion of the memory element with

the output element takes place in the manner of a self-holding 20 of increased security.

on the input element and feed of the clock. This task is achieved according to the invention

signals as a memory signal to the input element triggers that the memory element is triggered by the output

as well as a permanent signal on an input of the initiator's output signal when the press starts up

gang element. by feeding this signal to the input

The main patent is based on the task of showing a new way of clearing a digital signal for the output element by interrupting the clock. binary control, which consists of at least one logical If, for example, an interruption occurs at the clear input of the storage element with a semiconductor device, an interruption occurs and an interruption can be made to protect against internal errors. The solution in this regard can no longer be erased, this task succeeds in that the semiconductor arrangement 30 so still remains the possibility of erasure with an alternating voltage or with by interrupting the clock signal. The double of a pulse-shaped voltage is applied, deletion on two different elements of the such that the value L of the digital-binary control memory thus offers a high level of security with respect to signals a pulse train is assigned and that of the look-up protection, especially the memory for logic element a for this control signal through a defect is never connected downstream from the deleted to the reliable coupling element, can jump to the unstored state, since no further logic element or a control clock signal is then transmitted, element is connected. To further increase security one will

The control according to the main patent is preferably two initiators for the as usual achieves that the functional elements that provide logical 40 startup of the press, their outputs via Elements that no longer emit an output clock signal to the actuator of the press control directly if a defect occurs in the control. Through the influencing AND element are linked. the Coupling elements ensure that the memory is erased after a logical process Elements in terms of DC voltage separated teren feature of the invention so made that both are. This prevents the output voltage signals generated by DC when the press is running, those of the previous signals from both the input element and one Element are released due to a defect, interrupt circuit for the clock signal added-incorrect circuits can arise. leads are so that the memory element with a

It is stated in the main patent that the very high level of security when the press is started up

Control in particular for controlling a press 50 is deleted,

or similar machines. Further features and advantages of the invention

The circuit arrangement for a dormant press control, which is the subject matter of

control is known per se. It contains under an- subclaims, result from the

whose to look-up a memory element, description of the one shown in the drawing

that of at least one initiator when booting 55 exemplary embodiments. It shows

the press is deleted. This deletion is to be done with F i g. 1 an embodiment of the complete

a very high level of safety, since otherwise the circuit arrangement of a stationary press control

the press continue to run in an undesirable sense tion with an embodiment of the invention

can without the actuating elements for the appropriate deletion of the memory element for re-

Press released during the stroke 60 impact protection,

have to. In the patent application P 14 24 427.0 Fi g. 2 the exemplary structure of this storage

the structure of such a memory element is connected to a special OR or AND element

give or use in a press element.

Control with the control principle according to FIG. 1 shows a system consisting of dormant logical elements

Main patent described. According to the versions 65 th built press control in the usual

In this patent application there is the memory representation type. According to the control principle according to

element from at least two consecutive main patents, the logical elements are the same-

decoupled, DC-decoupled logical current-related and are connected to an alternating

voltage or a pulse-shaped voltage - referred to below as a clock signal - as a digital one binary control signal applied. In the drawing, the coupling links are not shown, they are to think arranged within the functional elements. The symbolic representation of the functional elements is therefore provided with a point.

The memory element S 1 provided for look-up protection, the AND element U 5, the OR gate V 2 and an initiator / 1 or / 2 are the elements of the functionally necessary logic for a press control, that is, the relevant circuit already fulfills the known ones functional conditions for controlling a press. The basic circuit also includes the two keys T1, T2, which when ^{pressed 1} S, the press should run downwards, or the actuator, a solenoid valve, to influence the stroke movement. The solenoid valve is expediently actuated via an amplifier A 1, as shown. The other functional elements serve to increase security. The AND element £ 74 z. B. ensures in connection with the OR element V 2 (memory circuit) that the press does not run over the bottom dead center with momentum if at least one of the keys T1, T2 is released during the downward movement.

The design of the memory element Sl is the subject of patent application P 14 24 427.0-32. In this regard, reference is made to this patent application. The memory element then consists of at least two series-connected, DC-decoupled, logic elements (input element, output element) with feedback of the output element in the manner of a self-holding to the input element and feeding of the clock signal as a memory signal to the input element and as a permanent signal to an input of the output element. The memory element is erased by initiator signals when the press starts up. This deletion takes place in that the initiator signals are switched to the input of the memory element as delete signals and at the same time interrupt the clock signal for the output element. For safety reasons, it is useful, as shown, to provide two initiators 11, 12 for deleting or starting up the press, both of which emit a signal in perfect condition, in the range from 180 to 360 ° (bottom dead center - starting point), and thus the Fulfill the AND condition for the AND element t / 3, so that in this area the actuator or the amplifier ^ receives its control signal from the initiators via the OR element V 2. Due to the AND operation i / 3, the press can only run up if both initiators have an output signal. To erase the memory by means of the initiator signals on the first path, according to a feature of the invention, both initiator outputs are connected to clear inputs of the memory element, so that the memory element is already cleared when only one initiator has an output signal. In the embodiment of FIG. 1 it is assumed that both initiators emit a direct voltage signal. However, since the press control according to the invention works with an AC voltage signal as the control signal, the initiator signals to act on the AND element U 3 must be "chopped up", which for safety reasons is best done with AND elements Vl, U 2 , the structure of which will be explained later.

The initiator DC voltage signal is applied to the input α of the AND elements U1, U 2 , and the clock signal is applied to the input b. If the initiator signal and the clock signal are present, then a clock signal also appears at the output of the AND elements Ul, U 2 , which is applied to the inputs a, b of the AND element t / 3. If you have initiators with a clock signal as the output signal, the AND elements Ul, U 2 can be dispensed with. However, a rectifier circuit must then be provided to influence the erase inputs of the storage element.

To interrupt the clock signal by means of the initiator signals, ie to delete the memory on the second path, rectifier circuits G1, G 2 are provided, which each produce a DC voltage from the clock signal of the AND elements Ul, U 2 , the inputs a, c of a Apply the OR element V 1, the third input b of which is influenced by the clock signal. Thereafter, the clock signal for the memory element 51 can only be transmitted by the OR element Vl if there is no DC voltage either at the input α or at the input b , ie neither the initiator / 1 nor the initiator / 2 has an output signal. The clock signal for the memory element 51 is thus already interrupted by an initiator signal and the memory is thus erased.

The double deletion in each case offers a very high level of security that the memory will run up when it starts up the press is deleted.

This security is also achieved in particular by a structure of the memory element according to FIG. 2 guaranteed. In addition, this memory is made up of two logical elements, which are also can be used to build up the other logical elements of the control system and the on Due to their fault-proof circuit, guarantee a high degree of accident safety of the press control. The two logical elements of FIG. 2 are thus basic elements for functional elements in a controller according to the main patent.

As in Fig. 2, it is an OR element (part framed by dashed lines), which is followed by an AND element. The OR element has z. B. four inputs c, d, e, f, the AND element two inputs a, b. The OR element represents the input element, the AND element represents the output element of the storage element. The output A of the AND element is fed back to the input c of the OR element in the manner of a latch. The galvanic separation of the elements takes place through the capacitors C 4, Cl corresponding to the capacitors 7, 14 according to the patent application P 14 24 427.0-32. It is useful to include the coupling links in the elements.

The OR element contains a transistor T ₅ 1 as a switching element which is biased by the resistor voltage divider circuit RQ, Rl so that it conducts in the idle state and is blocked by positive input signals. The diodes DS to D 11 of the upstream passive diode gate are therefore polarized reversely as usual. The diodes Dl and D 2 are used in a known manner to produce a desired direct current component behind the coupling capacitors C1, C2. You can

not applicable if inductive transformers are used as coupling links.

The error-protected downstream AND element also contains a transistor T _S 2 as a switching element with a downstream transistor stage T ₅ 3,. the resistor voltage divider circuits R6, R7 or R 10, R 12 are dimensioned so that the transistors conduct in the idle state. Coupling elements C 4, C 5, C6 are provided at the two inputs and at the output of the transistor T _S 2 , each of which is followed by a diode Z) 5, D 6, Dl to raise the potential. A clock signal is fed in at the input & which controls the base of the transistor T _S 2 , while the collector voltage for the transistor T _s 2 is obtained from the clock signal of the input α. A clock signal only appears at output A if input α and input b have an input signal.

The memory operates as follows: If the input d tact given, appears at the output of the OR gate or at the input A of the AND element clock signal (in F i g 1 via the closed contacts of the Tl keys, T 2.). A continuous clock signal is present at the input b of the AND element (in FIG. 1 via the OR gate Vl). Output A thus also has a clock signal that is fed back via input c. The memory signal at input d can then be removed, but output A still has a clock signal, ie the memory is in its memory position. The removal of the clock signal at output A, that is, the deletion of the memory can be done once by switching a DC voltage signal to input e or / which keeps transistor T _s l blocked and thus prevents the transmission of the clock signal (in FIG. 1 by the DC voltage signals of the initiators), on the other hand by the fact that the clock signal for the input b of the AND element is interrupted (in Fig. 1 by means of the OR element Vl, which is controlled at its input α or c or both by a DC voltage signal will).

Due to the error-proof structure of the individual elements of the memory according to FIG. 2, this memory is safe to a high degree, that is, if any component is defective, no clock signal will be output which would incorrectly apply to input b of AND element C / 5 (FIG. 1) and thus cause the downward movement when the keys are pressed the press could initiate.

The elements of the memory according to FIG. 2 can also be used, with particular advantage, to construct the other elements in the press control according to FIG. 1 occurring logical elements can be used. The combination of the memory erasure with the structure of the logic elements according to the arrangements according to FIG. 2 results in a press control with a very high level of accident safety and is therefore an essential element of the press control according to the invention. When using the OR element, it should be noted that a coupling element is provided at all inputs to which the clock signal is switched and, in the case of capacitors as coupling elements, a downstream diode is provided. When the AND elements U1, U 2 are implemented by AND elements according to FIG. 2, the capacitor C 4 or the rectifier circuit D 5, D 4, Cl can be omitted, since a direct voltage signal is available immediately stands. In this context it should be mentioned that a clock signal can also be switched to the OR inputs e, f as a cancel signal if coupling elements or a rectifier circuit are provided behind the inputs. In this case, in the circuit according to FIG. 1, the erase initiator signals to be switched to the erase inputs of such a memory element 51 could be picked up behind the AND gates U1, t / 2. This measure, as well as the measure to apply the inputs a, c of the OR element Vl not directly to the DC voltage signals of the initiators, but to a DC voltage that is obtained from the initiator signals converted by the AND elements Ul, U 2, important for the setting of the initiators. Due to the time constant of the coupling elements or the internal resistances of the initiators, an exact setting of the initiators relative to one another is not absolutely necessary. However, this fact also applies to the circuit according to FIG. 1 and 2 are taken into account, since here the delayed effect is caused by the coupling capacitor or the rectifier and filter circuit behind the input α.

Since a high frequency constancy does not appear to be absolutely necessary, a clock signal generator is sufficient z. B. a multivibrator or similar simple oscillator circuit.

The output stage A1 (FIG. 1) preferably contains inductive transformers as coupling elements and is in principle like the circuit arrangement according to FIG. 1 of the main patent.

The control according to FIG. 1 can of course also to control machines equivalent to the presses, e.g. B. of punching, ramming, stamping machines etc. can be applied.

Claims (8)

Patent claims: 1. Digital binary control protected against internal errors with at least one logic element with a semiconductor arrangement, in which the semiconductor arrangement is acted upon with an alternating voltage or with a pulse-shaped voltage, such that the value L of the digital-binary control signal is assigned a pulse sequence and the logic element is followed by a coupling element that is permeable to this control signal and to which either a further logic element or an actuator is connected, according to patent 1125 069 for use in a press control, in which a memory element is provided for look-up protection, which is triggered by at least one initiator when starting up the press is deleted and which consists of at least two series-connected, DC-decoupled, logic elements (input element, output element) with a feedback of the output element in the manner of a self-holding to the input element and feed of the clock signal as a memory signal to the input element and as a permanent signal to an input of the output element, characterized in that the memory element is activated by the output signal of the initiator when the press is started up and by feeding this signal to the Input element as well as by interrupting the clock signal for the output element can be deleted is. 2. Control according to claim 1 with two initiators, the outputs of which are linked via an AND element (logic element U 3) that indirectly influences the actuator of the press control, characterized in that both output signals pending when the press is started up, both the input element and an interrupt circuit are supplied for the clock signal. 3. Control according to claim 1 or 2 with initiators, which when actuated a DC voltage signal deliver, characterized in that an AND element is used to convert the DC voltage signal of an initiator into a clock signal (Conversion element t / l, t / 2) with two inputs and a transistor as a switching element is provided, on one of the input associated with the ao base the clock signal and on its other input, from whose input signal the collector voltage is obtained the initiator output signal is switched. 4. Control according to claim 3 with two initiators according to claim 2, characterized in that that the outputs of the conversion AND elements each with an input of the Linking AND element are connected. 5. Control according to claim 2 and 3 or 4, characterized in that from the output clock signal the conversion AND elements assigned to each initiator Rectifying and smoothing a DC voltage signal is available, each on a Input of an OR element (Kl) switched is, whose third input is a clock signal and whose output is connected to the clock signal input of the output element in the memory element is connected in such a way that when it occurs only one initiator signal from the OR element no longer transmit a clock signal and the memory is cleared. 6. Control according to claim 1 or one of the following, characterized in that the Input element of the memory element an OR element and the output element AND element with two inputs. 7. Control according to claim 6, characterized in that the OR element is one has conductive transistor in the idle state as a switching element, which has a passive diode gate is connected upstream and its inputs, to which the clock signal is given, capacitively coupled are. 8. Controller according to claim 6, characterized in that the AND element is an im Has retired conductive transistor as a switching element, the base of which via a coupling element is connected to an input for the clock signal and its collector voltage the input signal of the other input, d. H. from the output clock signal of the OR element, is won. 1 sheet of drawings WO 108