DE2230733B2 - Electronic digital clock - Google Patents

Description

The invention is an electronic digital watch according to the preamble of the main claim.

In DE-PS 22 13 460 is a time measuring device

ίο suggested that the twelve hours be displayed can. This time measuring device contains a clock pulse generator with a normal frequency pulse generator and a clock generator with a Frequency divider with a division ratio 1 / n and with a decryption device is connected. Clock pulses are applied to the output connections of the Clock pulse generator is always output when it receives a pulse from the standard pulse generator receives Four shift registers store the time count ment, with four half-adders adding up the time of the output signal of the shift register to a time signal. This timepiece still has a notable number of components and thus a notable number of connections, see above that integrated circuit techniques are not optimally attached.

The object of the invention is to be seen in particular in creating an electronic digital watch that is shown in the constructive training and in the circuit

Order is kept so simple that integrated Circuit techniques are preferably to be used,

where> the smallest possible number of components and few connecting lines are to be used.

The object is according to the invention after

Features of the main claim solved. Advantageous refinements of the invention are specified in the subclaims.

An essential feature of the electronic digital watch of this invention is that the Shift register is connected to an addition device in such a way that a closed circuit is obtained. The time information stored in the shift register, which represents several digits, is dur ^ h the in a predetermined smallest time unit to be counted closed loop. If there is any information at an input terminal of the addition device, which designates the smallest time unit, then the other input terminal receives an addition pulse in the the smallest time unit, which is an addition to the right, d. H. a position shift to the right, caused.

According to a particular feature of the invention, output signals are of a predetermined level of the shift register only to a common To lead decoding circuit, which is associated with a remarkable decrease in the required connecting lines.

Another feature of this invention is that the adder is in construction is kept simple and for each smallest time unit a number "1" is added to the time information that has already been transferred added up. If the addition leads to a carry over, the sum output is always zero. Of the The carry output becomes the time information at piner

M number of the then following higher order of magnitude added up. For this reason it does not matter if the carry output and the Unit pulse for adding the number I to the

Adding device are switched. Therefore there is also no addition device with three input terminals which is usually used in full addition. The addition device belonging to the digital clock consists of: an EXCLUSIVE-OR link with two input terminals for the implementation of the shift or the transfer as well as from a one-bit time delay scheme.

The invention is described below with reference to the embodiment shown in the drawing (the one in Exemplary embodiments shown in the drawing) explained in more detail

F i g. 1 is a block diagram for an electronic Digital clock according to this invention;

2 shows a circuit diagram for the block diagram according to

Fig. 3 Curves of the various impulses to explain the operation of the circuit shown with Figure 2;

F i g. 4 the Eiekirodenmusier of a number display device in the digital watch of this invention;

5 shows the display of time information by a plurality of digit display devices which are provided with electrodes according to FIG. 4 are provided.

As an exemplary embodiment, an electronic digital watch is described in which, for example, the Time information is given in six digits. In this case, the time information is made up of the three Groups hours, minutes and seconds together, each group having two digits each, making the smallest Unit of time is one second

From Fig. 1, a crystal oscillator 11 can be seen, to which an oscillating crystal 12 belongs. The sinusoidal output signals of the crystal oscillator 11 are subjected to frequency division in the frequency divider 13. The output signals resulting from the frequency division are fed to a displacement pulse generator 14 which generates the two pulses Φι and Φι which have different phase positions. These displacement pulses Φι and Φι are each generated in an interval of the time unit of a bit. An output of the shift pulse generator 14 is connected to a bit pulse generator 15, which is indicated by F i g. 3 reproduced four successive bit pulses B \, B ₂ , B * and Bg . These bit pulses have a binary meaning of 1, 2, 4 and 8 and are generated for the duration of one bit time unit.

After an output signal from the Bii pulse generator 15 has been switched on, a digit pulse generator 16 generates six consecutive digit pulses Di to Df, which are also labeled F i g. 3 are shown. Each digit pulse is generated in an interval that corresponds to the smallest unit of time, ie here in an interval of one second. The duration of each digit pulse corresponds to a digit time or Wb seconds.

If the time information is to be displayed at a rate of> / 100 seconds, then each digit pulse is chosen so that it is generated in an interval of '/ 100 seconds, what the corresponds to the smallest time unit in this case.

Now it is assumed that a digit time '/ 6 Seconds and the frequency divider 13 six cascaded flip-ΙΊορ circuits or monostable Multivibrators belong, for which reason the frequency divider coefficient is 64 In In this case, the oscillator frequency of the crystal oscillator U is chosen so that it has a frequency of 1.536 kHz corresponds to If you want time information consisting of eight digits, which is per '/ ioo second changed then the frequency of the crystal oscillator U can either be set to 25.6 kHz (which corresponds to a frequency divider coefficient of 8) or to a frequency of 204.8 kHz (which corresponds to a Frequency divider coefficients of 64).

ίο The method of generating the aforementioned shift pulses Φι and Φ2, the bit pulses B \ to fit and the digit pulses D \ to Dt, is already well known in this field, so that a description can be omitted.

Dynamic and six-stage shift registers 17, 18, 19 are provided, with a four-digit or step register 17 and two single-digit registers 18, 19 being available. Each stage of the shift register for storing a digit belonging to the time information stores the value for this digit in the form of a binary-coded decimal number or a BCD number! and is thus composed of four-bit shift register elements.
The essential construction of the digital clock of this invention is characterized in that an adding device or summing device 20 is connected to the shift registers 17, 18 and 19 in such a way that it forms a closed circuit with these shift registers to the adding device or

jo summing device 20 includes the two input terminals 21 and 22 and the two output terminals 23 and 24. The time information stored in the shift registers 17, 18 and 19 is shifted by shift pulses Φι and Φι in the smallest time unit through the first input terminal 21 of the addition device 20 itself and by the output terminal 23 circulated in a closed circuit.

The second output terminal 24 of the addition

direction 20 has to generate a carry output signal via an adder control 25 is fed to the second input terminal 22 of the addition device 20. On the second Input terminal 22 an addition pulse is then applied during the smallest time unit, if - as will be described in the following - on the first input terminal 21 from the shift register 18 time information is switched on at the smallest time unit, with the result

> o has that for the smallest time unit a number 1 corresponds to the time unit that is stored in shift register 18, is added. But this means that the memory contents of the shift register in this case by one second is increased.

The four bit output signals from the one-bit shift register 19, which correspond to a predetermined digit position, are switched to a decoding device 27 via a single-digit time delay device 26 with parallel inputs and parallel outputs. In this case, the decoding device 27 has the seven output terminals A to G, which are jointly led to the number corner electrodes of several digit display devices, in this case, for example, six display devices are

The decoding device 27 with the seven output terminals A to G is intended for use with such numeric display devices which each consist of an electrode arrangement

with seven electrode segments according to Figure 4. The output A of the decoder 27 is routed to the electrode segment A , the output B of the decoding device 27 to the electrode segment B, while the other outputs are analogously connected to the corresponding electrode segments. If the output terminals AF G, C and D of the seven output terminals of the decoding device 27 have output signals applied to them, then - this is shown in FIG. 4 - preparations have been made for the display of the number "5" in a selective manner. Each display device has a common electrode opposite the group of number drain electrodes. The corresponding pulse from the successive pulses Di to Dt generated by the digit pulse generator 16 is applied to this common electrode as an operating voltage. As shown in FIG. 3, the display devices successively display the digits which periodically correspond to the output signals of the decoding device 27 for a digit interval. F i g. Fig. 5 shows an example of time information including six digits.

In order to keep the watch electronics compact, the display devices should preferably be made of light-emitting There are diodes made of gallium phosphide that emit light with a low current can, or consist of gallium arsenic phosphide and then be able to emit even more light. The display devices can also use liquid crystals can be made even more compact and energy-saving. Probably also exists Ability to use display tubes known in the trade as "NIXIE" and ten electrodes, each in the form of Arabic numbers. In this case, however, has ten digit-shaped electrodes the decoding device has ten output terminals.

Since the construction of the aforementioned dynamic display system including the decoding device and of the display devices well known to those skilled in the art is one Description superfluous.

In the case of six-digit time information, only the least significant digit and the third are Digit from it required to display a number up to 10, while the second digit and the fourth Digit each form a number up to 6.

For this reason, the bit outputs from the one-bit shift register 19 are sent to a detector 30 led to Zah! “N 10 and 6 to be determined. From the detector 30 then a measurement signal is generated from the output signal, when a number stored in the one-bit shift register 19 is equal to 10 or 6 The output from Detector 30 is guided to a reset member 31, which in turn is in a closed circuit with it the output of the shift register 19 is connected, that it resets the outputs. Is in the shift register 19 If a number 10 or 6 is stored, then this is the time for the digit of the next higher order of magnitude is increased by one. To do this, the measurement output of the detector 30 is used as an excess signal connected to the second input terminal 22 of the addition device 20 via an addition element 25

The electronic digital clock can be used either as a 12-hour system or as a 24-hour system Find. For this purpose, the digital clock has a setting device 32 and a detector 33, which both with the Output of the setting device 32 is connected as well as to the one-bit shift registers 18 and 19, the stand together for two adjacent numbers, where -, the detector 33 can determine whether ir the shift registers 18 and 19 together a number 12 or a number 24 is stored. Is the adjustment device 32 on the The 12-hour system is set, then the detector cuts out 33 an output signal only if the

to shift registers 18 and 19 together a number 12 Show. After the 24-hour system has been selected, the detector 33 only generates an output signal when when the shift registers 18 and 19 share the number In any case, however, the detector 33

r, an output signal switched to a reset glicd 34, which is connected to the output of the shift register 18 within the closed circuit. From the Detector 33 will also send a signal to the reset / glicd 3i happened to the outgaiigsmgn.iie both slider egister 18 and 19 reset.

The following is now the digital clock, which is reproduced with the block diagram of Fig. I, based on the with F i g. 2 reproduced circuit diagram are described, the same parts also with the

r, are identified by the same reference numerals.

As should be known, the memory contents of the dynamic shift registers 17, 18 and 19 are shifted to the right as responses to the input pulses Φι and to the output pulses Φι , whereby

jo the 6-digit time information one after the other into the Adding device 20 is given, starting with the part of the time information that the the smallest time unit. The components for the dynamic shift register should preferably

) 5 consist of field effect transistors for the circuit integration are suitable. In particular when complementary field effect transistor groups for the shift register be used, d. H. so-called C-MOS-FET field effect transistors with

■ ίο worked with a relatively low operating voltage, then there is the option of running the digital clock in a compact manner. In this case - this should already be known - not only the shift pulses Φ \ and Φ _{2 are} required, but also

4Ί their complementary quantities Φ \ and Φ}.

The time information relating to the smallest time unit is then transferred from the shift register 18 via a Reset element 34 switched to the first input terminal of the addition device 20, if there is one

so digit pulse D \ - this is also with F i g. 3 reproduced - is generated. If the A _fc angsklemme 21 accepts the first bit output of the smallest unit of time information from the shift register 18, then is switched to the second input terminal 22, a bit pulse B \ whose binary value is equal to "1". This bit pulse is an addition pulse which is switched on via an UN D logic element 40 and via an OR logic element 41, both of which belong to the addition element 25. To the AND gate 40 includes an input terminal for taking over the bit pulse Bi. But so also an input terminal for taking over the digits pulse Di. It is likely that in this Grande the bit pulse Bi once per cycle of operation of the shift register or once during the smallest unit of time the addition device 20 is performed.

The addition is carried out in an EXKLU-SIV-OR logic element 42, one of which

output signal via the output line 23 / around the shift register 19 is given, Isi the initial bit output signal! from the shift register 18 equals "1", then there is obviously a transfer process. So that this comes about, the AND logic element 43 is connected to the two input terminals 21 and 22 of the EXK ^ JSIV-OR logic element 42 for the transfer process. An output signal AND logic element 43 is fed to the fingertip terminal 22 of the addition device 20 via a dynamic F.inbil shift register m or via a delayed hip-hop circuit 44 and the ODI: R logic element 41. The pulses • Λι and Φ ι are switched to the delayed I lip-flop circuit 44. This flip-flop circuit then forwards the output signal of the AND logic element 43 to the addition device 20 as a transmission input signal when the second bit output signal from the shift register 18 is switched to the addition device 20. ή

The four-bit output signals of a digit taken from the shift register 19 are then forwarded to the decoding device 27, and / was via a register 26 with a parallel input and a parallel output, to which the FIG. 3 reproduced transmission pulses M> \ and output pulses B * can be switched. Are the output signals c of the register 19 in the with F i g. 2, then the bit outputs, whose binary meaning stands for I. 2, 4 and 8, are entered into register 26 by the <, · ■ FinghDeimpuls fti '/' i and by means of the trailing edge of the output pulse B * removed again. The output signals read out are held by the register 26 for an interval of one bit. r.

The bit outputs of the shift register 19, whose binary meanings stand for the numbers 2 and 4, are switched to an AND logic element 45. This AND logic element 45 belongs to the detector 30, which has to detect the number 6. To the AND interlocking that ^J "Fung member 45 via an OR gate 46, the digits pulses Di and D ₄ are connected. If now respectively the contents of the second and fourth digit from the smallest number of the time information then given to the shift register 19 when the Digit pulses Di and D> are generated, then it is determined by the aforementioned detector 30 whether the contents of these two digits indicate the number 6. When the number 6 is detected, an output signal is generated by the AND gate 45. To determine whether the first and w the third or fifth digit each stand for the value 10, the bit output signals of the shift register 19, whose binary meanings stand for 2 and 8, are switched to the AND gate 47. The number 10 is detected when the contents of the first and the third or fifth digit are entered into the shift register 19, ie when the digit pulses D \ and Di or D ^ are generated there, which are connected to the AND link ungs member 47 are present via an OR logic element, which corresponds to the OR logic element hO 46

The output signals of the AND gates 45 and 47 are switched via an OR gate 48 to a delayed flip-flop circuit 49. The flip-flop circuit 49 causes the output signals from the AND gates 45 and 47 under the action of the input pulses are read in and read out under the action of the output pulses lh, ie their rear edges, so that the output signal read out in this way is held for the interval of one bit. If it essentially also consists of a dynamic kinbit shift register, the flip-hop circuit 49 can also be designed as a semi-static shift register which is provided on the output side with a circuit for echoing the output signal for the time interval of one bit. Such semi-static! Registers are already known to those skilled in the art.

The output signal of the flip-flop circuit 49 is fed via a NOR logic element 51 to an AND logic element 50 which belongs to the reset element 31. After switching on the read output signal from the flip-flop circuit 49, the AND logic element 50 is brought into the .Sperrstatus. In this way, a four-bit information item of a digit stored in the shift register 19 is successively switched to the AND logic element 50 for the purpose of resetting or releasing. An output signal of the flip-flop circuit 49 is fed together with a bit pulse R \ to an AND logic element 52 which belongs to the addition device 25. An output signal from the AND logic element 52 is passed through an ODF.R logic element 41 to the second finger terminal 22 of the addition device 20. If the time information for a certain digit stored in shift register 19 stands for a number 10 or 6, then the time information stored in shift register 18 or the digit with the next higher value receives a carry signal at the moment when the first bit output signal from the shift register 18 reaches the addition device 20.

The adjustment device 32. with the a 12-hour system or a 24-hour system can be selected, for example, consists of a single-pole double changeover switch 55. which can be designed as an electronic switching device. A firm contact this Switch 55 is grounded or is connected to ground, whereas the other fixed contact with one Power source 56 is in communication. The movable contact of the switch 55 is directly with a first AND gate 57. which belongs to the aforementioned detector 33, and also with an AND gate 58 connected via an inverter 59. As can be seen, the first receives AND logic element 57 from shift register 18 a bit output signal, the binary meaning of which stands for 2, and a bit output signal is applied from the shift register 19, the binary meaning of which is the number 4 is equivalent to. On the other hand, the second AND logic element 58 receives from the shift register 18 a bit output signal, the binary meaning of which stands for 1, is switched on, but also from the Shift register 19 a bit output signal, the binary meaning of which corresponds to the number 2

As shown in FIG. 2 can be seen, the movable contact of switch 55 on the grounded fixed contact is thus set to a 12-hour system, then the first AND logic element 57 is made inoperative. Now a 24-hour system Then the movable contact of the switch 55 with the power source 56 is required connected fixed contact switched, which in turn the AND gate 58 inoperative is made.

In the case of a 12-hour system, is transferred to the Shift register 18 is inputted time information corresponding to the number I to the shift register 19 but a time information corresponding to the number 2, then the second AND logic element generates a Output signal. If, on the other hand, in the case of a 24-hour system, one of the Time information corresponding to number 2 is entered, but to shift register 19 one corresponding to number 4 Time information, then an output signal is generated by the first AND logic element 57.

The output signals of the first AND gate 57 and the second AND gate 58 are fed to a flip-flop circuit 62 via an OR gate 60 and an AND gate 61, which in turn receives the digit pulse Ch. The time information of two digits for hours is then heard in the 34. This output signal is, however, also switched to the AND logic element 50, which belongs to the reset device 31, via a NOT-OR logic element 51. As a result, the two AND gates 63 and 50 are rendered inoperative in order to enable the four successive bit output signals from the shift registers 18 and 19 to be reset.

The circuit of this electronic digital clock is here interpreted by the Au ^r construction is preferably such that it can be integrated, in particular by Großintegnitionstechnikcn. Field effect transistors are preferred for circuit integration.

The preferred clock not only allows the inclusion of compensation circuits that are for the time information for numbers 10, 6, 12 and 14, as previously mentioned, are required. It also enables a switching tune to

rutlLI I, WCIIII UCl

Digit pulse Ds is present. If the digit pulse / Λ is generated, then causes the flip-flop circuit 62 that an output signal from the first AND gate 57 or from the second AND gate 58 is entered by the input pulse Β »Φ \ and through the falling edge of the Output pulse Bn is read out, the pulse thus read out being held there for a digit interval. An output signal of the flip-flop circuit 62 is passed on via an inverter 64 to an AND logic element 63, which is fed to the resetting element ruiLHMcui-Ti liner zjneniposmorieii in uer zeitweise, furthermore the taking in of a circuit for resetting certain digit positions, a circuit for ending the addition the number I to any digits, ie a stop-clock circuit. It is also possible to include a time correction circuit and a time setting circuit. All these different types of .circuits! •• can be integrated in a compact manner on a single semiconductor chip that is only a few square millimeters in size.

For this purpose 3 sheets of drawings

Claims (4)

Patent claims: 1. Electronic digital clock with a pulse generator for generating a time signal in one Interval of the smallest time to be counted, with a slice register circuit for storing off time data consisting of a number of digits, each of which is stored in a binary-coded decimal number, the order of the smallest digit the smallest time specification is equal to the smallest time, with one connected to the shift register circuit and one closed with this one Circle-forming adding means for adding up the time data from the shift register circuit and of the time signal and with a time image device connected to the shift register circuit for Representation of the time data in the shift register circuit, characterized in that in the set register circuit (17,18, 19) time data digit parts in series by a number from each of four series bit levels existing series digit levels can be stored that the Adding device (20) is constructed from an adder which performs a time counting and that the The adder is connected to a first output terminal (21) with a first shift register stage (18) of the shift register circuit and a second Input terminal (22) for receiving the time signal when a bit output signal is present an application of 1 in the smallest time specification on the first entry cycle (21) of the first Shift register stage (18) and one with an input terminal of a second shift register stage (19) the shift register circuit connected sum output terminal (23) and a transfer output terminal (24) which has a A one-bit time delay circuit (44) having the second input terminal (22) for providing a Transmission signal is connected 2. Electronic digital clock according to claim 1, characterized in that the Addiereinrichturg ^{(20) a 1} providing a sum output signal; Exclusive-OR.Verknüpfungseinrichtung (42) and an AND logic element causing a transmission signal (43). 3. Electronic digital clock according to claim I or 2, characterized in that on the second Shift register stage (19) each have a detector circuit (30) and a reset element (31) connected are that with the detector circuit (30) the presence of a decimal number from time data of Ten and decimal numbers of predetermined digits of those stored in the shift register circuit Time data of six can be displayed that with the reset element (31) the decimal digits of ten and Six can be reset to zero and that a display signal supplied by the detector circuit (30) for the decimal digits ten or six via the adding device (20) to the time data of the next higher digit can be added. 4. Electronic digital clock according to one of claims I to 3, characterized in that an a second of the first and second shift register stages (18, 19) of the shift register circuit (17, 18, 19) Detector circuit (33) is connected with an adjusting device (32) for a 12 or 24-hour system with the first and one second reset member (31,34) in the closed Circle is connected.