DE2539073B2 - Field effect transistor with insulated gate electrode and process for its manufacture - Google Patents

Description

25th

The invention relates to a field effect transistor with an insulated gate electrode (IGFET), consisting of a electrically insulating substrate, an island of single crystal silicon on part of a surface of the Substrate, the island having a source and a drain region at opposite ends, one Source electrode and a drain electrode, a channel zone between the source and drain zone, a dielectric layer over the channel zone and a gate electrode over the dielectric layer, and a method for its production.

It has been shown that the gate dielectrics of known IGFETs of the silicon-on-sapphire type (SOS) Early failures (breakdowns) occur when a bias voltage greater than approximately 36 volts between the gate electrode and the source-drain regions is applied. This breakthrough seems to be with the Polysilicon-silicon oxide-silicon-sapphire interface in the IGFET. The Achilles heel, d. H. the weakest point of the well-known SOS / IGFET technology appears to be on the opposite edges of the silicon island that forms the channel zone of the Includes IGFETs, particularly where the edges of the channel region meet the sapphire substrate surface.

The object of the present invention is to propose an IGFET and a method for its production, with which the aforementioned disadvantages are avoided, rather one that was achievable compared to previously Values significantly higher, at least twice as high breakdown voltage is achieved. This task will according to the invention achieved in that the dielectric layer is on opposite sides of the Channel zone extends to the surface of the substrate and further over parts of this surface and that on Extensions of the gate electrode are arranged on both sides of the channel zone, which extend from the substrate surface are separated by the dielectric layer.

The invention is of particular advantage to use in the production of SOS complementary transistors, which are used in many types of semiconductor circuits.

The dielectric layer can be silicon oxide, silicon nitride, aluminum oxide, or combinations thereof contain.

The inventive method for manufacturing the new IGFET comprises manufacturing an island of epitaxially applied, doped silicon on an electrically insulating substrate and a dielectric layer over both the island and parts of the substrate, in such a way that they! »I from extending away from opposite sides of the island

In one embodiment of the method according to the invention, the aforementioned manufacturing step is carried out by adding a layer of doped Silicon is formed epitaxially on the insulating substrate, the silicon layer is etched in such a way that an island is created, a thin layer of monocrystalline or polycrystalline silicon on the silicon island and also provided on the insulating substrate and then the last mentioned thin silicon layer is completely oxidized to form a dielectric layer of silicon oxide.

In another embodiment of the method according to the invention, this process is carried out, by epitaxially placing a layer of doped silicon on an electrically insulating substrate generated, the silicon layer to form a surrounded by a thin area of the doped silicon The mesa is selectively etched and both the mesa and the thin area surrounding silicon are oxidized until the thin area used to form a dielectric layer made of silicon oxide that extends over an island Silicon and, moreover, also extends over the substrate, is completely oxidized.

In a further embodiment of the method according to the invention, the production of a Island of epitaxial, doped silicon on an electrically insulating substrate and a dielectric Layer performed over both the island and parts of the substrate by placing the silicon island in accordance with above illustration and then a dielectric layer made of, for example, silicon nitride, aluminum oxide or silicon oxide is provided over both the silicon island and the substrate. The dielectric Layer can consist of several layers of one of the aforementioned materials and a layer of silicon oxide, which is formed by the oxidation of the surface of the silicon island.

The invention is explained below with reference to the drawings which illustrate preferred exemplary embodiments explained in more detail. It shows

F i g. 1 shows a known IGFET in cross section, the section running through the channel area,

F i g. 2 an embodiment of the IGFET according to the invention in a perspective view from top right, without passivation layer,

Fig. 3 to 8 and 10 and 11 cross sections of the IGFETs of the invention that incorporate various treatments in making an embodiment represent,

FIG. 9 shows a section along the plane 9-9 in FIG. 8 through the part that is to become the canal area,

12 and 13 show cross sections of the IGFET according to the invention in different manufacturing steps of a another embodiment of the method according to the invention,

Figs. 14, 15 and 17 are cross sections for explaining a further embodiment of the method according to the invention and

Fig. Ib is a cross-section along the plane 16-16 in

15 through the part of the IGFET which is provided for the channel area.

In the following description, the same reference numerals are used in different drawings for same parts used.

In Fig. 1, a known IGFET 10 is shown, in which the problem of premature breakdown of the dielectric Layer (silicon dioxide) occurs when a bias voltage greater than 36 volts between gate electrode and applied to the source-drain regions. The IGFET 10 consists of an electrically insulating Substrate 12, e.g. B. made of sapphire or spinel, an island 14 made of single-crystal, η-doped silicon on one Surface 16 of the substrate 12, a silicon oxide layer 18 which the gate dielectric over the Silicon island 14 represents, and a gate electrode 20, e.g. B. of doped polysilicon over the silicon oxide layer 18. The aforementioned premature breakthrough in known IGFETs 10 appears with the polysilicon-silicon oxide-silicon-sapphire interface 22 related.

Example I.

According to the invention, the problem caused in the area of the interface 22 (FIG. 1) is eliminated in the case of a Embodiment of the inventive IGFET 30 (shown in FIG. 2) resolved that a structure is proposed or provided that eliminates this interface. According to Fig. 2 shows the IGFET 30 an electrically insulating substrate 32, e.g. B. made of sapphire or spinel, on the surface 36 a Silicon island 34 is provided. A dielectric layer 38 is formed over a portion of the island 34 Silicon oxide is formed over the part that forms the channel region of the IGFET 30, the Layer 38 extends over both silicon island 34 and portions of surface 36 of substrate 32. on of dielectric layer 38 is a polysilicon electrode 40 applied. It acts as a gate electrode over the island; their extensions extend away from opposite sides of silicon island 34 and away from surface 36 of substrate 32 separated by dielectric layer 38. In this way, the IGFET 30 has no interface between the gate electrode and surface 36 of substrate 32 near the edge of silicon island 34; it will however, a structure is achieved in which the breakdown voltage of the IGFET 30 is at least twice as large like that of the known IGFET 10.

With reference to FIGS. 3 to 11, an exemplary embodiment of the method according to the invention for producing the IGFET 30 is described below. In FIG. 3, the substrate 32 is shown with a layer 34a of single-crystal, η-doped silicon, which is deposited on the surface 36 of the substrate 32. The substrate 32 can have a thickness of between about 0.025 and 0.050 cm. The silicon layer 34a may have a carrier concentration of e.g. B. have between about 1 to 2 χ ΙΟ ¹⁵ arsenic atoms / cm ³ and a thickness of between 0.6 and 0.8 μπι. The silicon layer 34a is preferably deposited on the (1102) sapphire plane by any method known in the semiconductor art. For example, the silicon layer 34a can be deposited epitaxially on the surface 36 by pyrolysis of silane (SiH ₄ ).

The epitaxial silicon layer 34a is now delimited as a rectangular mesa 346 (FIG. 4), which is bounded by a thin area 34c of the silicon layer 34a is surrounded, which is shown by photolithographic processes below Application of a suitable photoresist and etchant is achieved. The thickness of the thin silicon area 34c is between 5 and 50 nm, preferably between 10 and 30 nm. When the mesa 346 is formed and the surrounding thin region 36c of silicon layer 34a (Fig. 3) become parts of the silicon layer 34a etched away until the outer edges of the

ίο thin area 34c have almost completely disappeared. Under these circumstances, the area 34c near the mesa 346 is typically between about 10 and 30 nm. The exact thickness of the thin region 34c should be determined with conventional, known Measurement methods are determined.

The silicon structure according to FIG. 4, consisting of the thin area 34c and the mesa 346, is now oxidized, e.g. B. by heating in HCl-containing steam at a temperature of about 900 ° C for 50 minutes to completely close the thin portion 34c oxidize and form a dielectric layer 38a of silicon oxide (FIG. 5) over silicon island 34. An important feature of the IGFET 30 of the present invention is the fact that the dielectric layer 38a is extending across both silicon island 34 and surface 36 of substrate 32 from opposite sides Side of the silicon island 34, as shown in FIG. 5 is shown. Part of the dielectric layer 38a will form the gate dielectric 38 of the IGFET 30 according to the invention. The dielectric layer 38a consists entirely of silicon dioxide.

A layer 40a of polysilicon is deposited over the dielectric layer 38a to a thickness of approximately 0.5 μm using known methods. The in F i g. 6 is undoped at this point in time in the manufacturing process of the IGFET 30. A strip 42 of boron glass is placed on the polysilicon layer 40a and using known photolithographic processes, e.g. B. using a suitable photoresist and etchant of buffered hydrofluoric acid, shaped so that it is substantially the shape of the polysilicon layer 40 shown in FIG.
Boron is now diffused from the delimited boron glass strip 42 into the polysilicon layer 40a by heating the structure according to FIG. 6 to a temperature of approximately 1050 ° C. for approximately 15 minutes in a helium atmosphere. After this diffusion, the boron glass strip 42 becomes cleaner using it

so hydrofluoric acid (this does not attack the polysilicon layer 40a) is etched away. Next, the polysilicon layer 40a is treated with an anisotropic etchant composed of KOH, alcohol and water to remove all parts of the polysilicon layer 40a except for those shown in FIGS. 7 and 2, which had been doped with Boi from the boron glass strip 42, to be etched away. The anisotropic etchant results in sloping edges of the polysilicon layer 40.
The portions of the dielectric layer 38a that are not directly under the polysilicon layer 40, i. All parts except the (silicon oxide) dielectric layer 38 (FIGS. 8 and 2) are now also buffered! Hydrofluoric acid etched to expose areas of the top surface of silicon island 34 for dopant diffusion to form source and drain regions.

F i g. 9 is a cross section through the central area the IGFET structure, d. H. by the area that is to become the channel of the IGFET 30 according to the invention

F i g. 8 and 9 are cross-sections of the IGFET according to the invention without a passivating layer on the IGFET, thus in the same representation as in the perspective illustration according to FIG. 2.

Measures to form the source and drain regions of the IGFET 30 are now taken. For this purpose, a glass layer 44 made of ρ + -doped glass, such as. B. boron glass, deposited on the surface 36 of the substrate 32, on the exposed areas of the silicon island 34 and on the polysilicon layer 40, as shown in Fig. 10, by suitable, known methods. The p + dopant from the glass layer 44 is now diffused into the adjoining areas of the silicon islands 34 in order to achieve the properties shown in FIG. 11 to form source and drain regions 46 and 48, respectively. The diffusion takes place by heating the structure shown in FIG. 10 to approximately 1050 ^° C. for approximately 15 minutes in a helium atmosphere. The area of the silicon island 34 between the source and drain zones 46 and 48 is the channel zone 50 of the IGFET 30, which lies completely below the (silicon oxide) dielectric layer 38 and the polysilicon layer 40 (gate electrode)

Contact openings are now in the glass layer 44 over the source and drain zones 46 and 48 for Metal (aluminum) electrodes 42 and 54, respectively, are formed with these areas. An opening not shown in the Glass layer 44 for an electrical contact to the (gate electrode) polysilicon layer 40 is also used intended. In addition to its function as a dopant source, the glass layer 44 also serves as a passivating layer for the IGFET 30.

During the operation of the IGFET 30, it was found that the breakdown voltage with a structure according to FIG. 11 at least twice as high as in the known IGFET 10 according to FIG. The reason for these improved operating characteristics is at least in part because IGFET 30 has a structure in which the gate dielectric, that is, SiO ₂ layer 38, over both island 34 and surface 36 of the substrate 32 is formed, as best shown in FIGS. 2 and 9; and that the polysilicon layer 40 is of the same circumference as the dielectric layer 38, whereby the aforementioned weakness of the polysilicon-silicon-silicon-silicon-sapphire interface 22 (FIG. 1) of the known IGFET 10 is eliminated.

Example II

In the exemplary embodiment of the method according to the invention described above, this is partial Etching and the formation of the mesa from the epitaxial silicon layer 34a (see FIG. 4) with regard to the Accuracy demanding and in some ways time consuming because of the need to etch the This thin area 34c is uniform to a thickness of, for example, between 10 and 30 nm Operation usually requires close observation and testing. However, the partial etching is a problem another embodiment of the method according to the invention, which is shown in FIGS. 12 and 13, avoided. In this case, after the silicon layer 34a on the surface 36 of the substrate 32 according to FIG is deposited, the silicon layer 34a is etched using known photolithographic processes to form the to form rectangular silicon island 34 as shown in FIG. Next, a layer 34d of epitaxial, single crystal or polycrystalline silicon is deposited on top of the Silicon island 34 and surface 36 of substrate 32 deposited to a thickness of between 5 and 50 nm, preferably between 10 and 30 nm.

The structure according to FIG. 13 is then oxidized in HCl-containing steam at a temperature of about 900 ⁰ C for about 15 minutes until the silicon layer Md completely to silicon oxide, primarily silicon dioxide, is oxidized. After the structure according to FIG. 13 has been oxidized in this way, it assumes the structure previously described in connection with FIG

ίο has been, with the oxidized layer now the Silicon oxide layer 38a (dielectric) of Figure 5 The fabrication of IGFET 30 (Fig. 11) from this stage on is the same as previously in context with the F i g. 5 to 11.

In FIGS. 15, 16 and 17, an IGFET 30a is shown as a further exemplary embodiment of the invention, that is similar to that shown in FIGS IGFET 30 is, with the exception of the gate dielectric. In the IGFET 30a, the gate dielectric is made of a dielectric layer 39 made of insulating material, specifically not a thermally grown silicon oxide, but for example made of silicon nitride or (S13N4), aluminum oxide (Al ₂ O ₃ ), vapor-deposited silicon oxide. The gate dielectric 30a can preferably indicate a composition of two layers have electrically insulating material, such as the dielectric layer 39 and a dielectric Layer 38c (Fig. 17) of silicon dioxide. As a result, the polysilicon layer extends in the IGFET 30a 40 (gate electrode) from opposite sides of silicon island 34 and is from surface 36 of the Substrate 32 through the dielectric layer 39 made of silicon nitride or aluminum oxide according to FIG. 16 separately The one shown in FIGS. 15, 16 and 17 dielectric layer 38c extends only over the Channel zone 50 of the IGFET 30a Although the IGFET 30a also without the dielectric layer 38c made of silicon oxide can be operated, however, a composite dielectric of this and dielectric

Shift 39 preferred.

The exemplary embodiment of the method according to the invention for producing the IGFET 30a is below with reference to FIG. 3,12,14,15, and 17. The silicon island 34 (Fig. 12) The surface 36 of the substrate 32 is formed by delimiting the epitaxially deposited silicon layer 34a (FIG. 3) as previously described. A dielectric layer 38b (FIG. 14) is deposited on the exposed surface of the silicon island 34 grow, for example by heating the silicon island 34 in HCl-containing steam at a temperature of approximately 900 ^° C. for approximately 50 minutes. The thickness of the dielectric layer 38ύ can be between approximately 2 and 90 nm.

Next, a dielectric layer 39a (Fig . 14) made of silicon nitride, alumina or evaporated silicon oxide is deposited on the dielectric layer 3Sb to form a composite dielectric layer. Silicon nitride can be produced by reaction (NH ₃₎ are deposited at a temperature of about 900 ⁰ C in hydrogen (Hr) atmosphere of silane (S1H4), and ammonia. Aluminum oxide, if it is provided for the dielectric layer 39a, can be applied in that first an aluminum layer is provided and the aluminum then z. B. by anaodic oxidation, which as such is known to be oxidized. The vapor deposition of silicon oxide can be caused by the reaction of silane and

Oxygen can be achieved in a neutral (N2) atmosphere at about 400 ⁰ C. The thickness of the dielectric layer 39a can be between approximately 10 and 100 nm.

The polysilicon layer 40a (Fig. 14) is now on the deposited dielectric layer 39a and diffused from the boron glass strip 42 (FIG. 14) in the previously in connection with the explanation of the formation of the polysilicon layer 40 of the IGFETs 30 explained way

The doped polysilicon layer 40a (FIG. 14) is then treated with an anisotropic etchant composed of KOH, alcohol and water to form the layers shown in FIG. 2 etched polysilicon layer 40, ie to form this layer over the future channel region 50 (FIG. 17) of the IGFET 30a. Using the polysilicon layer 40 as a mask, the dielectric layers 39a and 386 are etched to the shape shown in FIGS. 15 and 16. If the dielectric layer 39a is made of silicon nitride or aluminum oxide, it is treated with hot phosphoric acid to form the dielectric layer 39 ( Figs. 15 and 16) etched. The dielectric layer 3Sb made of silicon oxide is etched with buffered hydrofluoric acid to form the dielectric layer 38c (FIGS. 15 and 16).

The construction of the IGFET 30a, which has been completed so far, as shown in FIGS. 15 and 16, the p + -doped layer 44 is now shown in accordance with FIG F i g. 17 coated in the same way as previously described with reference to FIGS. 10 and U. has been. From this stage on, the formation of the source zone 46, the drain zone 48, the channel zone proceeds 50 and the electrodes 52 and 54 for the source and drain zones in the IGFET 30a exactly in the same

ι ο way as previously described for the IGFET 30.

Although in the described exemplary embodiments the IGFETs 30 and 30a are doped Polysilicon gate electrode (doped polysilicon layer 40) is provided, it is within the scope of Invention to provide the IGFETs 30 and 30a also with a metal (gate) electrode, e.g. B. made of aluminum, molybdenum, tungsten or alloys thereof, instead of the doped polysilicon gate electrode; this can be seen in known ways. Gate electrodes off doped polysilicon (layer 40) for the IGFETs 30 and 30a, metal gate electrodes are preferred, because they give the IGFETs better behavior, higher operating speeds and lower power dissipation.

For this purpose 4 sheets of drawings

Claims (14)

Patent claims: 1. Field effect transistor with insulated gate electrode (IGPET), consisting of an electrically insulating substrate, an island of single crystal silicon on part of a surface of the Substrate, the island having a source and a drain region at opposite ends, a source electrode and a drain electrode of a Kstnalzone between the source and the Drain zone, a dielectric layer over the channel zone and a gate electrode over the dielectric layer, characterized in that the dielectric layer (38) is on opposite sides of the channel zone (50) except for the surface (36) of the substrate (32) and further over parts of this surface (36) and that on the R.anal zone (50) extensions of the gate electrode are arranged, which extend from the substrate surface before (36) are separated by the dielectric layer (38). 2. IGFET according to claim 1, characterized in that the substrate consists of sapphire or spinel 3. IGFET according to claim 1 or 2, characterized in that the dielectric layer consists of Silicon oxide, silicon nitride or aluminum oxide consists. 4. IGFET according to one of claims 1 to 3, characterized in that the gate electrode made of poly crystalline silicon, aluminum, molybdenum or tungsten. 5. IGFET according to claim 1, 2 or 4, characterized in that the dielectric consists of a Layer of thermally grown silicon oxide and a layer of vapor-deposited silicon oxide, Silicon nitride or aluminum oxide. 6. A method for producing an IGFET according to any one of claims 1 to 5, characterized in that a) an island (34) made of epitaxially applied, doped silicon on an insulating Substrate (32) is provided and a continuous dielectric layer (38) over the island (34) and over areas of substrate (32) extending from opposite sides of the island (34) extend away, is formed, b) a layer (40a) of gate electrode material is applied to the dielectric layer (38) and limited and therefrom an electrode (40) is made, which between the ends of the Island (34) forms the gate electrode and extends from opposite sides of the island (34) in Form of extensions of the gate electrode extending outwards, the extensions of the gate electrode through the dielectric Layer (30) are separated from the substrate (32), c) the dielectric layer (38a) with the exception of the part below the electrode (40) (38) is etched away and d) the exposed areas of the island (34) using the gate electrode (40) as a mask to form source and drain zones of the IGFET (30) are doped. 7. A method for producing an IGFET according to claim 7, characterized in that in the treatment step (a) a silicon layer is deposited epitaxially on the insulating substrate gen and etched to form the island that a thin layer (346) of between about 5 and 30 nm thickness of silicon deposited both on the island and on the substrate and to the Formation of the dielectric layer is completely oxidized. S. The method according to claim 6, characterized in that in the course of treatment step (a) a layer of doped silicon is deposited epitaxially on the insulating substrate, that this layer is used to form a mesa surrounded by a thin area (34c) of doped silicon ( 34b) is etched, the thin area (34c) having a thickness of between approximately 5 and 50 nm, and that the thin area (34c) is completely oxidized and the mesa (34b) is partially oxidized to form an island ( 34) of epitaxially doped silicon and an overlying dielectric layer (38) extending over parts of the substrate. 9. The method according to claim 6, characterized in that in the course of treatment step (a) a layer of doped silicon is deposited epitaxially on the substrate, limited and etched so that the island is formed, and that a dielectric layer made of silicon nitride on both is deposited on the island as well as on the substrate. 10. The method according to claim 9, characterized in that the silicon layer is oxidized to Form a dielectric layer of silicon oxide over it before leaving the dielectric layer Silicon nitride is provided over both the island and the substrate, being the dielectric Layer of silicon nitride is deposited on the dielectric layer of silicon oxide. 11. The method according to claim 6, characterized in that as part of the treatment step (a) a silicon layer is deposited epitaxially on the substrate, limited and etched to form the island, and that a dielectric layer of aluminum oxide both on the island and on the Substrate is formed. 12. The method according to claim 11, characterized in that the silicon island for formation a covering dielectric layer of silicon oxide is oxidized before the dielectric Aluminum oxide film is formed provided on the silicon oxide dielectric film. 13. The method according to any one of claims 6 to 12 characterized in that a) a polysilicon layer is deposited on the dielectric layer, b) a first glass layer with first dopants for the polysilicon layer is deposited on the polysilicon layer, c) an area is delimited from the first glass layer, which is the area of the to be formed The gate electrode including its extensions, d) said first dopant from the limited area of the first glass layer in the polysilicon layer diffuses to form the gate electrode and its extensions will, e) the limited area of the first glass layer is removed, f) the polysilicon layer with the exception of the The gate electrode and its extensions are etched away, g) the dielectric layer is etched away with the exception of the area below the gate electrode and its extensions, h) a second glass layer with a second dopant for doping source and drain zones in the island is deposited on this and the gate electrode,
i) the second dopant is diffused from the second glass layer into the island to form the source and drain zones,
j) contact openings are provided in the second glass layer over the source and drain zones and is k) Metal electrodes deposited through the contact openings for the source and drain zones will. 14. The method according to claim 13, characterized in that the polysilicon layer on the dielectric layer is deposited to a thickness of approximately 0.5 μΐη.