DE2736119B2 - Circuit arrangement for telecommunications switching systems, in particular telephone switching systems with individual central devices that are common to them - Google Patents

Description

The invention relates to a circuit arrangement for

· "'Telecommunication exchanges, especially telephone exchanges, with individual devices and with at least two central devices common to them and with information lines individually assigned to them, and with connection means by means of which

^4r> the individual devices can be connected to one of the central devices via the corresponding information box, and with switching devices assigned to the central devices, which monitor the operational readiness of the respectively assigned central device.

^r ' ^(l ensure the connection of the individual devices only to a single central device that is ready for operation and for this purpose are individually equipped with bistable flip-flops, the position of which indicates whether the relevant

"· 'Central device individual devices are switched on may or may not.

A circuit arrangement of this type is already known from DE-AS 22 17 665. In the bistable flip-flops provided here, one corresponds in each case Switching position of a first of two central computers and a second switching position of a second central computer. The flip-flops are controlled by the computers. Several switching devices are provided, each with a flip-flop. the Flip-flops of the multiple switching devices are under the controlling influence in parallel operation the central computer.

In the one known from this Ausleeeschrift

Circuit arrangement is made with the help of timers that are provided in the central computers, ensures that when a changeover operation is carried out ("equivalent circuit") all the bistable flip-flops detected who that. The operational reliability in the case of an equivalent circuit of one of the two Computer by the other computer is so in the known case with the help of timing elements of the central computer accomplished the Nachimpuises generated with the help of a Eisatzschaltungvorgang catch up on any switchover of the relevant lines that has not yet been completed.

The object of the invention is to improve operational safety compared to the known circuit arrangement when handling replacement switching operations to i ~> increase and independently of time switching elements to accomplish. In addition, it should be achieved that in the case of errors of the first order (single errors) in an Handling of substitute switching operations involved circuits of the switching devices the operating 2 <i security is not called into question. If a first-order error occurs, an equivalent circuit should be set up either take place immediately automatically or - provided that such an equivalent circuit only corrects the error that has occurred would bring about - be prevented. - '"> In any case, if an error occurs, the first Order, the continuation of ongoing operations must be guaranteed.

This object is achieved according to the invention in that the bistable multivibrators provided individually in the switching devices each have an input and output corresponding to an operating position of the relevant central device and an input corresponding to a reserve position of the relevant central device. · Corresponding output in each of the switching devices not only with connection means for connecting the individual devices to the central device assigned to the respective switching device but also with the input or inputs corresponding to ^{the reserve position 4 "in the other switching device or in the other} Switching devices provided flip-flop or flip-flops is connected, and that the input corresponding to the reserve position of each of the flip-flops in the ⁴ > relevant switching device is also connected to a signal current path for signaling the cessation of operation is connected iebsbereitschaft a central unit, and that the corresponding input is the operating position of each of the flip-flop circuits connected in the ^w relevant switching device with a start signal current path to transmit a start pulse to initiate the operating state of the central unit concerned.

Depending on the type of error first order, occurs at ^"1 ^ one of the invention to the equivalent circuit involved circuits, an equivalent circuit using the switching devices is either effected at once or eliminated. Also in the event of such a failure is ensured that ^b0 simultaneously only a single central device can be connected to the individual devices.

In the drawing, an exemplary embodiment of the invention is shown only in the constituent parts that contribute significantly to its understanding. ^b5

In the middle of the upper part of the drawing, a number of individual devices H t to Hn are indicated. This inHiviHiipMpn { ".prätp ctphpn are altprnativ with pinpm central two units Z 1 and Z 2 in the information exchange. The central equipment systems of L 1 and L 2 individually assigned Further, the central equipment Umschalteeir.richtungen Ui and LJ 2 associated with this guarantee, that only one of the two central devices can be in information exchange with the individual devices Hi to Hn . These switching devices also accomplish the equivalent circuit (cf. Peter R. Gerke "Computer-controlled Vermittlungssysteme", Springer-Verlag, Berlin / Heidelberg / New York, 1972 ), i.e. the switchover in such a way that a central device which is in the operating position up to a certain point in time is switched to a reserve position and a central device which is in the reserve position up to this point in time is brought into the operating position.

The individual devices can be connection sets and / or line sets of any kind, e.g. B. to internal connection sets, external connection sets for incoming and / or outgoing traffic, trunk connection sets in private branch exchanges, line termination circuits for local and long-distance lines and the like. Act. Likewise, the individual devices can also be registers, setting devices for voters and / or switching matrices and the like. The central devices ZX and Z 2 can be correctors, central markers or, in general, central control units (computers with stored programs).

The two line systems L 1 and Ll each consist of three line groups Vi. Av 1 and B ! and V 2, A ν2 and B2, respectively. The line group Vi, which thus comprises a plurality of circuits, is used to transmit information from one of the individual devices to the central device Zi. The information is transmitted in a manner known per se in encoded form. This can be a parallel code, a serial code or a mixed code. In a corresponding manner, the line group Bi is used to transmit information from the central device Zl to one of the individual devices. This information is also transmitted in coded form, which can also be a parallel code, a serial code or a mixed code.

The same applies to the line groups of the line system L 2.

So that only one of the individual devices Hi to Hn is involved in the exchange of information during the previously indicated information exchange with the central device Zl, i.e. during the transfer of information to this central device or from this central device, the gate circuits GiH to Gbn 1 intended. In the drawing, the actual wiring is not specified, but the gate circuits are intended to symbolically represent the logical conditions under which information can be exchanged with the individual devices via the multiple lines. According to the drawing, these gate circuits are each connected to one of their inputs to the line groups Av i . However, this line group Avi actually represents a multi-wire address multiple. The mentioned gate circuits are now connected to the line wires of this address multiple with their multiple address inputs each. Only the gate switching. They desienisen individually

duel device, ζ. B. H 1, the address of which is sent out from the central device Zl via the address array AvI, each coincidentally receive an input signal via all of their address inputs. For this purpose it is equally possible to assign individual address receivers to the> gate circuits and to connect their outputs to a single address input of each of the gate circuits.

In addition, each of the gate circuits is connected to i <> a so-called bus enable circuit el for identifying the respective operating state (operating position or reserve position) of the central device Zl. These bus enable circuits e 1 and el are provided separately from the address multiples Av 1 and Av 2 . Via these bus enable circuits el and e2, a bus enable signal is used to signal which of the two central devices Z1 and Z2 is currently in the operating position. The central device whose corresponding bus enable circuit does not have the bus enable signal is in the reserve position at the relevant point in time. If now both the address corresponding to an individual device and the bus enable signal reach the gate circuits Gi 11 to Gbni, the gate circuits concerned, e.g. B. Gi 11 and Gbn 1, permeable to information coming from the output, e.g. A 1, of an individual device, e.g. B. H 1, are to be transmitted via the line group V1 to the central device Zi or are to be transmitted from this via the line group Bi to an input, for example Ei, of the individual device in question.

Since the line systems L 1 and L 2 are constructed in exactly the same way, which also applies to the gate circuits connected to the line systems, the preceding statements about the line system L 1 and the information exchange carried out via it also apply to the line system L 2. The individual devices are also applicable Wl to Hn constructed completely symmetrically with respect to the two line systems and the two central devices Zl and Z2. In addition, the switching devices U 1 and t / 2 are constructed identically to one another, which also applies to the central devices Z1 and Z 2.

As stated, only one of the two bus enable circuits e 1 and e 2 carries the bus enable signal. Accordingly, only one of the two central devices is in at any one time Operating position; the other central device is then in reserve.

Each of the central device is a monitor current path i u and u 2, a monitoring signal to a monitoring switching device UEi or Ü2 of his respectively assigned Umscha'teeinrichtung Ui or U 2. The surveillance signal consists of a continuous sequence of pulses, that is pulses, which have an even time interval from pulse to pulse. Each of the monitoring switching devices is equipped in a known manner with a time measuring device which measures the time interval between the received pulses of the monitoring signal. B. Oi, an alarm signal via & ⁵ gate circuits, e.g. B. G 13 and G 12, to an input k 12 of a bistable trigger stage Ki . This flip-flop input it 12 corresponds to that switching position of the bistable flip-flop K 1, which is assigned to the reserve position of the central device Zl. The flip-flop K 1 receives an alarm signal via its flip-flop input k 12, if there; to be transmitted via the monitoring current path ü 1 «monitoring signal of the central device Zl remains off.

It is now assumed that the monitoring switching device L? Das: receives monitoring signal. It consequently does not emit an alarm signal via its output to the gate circuit G 13. It should also be assumed that no signal is present at the second input of the gate circuit G ic via the signal current path d 1 either. As a result, this gate circuit does not emit an output signal. It is also assumed that the bus enable signal is not present in the bus enable circuit e2. In this switching state, there are no signals at the two inputs of the gate circuit G 12. As a result, this gate circuit does not emit a signal via its output either. There is no signal at Kippstufeein input k 12. - It is also assumed that a start pulse is transmitted to the right input of the gate circuit GlI via a start signal current path c 1. This start pulse should be issued manually and transmitted via the input g 1 of the gate circuit Gz 1 of the central device Zl aul not shown in detail Since now there is no signal at the left input of the gate circuit GIl, on the other hand the mentioned start pulse to the right input of the gate circuit GIl arrives, the start pulse is passed to Kippstufeein input k 13 of the K 1 flip-flop. As a result, the flip-flop K 1 changes its switch position, so it now assumes that switch position which indicates the operating position of the central device Z1.

Because the flip-flop K 1 has assumed the switch position corresponding to the operating position of the central device Zl, it emits a bus-enable signal on the bus-enable circuit e 1 via its flip-flop output λ 11. This creates the prerequisite that the gate circuits G / 11 to Gbn] can be controlled by means of the addressing described. As a result, the central device Z1 can now communicate with each of the individual devices Hi to Hn for the exchange of information via the line system L 1.

The bus enable signal applied to the bus enable circuit el also reaches the switching device U 2 via a blocking input 52. This signal is passed on via the gate circuit G 22 to the flip-flop input A: 22 and causes flip-flop K 2 to be the one Assumes the switching position - or maintains it, if it had already assumed it - which corresponds to the reserve position of the central device Z 2 A start pulse possibly arriving via the left input of the gate circuit G 21; cannot be passed on to the flip-flop input k 23 because the output signal of the gate circuit G 22 is also present at the right input of the gate circuit G 21 and makes this gate circuit impermeable to a start pulse

The two central devices Z1 and Z2 are in ar routinely, as is known, d. H. switched at regular time intervals This means that there; one central device is switched from the operating position to the reserve position and the other Device is switched from the reserve position to the operating position. The impetus for a routine change

circuit comes from the central device that is currently in reserve. It is assumed that the central device Z2 is in the reserve position and the central device Z1 is in the operating position. The two central devices Zl and Z2 are equipped with two time switch devices Zs 1 and Zs 2. If the central device Z2 has been in the reserve position for a certain waiting time, its time switch device Zs 2 emits a blocking pulse to the central device ZX via a current path R 2/1 used for routine switching after this waiting time has elapsed. The delivery of the blocking pulse depends on the central device Z2 being operational. The blocking pulse passes via the gate circuit Gt 1 of the central device Z ί and via the gate circuit G 13 and G 12 of the switching device U to the flip-flop input Jt 12 of the flip-flop K 1, which corresponds to the reserve position of the central device Zl. The flip-flop K 1, at whose flip-flop input Ar 13 there is no longer a signal (the start pulse has already ended), changes its switching position as a result of the signal applied to the flip-flop input Ar 12. It therefore assumes the switch position corresponding to the reserve position of the central device Zl. As a result, the bus enable signal disappears from the bus enable circuit e 1. This signal, which until then had been applied to the left input of the gate circuit G 22 of the switching device U 2 , consequently also disappears here. Since the central device Z 2 is assumed to be operational and emits the monitoring signal via the monitoring current path ü2 , there is also no signal at the right input of the gate circuit G 22. Consequently, in this switching phase, there is no signal at the flip-flop input k 22 of the flip-flop K 2. - The disappearance of the bus enable signal from the output ArIl of the flip-flop Ki also has the consequence that the negation gate Gn 2 now emits a signal via its output, which reaches a monostable flip-flop M 2. This monostable flip-flop gives a start pulse via the gate circuit Gz 2 , which reaches the flip-flop input Ar 23 via the gate circuit G 21. As a result of this start pulse, the flip-flop K 2 changes its position. After it has taken the switch position corresponding to the reserve position of the central device Z 2, it now assumes the switch position corresponding to the standby position. Consequently, it emits a bus enable signal via its flip-flop input Ar 21, which reaches the gate circuits Gi 12 to Gbn2 via the bus enable circuit e2 and the exchange of information between the central device Z 2 and the individual devices H 1 up to Hn

The last-mentioned bus enable signal also reaches the central device Zl and its switching device Ui. The switching processes taking place here are the same as described above with reference to the central device Z2 and its switching device U 2 .

If a fault occurs while a central device is ready for operation, i.e. during the time it is in its operating position, a fault signal passes through a circuit st 1 or si 2 serving for fault signaling to the corresponding input of the gate circuit GiI or . Gt2. This malfunction can, among other things, affect the * 5 exchange of information with the individual devices (»plausibility check«, see below). This interference signal arrives at the input of the gate circuit G13 or G23 . As a result, a switchover is brought about in the same way as was previously described with reference to the routine switchover. - The occurrence of a fault prevents the timer from being started in the central device affected by the fault. This prevents the initiation of a routine switchover to the central device affected by the malfunction.

The monitoring of the functionality of the circuits connected to the central devices Z1 and Z2 will then be described. The functioning of the line systems L 1 and L 2 is monitored in a manner known per se with the aid of plausibility checks.

If an error occurs on one of the bus enable circuits e 1 and e 2 which simulates the bus enable signal, this prevents the next routine switch (routine equivalent switch, as described in detail above). If, in such an error case, the central device Z 2 with its time switch device Zs 2 emits its blocking pulse via the current path Λ 2/1 after the waiting time mentioned above, the flip-flop Ki changes its switch position in the manner described (the bus enable signal disappears at the flip-flop output λ 11), which, however, cannot suppress or eliminate the previously mentioned simulated bus enable signal. The error that occurred z. B. on the bus enable circuit e 1, which thus simulates the bus enable signal, causes the line system L 1 and the central device Z1 to continue to operate. This error also prevents the central device Z 2 and its line system L 2 from taking over the handling of the operation. The fact that the output of the blocking pulse by the central device Z 2 does not also lead to a change from the reserve state to the operating state is recognized by the central device Z2 by time monitoring in a manner known per se and signaled as an error

If an error occurs on the bus enable current circuit el which suppresses a bus enable signal emitted via the flip-flop output Ar 11, the gate circuits Gi 11 to Gbn 1 become impermeable to any information transmission via the line system L 1. The central device Z2 and its switchover device U 2 react to the error that has occurred in the same way as in the routine switchover described above (routine equivalent switch). At the output of the gate circuit G 22 the signal disappears in this case and the monostable multivibrator M 2 gives a start impuis via the gate circuits Gz 2 and G 21 to the flip-flop input Ar 23 of the flip-flop K 2, which thereby changes the switch position corresponding to the reserve position of the central device Z2 switches to the switch position corresponding to its operating position. Via the multivibrator output Ar 21 of the switching device U 2 , the bus enable signal is now applied to the bus enable circuit eZ. This enables the transmission of information via the line system L 2; Furthermore, a signal is given to the flip-flop input Ar 12 via the blocking input S1 of the switching device U i and the gate circuit G12, whereby the flip-flop K 1 changes over to the switch position corresponding to the reserve position of the central device Z1

If an interruption occurs in the bus enable circuit el, the bus enable signal at the blocking input S2 of the switching device disappears

U2 and at the gate input of the gate Cn2 of the central device Z2. As a result, in the manner already described, the switching device U 2 is caused to carry out an equivalent circuit, as a result of which the central device Z2 assumes the operating position instead of the central device ZX; the central device Z t is in the reserve position.

The control circuits from 1 and from 2 are used to control the monitoring of the central devices Zl

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and Z2 with the help of the monitoring switching device Ü I and Ü2. For this purpose, the central devices simulate a failure of the monitoring signal at certain time intervals. In a manner not shown in detail, the central devices control via the control circuits from 1 and from 2 whether the alarm signal described arrives via the relevant control circuit when simulating a failure of the monitoring signal (via ü 1 or ü 2).

1 sheet of drawings

Claims (8)

Patent claims: 1. Circuit arrangement for telecommunications switching systems, in particular Fernsprechvermiti-I systems, with individual devices and with at least two central devices common to them and individually assigned to them Information lines, and with connecting means, by means of which the individual devices to one of the central devices can be connected via the corresponding information line, and with the central Switching devices assigned to devices, which ensure the operational readiness of the respectively assigned monitor the central device and the connection of the individual devices to only one, namely to Ensure a central device that is ready for operation and for this purpose individually with bistable multivibrators are equipped, the position of which indicates whether to the relevant central Device individual devices may or may not be switched on, characterized in that the individual devices in the switching devices provided bistable flip-flops each one an operating position of the relevant central device corresponding input and output and one of a reserve position of the relevant central Device have corresponding input that the output corresponding to the operating position in each of the switching devices not only with connecting means for connecting the individual Devices to the central device assigned to the relevant switching device, but also with the input or inputs corresponding to the reserve position in the other Unischaltungeinrichtung or provided in the other switching devices flip-flop or flip-flops is connected, and that the input corresponding to the reserve position of each of the flip-flops in the switchover device in question also has a signal current path for signaling the Ceasing of the operational readiness of a central device is connected, and that the operational position corresponding input of each of the flip-flops in the relevant switching device with a start signal current path for transmitting a start pulse to initiate the operating state of the relevant central device is connected. 2. Circuit arrangement according to claim 1, characterized in that the central devices to the switching devices assigned to them each emit a monitoring signal, if it does not produce an alarm signal for the reserve position of the relevant central device corresponding flip-flop input is issued. 3. Circuit arrangement according to claim 2, characterized in that the monitoring signal is off a continuous sequence of pulses, and that the switching device contains a monitoring switching device which emits the alarm signal if after the end of one received Pulse does not receive a next pulse within a specified time. 4. Circuit arrangement according to claim 2, characterized in that one for forwarding the Alarm signal to the one corresponding to the reserve position of the relevant central device The alarm signal circuit serving the flip-flop input has a branch via which the Alarm signal is fed to the central device. 5. Circuit arrangement according to claim 1, characterized in that the transmission of a Blocking pulse serving blocking signal current path of a switching device assigned to a central device a time switching device of a other central device is connected, and that this time switch device after a given waiting time of the other central device emits a blocking pulse. 6. Circuit arrangement according to claim 5, characterized in that the delivery of the blocking pulse depends on the operational status of a central device 7. Circuit arrangement according to claim 1, characterized in that the flip-flop output corresponding to the operating position of a switching device with the signal current path serving to transmit a start pulse to another Switching device is connected via a monostable multivibrator in such a way that if it does not occur one of the signals used to connect individual devices, a start pulse is sent to the input corresponding to the operating position of the relevant Tilt stage is delivered. 8. Circuit arrangement according to claim 1, characterized characterized in that one connected to the connecting means and one of the central devices associated connection control circuit with one end to the output of the relevant bistable multivibrator corresponding to the operating position and at its other end to the inputs of the flip-flops of the other switching devices is turned on.