DE68920580T2 - Display system with direct color mode. - Google Patents

Description

The invention relates to a display system that can be operated in both indirect and direct color mode.

The display mode most commonly used today in display systems such as personal computers or display adapters for such computers can be called "indirect color mode". In this mode of operation, pixel data contained in a display memory is used indirectly to define the chrominance and/or luminance values of the pixels to be displayed.

In a display system with a point-addressable display memory, a number of bits, typically between 1 and 8, are stored for each of the picture elements (or pixels) of a display area (corresponding, for example, to the screen of a display unit). When operating in an indirect color mode, these bits in the display memory form an index for accessing a memory cell within a reference table called a palette. The addressable memory cells in the palette contain data defining the chrominance and/or luminance for a pixel having an index addressing that memory cell in the palette. In a display system controlling a color cathode ray tube or other display unit in which colors are produced by mixing the primary colors red, green and blue, the palette entry contains chrominance and/or luminance data specifying an intensity for each of those colors. If the display unit requires analog signals to control the physical display processes, the output chrominance and/or luminance data from the palette are converted into analog signals in digital-to-analog converters (DACs) to control the display unit to control (e.g. the paint guns in a color cathode ray tube).

US Patent US-A-4,808,989 describes a display system that can be used in both indirect and direct color modes. The display system includes a digital-to-analog converter stage for converting input data words into analog values that are used to control a display unit. A screen memory is provided for storing pixel data. A palette is connected to the memory to convert pixel data from the memory into chrominance and luminance data. A multiplexer means is connected to the converter stage, the memory and the palette. When the display system is operated in an indirect color mode, the multiplexer means applies the chrominance and/or luminance data from the palette to the input of the converter stage. When the display system is operated in the direct color mode, the multiplexer means applies the pixel data from the memory to the input of the converter stage.

In an indirect color mode, up to eight bits for each pixel are typically stored in a display memory and converted into three values in a reference table (or palette) that define the intensity of the red, green, and blue elements of the pixel. In the standard indirect color mode used in many existing display adapters, such as those for the IBM PS/2 family of systems, the palette generates 6 bits each for red, green, and blue, for a total of 18 bits. If the display memory contains 8 bit planes (i.e. 8 bits per pixel), it allows the simultaneous display of up to 256 (2**8) different colors, selected from the 256K (2**18) possible different colors.

However, for some applications, specifying only 256 colors at once is not sufficient. In this case, a larger number of bits per pixel is required. If 16 bits are used, 64K (2**16) different colors can be specified at once. The ability to specify one of 64K different colors eliminates the need for a palette. In addition, using 16 bits to address a palette would make the palette too large and therefore uneconomical. If the display memory can be structured to define a sufficiently large number of bits per pixel to directly specify all desired colors, it would therefore be possible to operate the display unit in what is known as a "direct color mode," in which the values stored in the display memory control the display unit directly via the DACs.

If it is desired to operate a display system in an indirect mode as well as a direct mode, a problem arises in that a different number of bits may be generated to control the digital-to-analog converter stage in the indirect and direct color modes. Consider the case described above where 18 bits of chrominance and/or luminance data are generated for each pixel in an indirect color mode. To process these, the digital-to-analog converter stage in the indirect color mode must convert the 18 bits of chrominance and/or luminance data from the palette into analog chrominance and/or luminance values to control the display of the pixels. However, if 16 bits of chrominance and/or luminance data (i.e. 2x8 bits) in the display memory are used in a direct color mode to directly define the color and/or luminance of the pixels, two inputs remain in the converter stage that are not specified.

It is understood that the figures mentioned here are merely used to illustrate the general problem of designing a display system that can be used in both a can operate in both direct and indirect color modes and uses a different number of bits to define the chrominance and/or luminance of the pixels in the different modes.

According to the present invention there is disclosed a display system which can be operated in both indirect and direct color modes and which comprises: a digital-to-analog converter stage for converting X-bit input data words into analog values for controlling a display unit; a screen memory for storing pixel data; a palette connected to the memory for converting the pixel data from the memory into chrominance and/or luminance data; and multiplexer means connected to the converter stage, the memory and the palette for applying the chrominance and luminance data from the palette to the input of the converter stage when the display system is operating in the indirect color mode and for applying pixel data from the memory to the input of the converter stage when the display system is operating in the direct color mode; characterized in that the pixel data stored in the memory contains Y bits of chrominance and/or luminance data per pixel, where Y is less than X, and the remaining X-Y bits of the X bits fed to the converter stage when the display system is operating in direct color mode are provided by the palette depending on the pixel data stored in the memory.

The invention enables a flexible and efficient provision of direct and indirect color modes. The provision of a variety of formats for the direct color modes can be achieved by loading suitable information into the palette.

Preferably, only selected bits from the screen memory are fed to the palette as input in order to determine the bit output for the converter stage. In the event that If the display memory in a direct color mode contains 16 data bits per pixel and the converter stage requires 18 input bits, the remaining two bits may be provided by the palette. Similarly, if the converter stage requires 24 input bits, the remaining 8 bits may be provided by the palette. If the converter comprises a plurality of digital-to-analog converters, it is also possible for all of the bits for one of the converters to be provided by the palette. By loading appropriate information into the palette, the data bit on selected address bit lines of the palette can be output from corresponding output lines so that certain bits effectively "pass" the palette.

Depending on the order of the bits within a direct color word in display memory, it may be desirable in some implementations to reorder the order in which the bits are output from display memory in a direct color mode in response to a mode control signal. The goal of this reordering is to minimize the number of bits that change significance in different data formats, as will become clear from the specific examples described below.

Specific examples of display systems designed in accordance with the present invention will now be described with reference to the accompanying drawings, in which:

Fig. 1 shows a block diagram of the elements of a first example of a display system designed according to the invention;

Fig. 2 shows a block diagram of the serializer logic to be included in the display system of Fig. 1;

Fig. 3 shows a block diagram of a circuit for reformatting data in the display system according to claim 1 ;

Fig. 4 shows a block diagram of a circuit for further reformatting of data;

Fig. 5 shows a block diagram of the elements of a second example of a display system designed according to the invention; and

Fig. 6 shows a block diagram of a data station into which the elements from Fig. 1 or Fig. 5 can be integrated.

The detailed examples of display systems designed in accordance with the present invention are described here in terms of display adapters installed in a terminal such as that shown in Fig. 6. It is to be noted, however, that the term "display system" as used in the claims is not limited to a display adapter, but includes any system capable of displaying information. Thus, a "display system" is to be understood to include both a display adapter supplied as an add-on card for an existing computer such as the terminal shown in Fig. 1, and a complete computer system.

Fig. 1 is a block diagram of the elements of a first example of a display system designed in accordance with the invention. Illustrated in Fig. 1 are a screen memory 20, a color reference table or palette 22, a digital-to-analog converter stage comprising three digital-to-analog converters (DACs) 24, 26, 28, control logic 30, and a plurality of multiplexers (MPX) and connections. For the sake of clarity and ease of explanation, only the functional features which are essential for understanding are shown in Fig. 1. essential to how the present invention is implemented.

The display memory 20 is a point addressable display memory with a serializer to enable the memory to be configured to store a plurality of bits for each of the picture elements (or pixels) of the display area for the connected display unit (not shown). In this case, the display unit is assumed to be a color cathode ray tube unit. The palette 22 has eight address inputs (0-7) resulting in 256 addressable memory cells. Each addressable memory cell contains 24 bits of color information. The three DACs 24, 26, 28 each receive eight bits of digital input information at inputs 0 through 7 and produce an analog output signal which is used to control the display unit. DAU 24 generates a signal SB to control the blue intensity, DAU 26 generates a signal SR to control the red intensity, and DAU 28 generates a signal 5G to control the green intensity.

The display system can operate in either an indirect color mode or a direct color mode under the control of the control logic 30. To set the display system to operate in an indirect color mode, the control logic outputs a signal on line 32 which causes the multiplexers 34, 36 and 38 to select inputs to the multiplexers designated by the letter "I" and causes the display memory serializer 20 to output eight bits on each access.

Data is read from the screen memory 20 via a 16-bit data bus 40. In an indirect color mode, only eight of the data lines on the bus are used, while in the direct color mode, all 16 bits on the data bus 40 are used.

Figure 2 illustrates the logic of the serializer, which is installed in a 32-bit display memory 20 to form either two consecutive 16-bit pixels (memory bits 0-15, followed by memory bits 16-31) in a direct color mode, or four consecutive 8-bit pixels (memory bits 0-7, then bits 8-15, then bits 16-23, and finally 24-31) in an indirect color mode. The data appears from memory on lines B0-B31. Selected bit pairs are either passed straight through the multiplexers M0-M7 in a direct mode or exchanged by the multiplexers M0-M7 in an indirect mode. The hourglass symbol in the multiplexers represents either parallel, straight through paths (=) in a direct mode or crossed paths (x) in an indirect mode. The data on the lines to the right of the multiplexers is loaded into the shift registers 50-57 as shown in the figure and from there shifted to lines 0-15 of data bus 40. In an indirect mode, only data lines 0 through 7 are used, while in direct mode, data lines 0 through 15 are used. Note that Fig. 2 does not show individual lines to the multiplexers M0-M7 and the shift registers 50-57 for control signals derived from the control line 32 of Fig. 1 for clarity.

The operation of the display system in an indirect mode will now be explained with reference to Fig. 1. To set the display system to operate in an indirect color mode, the control logic outputs an appropriate signal on line 32 which causes multiplexers 34, 36 and 38 to select inputs to the multiplexers designated by the letter "I" and sets the serializer in Fig. 2 to output eight bits of data per pixel from the display memory 20 on lines 0 through 7 of data bus 40. Bits 0-4 from each group of eight bits are passed directly to the palette, and bits 5-7 of each group are passed to the palette via multiplexer 34. and point to specific memory cells of the palette. Each indexed memory cell of the palette in turn yields 24 bits defining chrominance and/or luminance data for that pixel in the form of three eight-bit intensity values for each of the primary colors blue, red and green. These eight-bit groups are channeled through the paths shown in Fig. 1, either directly to the appropriate DACs at palette output bits B0-B7, or through multiplexers 36 and 38 at palette output bits R0-R7 and G0-G7, respectively. The reasons for these differences will become clear when the operation of the direct mode is explained.

In indirect mode, the data in the display memory forms indexes for each pixel to access a special memory cell in the palette that stores data defining the chrominance and/or luminance appropriate for that pixel. Since a color cathode ray tube (CRT) is used as the display unit in this case, this chrominance and/or luminance data is translated by the DACs into corresponding signals to control the blue, red and green color guns of the CRT.

As mentioned above, specifying 256 colors simultaneously may not be sufficient for some applications. Therefore, the display system of Fig. 1 also supports a direct color mode. To set the display system to a direct color mode, the control logic outputs an appropriate signal on line 32 which causes multiplexers 34, 36 and 38 to select inputs to the multiplexers designated by the letter "D" and which sets the serializer of Fig. 2 to output sixteen bits of data per pixel from display memory 20 on lines 0 through 15 of data bus 40. In a direct mode, the sixteen bits of data per pixel in display memory directly define the chrominance and/or luminance values for the pixel and should generally be fed directly to the DACs. However, it is apparent that with sixteen bits cannot simply define the state of all 24 inputs to the three 8-bit DACs 24, 26 and 28.

First, the question arises as to how to divide the available sixteen bits among the three primary colors if more than eight bits are not allocated to any of the color DACs. Two formats for such allocation are described below. In the first format, 6 bits are allocated to the color green, 5 bits to the color red, and 5 bits to the color blue; this format is referred to as the 6-5-5 format. In the second format, 6 bits are allocated to the color green, 6 bits to the color red, and 4 bits to the color blue; this format is referred to as the 6-6-4 format. These allocations are derived from the fact that the eye can perceive subtler changes in the intensity of green than in that of red, and subtler changes in the intensity of red than in that of blue; For this reason, fewer bits need to be allocated to the color blue than to the color red, and fewer bits need to be allocated to the color red than to the color green.

However, the problem remains what to do with the unused input(s) of an 8-bit DAC when only 4, 5 or 6 bits are available to drive it. One solution would be to leave the unused bits permanently unused. Another solution would be to wire them to some of the other bits, or they could be turned on when any of the other bits are turned on. These solutions each have their own advantages and disadvantages, and each might be preferred in certain circumstances. However, choosing a single solution would be detrimental to flexibility. However, in a display system designed in accordance with the invention, the disadvantages of a rigid, inflexible approach are not present in that the palette is used to provide the missing bits. By loading appropriate information into the palette and using At least some of the data bits from the screen memory for addressing the palette can provide the additional bits in a very flexible manner.

Table 1 illustrates an allocation of the green, red and blue bits in a 16-bit word for each of the two formats for a direct color mode. Table 1 is found at the end of this description and relates to the example of a display system according to the invention illustrated in Figure 1. The two formats refer to the significance of the bits in the 16-bit word. Each 16-bit data word specifies the color and/or chrominance of a pixel and is fed from the display memory in either a 6-6-4 format or a 6-5-5 format. Considering that eight bits must be fed into each of the blue, red and green DACs, this means that for the 6-6-4 format, 2 additional bits must be generated for green, 2 additional bits for red and 4 additional bits for blue. Similarly, for the 6-5-5 format, 2 additional bits for green, 3 additional bits for red and 3 additional bits for blue must be generated.

From Table 1 it can be seen that for the assignment of the specified bits only bits 4 to 0 of the 16-bit word change their value between the two formats. These bits 4 to 0 of the 16-bit word are forwarded directly to inputs 4-0 of palette 32 and form part of the address there. The remaining palette address inputs are supplied via multiplexer 34.

The data that must be stored in the palette to generate the missing bits depends on the effect that is to be achieved with them. The data is stored in the palette via the data bus 23. At this point it is useful to explain the philosophy of expansion to generate the missing bits in more detail.

The simplest solution would be to keep the missing bits at a constant value. However, if this value is non-zero, the DAC will not be able to produce a zero output and it will be impossible to darken the screen completely. Nevertheless, some screens can achieve a level of dimming that is in practice indistinguishable from black, so in such cases a constant non-zero value for the missing bits may be acceptable. On the other hand, if the value is zero, the DAC will not be able to achieve full output and thus maximum intensity will not be achievable. If the extra bits are always set to zero, it means that it is possible to make all three DACs produce the same output while their inputs pass through all the stages available in the DAC, allocating the smallest number of bits. For example, data in 6-5-5 format would be effectively converted to 5-5-5 format by always setting the low order data bit for green to zero, and therefore the three low order bits of all three DACs are always zero and can then remain graded together. One advantage of this is that the grays will then be monochrome. With other methods of handling the missing bits, the DACs do not remain exactly graded together and the grays are then slightly colored. Another advantage is that all the levels in the DAC output are the same size. If the missing bits are always set to 1, this means that full output is achievable and that the grays are monochrome.

If it is necessary for the DACs to achieve both zero output and full output, the extra DAC bits must be switched to non-zero for some values of the DAC inputs. In this case, some stages in the DAC output are larger than most other stages. A good candidate for an extra large stage is the stage from zero to the lowest non-zero value, since this stage is already limited in terms of percentage intensity increase is already very large, and since a larger step at this point allows some compensation for the gamma exponent behavior of the cathode ray tube.

In practice, there are therefore three plausible methods to generate the data for the additional bits.

1. The additional bits are always a constant.

2. The additional bits are gradually turned on as the value of the other bits increases.

3. The additional bits are all turned on when any of the other bits are turned on.

If the extra bits are stored in the palette, it is easy to provide a constant value for them, since no direct color data bits affect this value.

To turn on the extra bits one at a time, a reasonable approximation is effectively to connect the extra bits to the most significant direct color data bits of the same color in the same order of significance. This gives a very close approximation to having as even a distribution of the extra stages as possible between zero and full DAC output power. The extra bits for green would be connected to the direct color data bits 15:14, and the extra bits for red would be connected to the direct color data bits 9:7 in 6-5-5 format and to the 9:8 bits in 6-6-4 format.

To turn on the additional bits when any of the other bits are on, the OR of the direct color data bits 15:10 is needed for the additional bits for green. Since bits 15:14 are already needed to affect the generation of the additional bits for green, the OR of bits 13:10 is only needed. Similarly, the OR of bits 6:5 is only needed since the direct color data bits 9:7 are already needed to affect the generation of the missing bits for red, and since the direct color data bit 4 is already required by the additional bit generation circuits for the blue bits.

Thus, ideally the following direct color data bits are required by the overhead bit generation logic 15, 14, OR of 13:10, 9, 8, 7, OR of 6:5, 4, 3, 2, 1, 0. This is 12 bits in total. Seven of these bits can be used to address the palette. The three missing red DAC bits can be driven from the red palette output bits 2:0 or 6:4 through a two-to-one multiplexer, using another of the 12 bits to control that multiplexer. The two missing green DAC bits can be driven from the green palette output bits 1:0 or 3:2 or 5:4 or 7:6 through a four-to-one multiplexer, using two more of the 12 bits to drive that multiplexer. In this way, it is possible to find a use for only 10 of the 12 bits, and so a compromise must be made in the available options to reduce the number of bits used by the extra bit generation logic from 12 to 10.

The recommended compromise is to change what is provided to allow the extra bits to be turned on sequentially. Rather than being linked to a high-order bit, the least significant extra bit is turned on when any of the other bits are on. This results in very little distortion of the chosen approximation and instead a small CRT gamma correction is performed. With this compromise, the following direct color data bits are required by the extra bit generation logic 15, OR of 14:10, 9, 8, OR of 7:5, 4, 3, 2, 1, 0. This is the desired total of 10 bits. Fig. 1 shows an arrangement in which the extra bits are generated using the OR gates 46, 48, the palette 22, the multiplexers 42 and 44, the D inputs to the multiplexers 34, 36 and 38 and the various connecting lines are generated in this way.

The following equations define how the data to be loaded into the palette is generated to achieve each of the three approximation methods in each of the two formats. Note that the data for the green section is independent of the address, but the data for the other sections is dependent on the address of the memory cell loaded. In the following, 'hg' represents the two constant green bits, 'sr' represents the two constant red bits, 'edcb' represents the four constant blue bits, and 'tsr' represents the three constant red bits.

For data format 6-6-4:

For constant missing bits:

GREEN(7:0) = 'hghghghg'b

RED(6) = ADDRESS(4)

ROT(5:4) = 'sr'b

RED(2) = ADDRESS(4)

R0T(1:0) = 'sr'b

BLUE(7:4) = ADDRESS(3:0)

BLUE(3:0) = 'edcb'b

For an evenly distributed approach:

GREEN(7:0) - '11110100'b

RED(6) = ADDRESS(4)

RED(5) = ADDRESS(6)

RED(4) - '1'b

RED(2) = ADDRESS(4)

RED(1) = ADDRESS(6)

RED(0) = OR of ADDRESS(6:4)

BLUE(7:4) = ADDRESS(3:0)

BLUE(3:1) = ADDRESS(3:1)

BLUE(0) = OR of ADDRESS(3:0)

For an approximation with gamma correction:

GREEN(7:0) - '11111100'b

RED(6) = ADDRESS(4)

RED(5:4) - '11'b

RED(2) = ADDRESS(4)

RED(1) = OR of ADDRESS(6:4)

RED(0) = OR of ADDRESS(6:4)

BLUE(7:4) = ADDRESS(3:0)

BLUE(3) = OR of ADDRESS(3:0)

BLUE(2) = OR of ADDRESS(3:0)

BLUE(1) = OR of ADDRESS(3:0)

BLUE(0) = OR of ADDRESS(3:0)

For the data format 6-5-5:

For constant missing bits:

GREEN(7:0) - 'hghghghg'b

RED(6:4) - 'tsr'b

RED(2:0) - 'tsr'b

BLUE(7:3) = ADDRESS(4:0)

BLUE(2:0) - 'dcb'b

For an evenly distributed approach:

GREEN(7:0) - '11110100'b

RED(6) = ADDRESS(6)

RED(5) = ADDRESS(S)

RED(4) - '1'b

RED(2) = ADDRESS(6)

RED(1) = ADDRESS(5)

RED(0) = OR of ADDRESS(6:5)

BLUE(7:3) = ADDRESS(4:0)

BLUE(2:1) = ADDRESS(4:3)

BLUE(0) = OR of ADDRESS(4:0)

For an approximation with gamma correction:

GREEN(7:0) - '11111100'b

RED(6:4) - '111'b

RED(2) = OR of ADDRESS(6:4)

RED(1) - OR from ADDRESS(6:4)

RED(0) - OR from ADDRESS(6:4)

BLUE(7:3) - ADDRESS(4:0)

BLUE(3) - OR from ADDRESS(4:0)

BLUE(2) - OR from ADDRESS(4:0)

BLUE(1) - OR from ADDRESS(4:0)

BLUE(0) = OR of ADDRESS(4:0)

In Table 1, it is assumed that the colors are stored in the order green, red, blue (GRB). If the data in the display memory 20 were stored in the order RGB instead of GRB as in Table 1, much more than just bits 4-0 would have variable significance, since all of the green bits would change position. On the other hand, if the colors are to be assigned in the order RGB, a mode control bit can be used to indicate whether the data is in 5-6-5 or 6-6-4 format. According to the value of this control bit, it is possible to modify the order of direct color data output from the display memory so that the order is as shown in Table 1. Essentially the same display system as illustrated in Figure 1 could then be used.

Fig. 3 illustrates a circuit that could be incorporated into the display system of Fig. 1 to modify the order of direct color output from the display memory when stored in RGB format. This circuit can be incorporated either into the display memory 40 adjacent to the serializer in Fig. 2, or into the data bus 40 which is external to the display memory. The numbers 0 through 15 in the column headed "MW" in Fig. 3 on the left identify lines 0 through 15 of data bus 40 as output from the shift registers S0.

to S7 of the serializer. The two reference columns to the right of the column headed MW indicate the significance of the bits for each of the lines 1 to 15 in the 5-6-5 and 6-6-4 modes, respectively, as indicated by the headers of these columns. As shown in Fig. 3, a multiplexer MPX1 is connected to certain data lines. Depending on the state of a format mode signal indicating either a 5-6-5 or a 6-6-4 format and transmitted over a control line C1 from the control logic 30 of Fig. 1, the multiplexer selects either the lines on the first multiplexer port A for a 5-6-5 format or the lines on the second multiplexer port B for a 6-6-4 format. The numbers 0 through 15 in the column headed "DCW" at the top right of Fig. 3 represent lines 0 through 15 of data bus 40 which extend to other circuit elements of Fig. 1. The two reference columns to the left of the column headed DCW indicate the significance of the bits for each of lines 1 through 15 in the 5-6-5 and 6-6-4 modes, respectively, as shown in the header for these columns. It will be seen below that the significance of the data in these last two columns corresponds to the significance for the respective lines illustrated in Table 1.

This approach could also be used to further reduce the number of bits that change significance between formats, but this is not possible in the particular embodiment of Figure 1, which is designed to operate according to Table 1. Figure 4 illustrates this in the form of a circuit in which the data is regrouped so that only one bit changes significance between the 5-6-5 and 6-6-4 formats. Table 2 illustrates the data produced by the circuit of Figure 4 so that it can be compared with Table 1. Table 2, like Table 1, is at the end of this specification.

Fig. 5 shows a schematic block diagram of a section of a second example of a display system according to of the present invention, which is based on three 6-bit instead of three 8-bit DACs. The structure and operation of the display system from Fig. 5 are essentially the same as the system shown in Fig. 1. However, there are differences due to the reduced number of bits required to control the DACs. Here too, for reasons of clarity and better comprehensibility, only those functional features of the display system are shown that are essential for understanding how the present invention is implemented.

The display memory 20 is a point-addressable display memory with a serializer so that a large number of bits per pixel can be stored in it. Palette 22 has eight address inputs (0-7) giving 256 addressable memory cells. Each addressable memory cell contains 18 bits of color information. The three 6-bit DACs 24, 26, 28 each receive 6 bits of digital input information via inputs 0 through 5 and generate analog output signals SB, SR, SG to control the display unit. The control logic 30 controls operation in either an indirect color mode or a direct color mode.

Data is read from the display memory 20 via a 16-bit data bus 40. In an indirect color mode, only eight of the data lines on the bus are used, while in the direct color mode, all 16 bits on the data bus 40 are used. Serializer logic such as that shown in Fig. 2 is integrated into the display memory 20 to convert the data read on the data bus 40 into a bit-serial form.

The following explains how the display system of Fig. 5 is operated in an indirect mode. To set the display system to an indirect color mode, the control logic outputs an appropriate signal on line 32 which causes multiplexers 34, 36 and 38 to select inputs to the multiplexers designated by the letter "I", and which sets the serializer in Fig. 2 to output eight bits of data per pixel from display memory 20 on lines 0 through 7 of data bus 40. Bits 0-4 from each group of eight bits are passed directly to the palette, and bits 5-7 from each group are passed through multiplexer 34 to the palette where they index specific memory cells of the palette. Each indexed memory cell of the palette results in eighteen bits defining chrominance and/or luminance data for that pixel in the form of three 6-bit intensity values for each of the primary colors blue, red and green. These 6-bit groups are channeled along the paths shown in Fig. 1, either directly to the appropriate DACs at palette output bits B0-B5 and R0, or through multiplexers 36 and 38 at palette output bits Rl-RS and G0-G5, respectively.

The following explains how the display system of Fig. 5 is operated in a direct mode. To set the display system to a direct color mode, the control logic outputs an appropriate signal on line 32 which causes multiplexers 341 36 and 38 to select inputs to the multiplexers designated by the letter "D" and which sets the serializer of Fig. 2 to output sixteen bits of data per pixel from display memory 20 on lines 0 through 15 of data bus 40. In a direct mode, the sixteen bits of data per pixel in display memory directly define the chrominance and/or luminance values for the pixel and are therefore, in principle, intended for direct input to the DACs. Although the DACs only require 18 bits to control them instead of 24 bits in the example in Fig. 1, sixteen bits are still not sufficient to define the state of all inputs to the three 6-bit DACs 24, 26 and 28.

Table 3 illustrates, for a direct color mode, an allocation of the green, red and blue bits in a 16-bit word for the same two formats described with reference to Fig. 1 discussed. Table 3 is included at the end of this specification and relates to the example of a display system according to the invention illustrated in Fig. 5. The two formats refer to the significance of the bits within the 16-bit word. Each 16-bit data word specifies the color and/or chrominance of a pixel and is fed from the display memory which is organized in either a 6-6-4 format (6 green bits - 6 red bits - 4 blue bits) or a 6-5-5 format (6 green bits - 5 red bits - 5 blue bits). As in the mapping of Table 1 for the example of Figure 1, only bits 4 through 0 of the 16-bit word change significance between the two mapping formats in Table 3. In order for the palette to be used to determine the mode of operation, bits 4 through 0 of the 16-bit word are routed to inputs 4 through 0 of input port "D" to the multiplexer 34. In direct color mode, these inputs are routed to the appropriately numbered outputs of the multiplexer and from there to the appropriately numbered inputs to the palette where they form part of the address.

In the embodiment of the invention illustrated in Figure 5, for the assignment of Table 3, the expansion to 6 blue bits to control the DACs is performed from the 5 or 4 blue bits of the data word for the 6-5-5 format and the 6-6-4 format according to the data stored in the palette. This is done because all of the blue bits in the 16-bit word address the palette. Although bits 5-2 to the blue DAC could be fetched directly from bits of the 16-bit word, a multiplexer is saved by using the output of the palette for all of the blue DAC bits.

In the case of extending the red data for the 6-5-5 format, an additional red bit (R0) must be generated in addition to the one blue bit (B0) that is required to be generated. There are three practical methods that are similar to those which were discussed with reference to Fig. 1 above. These methods are:

1. The additional bit is always a constant.

2. The additional bit is linked to the higher-order bit.

3. The additional bit is turned on when any of the other bits is turned on.

To allow a selection from these three methods, the high order red bit (R5) and the OR of the remaining red bits (R4-R1) from the 16-bit data word form part of the palette address. In this case, therefore, a total of 7 bits are needed to address the palette. This means that half of the palette memory cells are needed to support the direct color mode. The other half of the memory cells are available for other uses, such as defining the color of the border around the display area of the screen. In this case, the high order palette address bit could be the opposite of the high order bit of the color index for the border.

Therefore, in direct color mode, the three 6-bit DACs 24, 26 and 28 are controlled as described below. Bits 15 through 10 of the direct color data are passed through multiplexer 38 to drive bits 5 through 0 of the green DAC 28. Bits 9 through 5 of the direct color data are passed through multiplexer 36 to drive bits 5 through 1 of the red DAC 26; with the red DAC bit 0 being received from the same output (R0) of the palette that is used for indirect data. All 6 bits (5-0) of the blue DAC are controlled by the same palette outputs (BS-B0) that are used for indirect data. All of these connections are shown in Fig. 1.

For operation in 6-4-4 format, the pallet is loaded with data in a conventional manner via the data bus 23, so that the red bit 0 of the palette's R0 output corresponds to its address bit 4, so that the direct data bit 9 is effectively passed to the bit 0 input of the red DAC 26. The blue part of the palette is loaded to allow any desired translation from 4 to 6 bits.

In the 6-5-5 format, the palette still receives all of the blue direct color bits, and so any translation from 5 to 6 bits can be performed. In addition, the palette receives enough information about the red direct color bits to perform a meaningful extension from 5 to 6 bits.

It can be seen that direct color data can be accepted in either 6-5-5 or 6-6-4 format and the data can be appropriately extended by using the palette. The equations below define how the data to be loaded into the palette is generated to provide the appropriate extensions for the two data formats (664 and 655) for 6-bit DACs. For each of the data formats, three approximation methods for the missing bits (constant, gamma correction and uniform distribution) are illustrated.

The palette data bits are numbered 5:0, with 0 being the least significant bit. All six blue bits are relevant. Only bit 0 of the red data is relevant, and none of the green bits are relevant.

In many cases, the data to be loaded into a particular memory cell depends on the address of the memory cell. The required address bits are assigned the numbers 6:0, where 0 is the least significant bit. In the constant approximations, 'cb'b and 'r'b represent the desired constant values for the missing blue and red bits, respectively.

Data format 6-6-4:

Constant approach:

Blue(5:2) = Address(3:0)

Blue(1:0) = 'cb'b

Red(0) = Address(4)

Approximation with gamma correction:

Blue(5:2) = Address(3:0)

Blue(1) = OR of Address(3,2,1,0)

Blue(0) = OR of Address(3,2,1,0)

Red(0) = Address(4)

Uniform distribution approach:

Blue(5:2) = Address(3:0)

Blue(1) = Address(3)

Blue(0) = Address(2)

Red(0) = Address(4)

Data format 6-5-5:

Constant approach:

Blue(5:1) = Address(4:0)

Blue(0) = 'b'b

Red(0) = 'r'b

Approximation with gamma correction:

Blue(5:1) = Address(4:0)

Blue(1) = Address(4)

Red(0) = Address(6)

As explained in the example of Fig. 1, many more than bits 4 to 0 of the data word would have variable significance if the color data were stored in the display memory 20 in the RGB order instead of in the GRB order as shown in Table 3. However, if the colors are to be assigned in the RGB order as in the example of Fig. 1, a Mode control bit may be used to indicate whether the data is in 5-6-5 or 6-6-4 format. Circuits similar to that shown in Figure 3 and responsive to this mode control bit could be used to reformat the data word output from the serializer of Figure 2 into the order shown in Table 3.

Again, this approach could be used to further reduce the number of bits that change significance between formats for a display system with three 6-bit DACs, but not with the particular embodiment of Figure 5, which is designed to operate according to Table 3. A circuit similar to that shown in Figure 4 could be used to reorder the data so that only one bit changes significance between the 5-6-5 and 6-6-4 formats. Table 4 illustrates a data format suitable for use with three 6-bit DACs in which only one bit changes significance. Table 4 is listed at the end of this description.

Fig. 6 illustrates a data station into which the elements described in connection with the previous figures can be integrated. The data station comprises a central processing unit 80 in the form of a conventional microprocessor and a number of other units including a display adapter 90 connected via a system bus 92. Connected to the system bus are a random access memory (RAM) 82 and a read only memory 81. An I/O adapter 83 is provided by which the system bus can be connected to peripheral units 84 such as disk units. A communications adapter 85 is also provided for connecting the data station to external processors (e.g. a host computer). A keyboard 87 is connected to the system bus via a keyboard adapter 86. The display adapter 90 is used to control the display of data on a display unit 94. During operation, the CPU issues commands to the display adapter over the system bus to instruct it to perform display processing tasks.

The elements described with reference to previous Figures 1 or 5 fit into the display adapter 90 of Figure 1. In addition to the elements shown, the display adapter contains other elements such as memory logic for controlling storage in the display memory 20 of data received from the bus 92. The memory logic may be conventional and is not relevant to the understanding of the present invention. Therefore, the memory logic will not be described further here. The circuits shown in Figures 1 or 5 generate the green, red and blue color signals SB, SR and SG which control a display unit, in this case a color cathode ray tube.

Although specific examples of the present invention are described here, the invention disclosed in the claims is not limited to these specific examples.

For example, it will be appreciated that although the examples described are intended for use in a display unit with a cathode ray tube that requires blue, red and green color information, a different combination of colors could be generated for other types of devices. For example, if the display unit were an ink jet printer, signals for each of the blue, red and yellow colors could be generated.

Furthermore, in the specific embodiments, data is read from the display memory 20 via a 16-bit data bus 40. In an indirect color mode, only eight of the data lines on the bus are used, while in the direct color mode, all 16 bits on the data bus 40 are used. However, other implementations are possible, for example two buses, an 8-bit bus for indirect mode data and a 16-bit bus for direct mode data. TABLES Bit number assignment TABLE 1 TABLE 2 TABLE 3 TABLE 4

Claims (7)

1. A display system operable in both indirect and direct color modes, the display system comprising: a digital-to-analog converter stage (24, 26, 28; 64, 66, 68) for converting X-bit input data words into analog values for controlling a display unit; a screen memory (20) for storing pixel data; a palette (22; 62) connected to the memory for converting pixel data from the memory into chrominance and/or luminance data; and multiplexer means (36, 38; 76, 78) connected to the converter stage, the memory and the palette for applying the chrominance and/or luminance data from the palette to the input of the converter stage when the display system is operating in the indirect color mode and for applying the pixel data from the memory to the input of the converter stage when the display system is operating in the direct color mode; characterized in that the pixel data stored in the memory contain Y bits of chrominance and/or luminance data per pixel, where y is less than x, and the remaining X-Y bits of the X-bit input to the converter stage are provided by the palette when the display system is operating in direct color mode depending on the pixel data stored in the memory. 2. A display system according to claim 1, wherein in the direct color mode selected bits from the display memory are fed as input to the palette to determine therefrom the data bit output to the converter stage. 3. A display system as disclosed in claim 1 or 2, in which the converter comprises a plurality of digital-to-analog converters and in a direct color mode all bits for one (24, 64) of the converters are provided from the palette. 4. A display system according to any preceding claim, in which the converter stage comprises three 6-bit digital-to-analog converters (64, 66, 68), i.e. one for each primary color (R, G, B) of the display unit. 5. A display system according to one of the preceding claims 1 to 3, in which the converter stage comprises three 8-bit digital-to-analog converters (24, 26, 28), i.e. one for each primary color (R, G, B) of the display unit. 6. A display system according to any preceding claim, in which the display memory contains 16 bits of chrominance and/or luminance data per pixel in direct color mode. 7. A display system as claimed in any preceding claim, in which the order of bit output from the display memory in a direct color mode is rearranged in response to a mode control signal.