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FR2620839B2 - BINARY CALCULATION DEVICE WITH IMPROVED INPUTS - Google Patents
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FR2620839B2 - BINARY CALCULATION DEVICE WITH IMPROVED INPUTS - Google Patents

BINARY CALCULATION DEVICE WITH IMPROVED INPUTS

Info

Publication number
FR2620839B2
FR2620839B2 FR8713146A FR8713146A FR2620839B2 FR 2620839 B2 FR2620839 B2 FR 2620839B2 FR 8713146 A FR8713146 A FR 8713146A FR 8713146 A FR8713146 A FR 8713146A FR 2620839 B2 FR2620839 B2 FR 2620839B2
Authority
FR
France
Prior art keywords
calculation device
binary calculation
improved inputs
inputs
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR8713146A
Other languages
French (fr)
Other versions
FR2620839A2 (en
Inventor
Hedi Hmida
Pierre Duhamel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gouvernement de la Republique Francaise
Original Assignee
Gouvernement de la Republique Francaise
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR8703758A external-priority patent/FR2612660B1/en
Application filed by Gouvernement de la Republique Francaise filed Critical Gouvernement de la Republique Francaise
Priority to FR8713146A priority Critical patent/FR2620839B2/en
Priority to EP88402383A priority patent/EP0309348B1/en
Priority to DE88402383T priority patent/DE3880409T2/en
Priority to JP63238613A priority patent/JPH0289130A/en
Priority to US07/248,089 priority patent/US4985862A/en
Publication of FR2620839A2 publication Critical patent/FR2620839A2/en
Priority to US07/578,201 priority patent/US5095455A/en
Publication of FR2620839B2 publication Critical patent/FR2620839B2/en
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4812—Multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
FR8713146A 1987-03-18 1987-09-23 BINARY CALCULATION DEVICE WITH IMPROVED INPUTS Expired - Lifetime FR2620839B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR8713146A FR2620839B2 (en) 1987-03-18 1987-09-23 BINARY CALCULATION DEVICE WITH IMPROVED INPUTS
EP88402383A EP0309348B1 (en) 1987-09-23 1988-09-21 Binary addition and multiplication device
DE88402383T DE3880409T2 (en) 1987-09-23 1988-09-21 Binary addition and multiplication device.
JP63238613A JPH0289130A (en) 1987-09-23 1988-09-22 binary calculation circuit
US07/248,089 US4985862A (en) 1987-09-23 1988-09-23 Binary adder circuit with improved inputs
US07/578,201 US5095455A (en) 1987-09-23 1990-09-06 Binary multiplier circuit with improved inputs

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8703758A FR2612660B1 (en) 1987-03-18 1987-03-18 BINARY CALCULATION DEVICE
FR8713146A FR2620839B2 (en) 1987-03-18 1987-09-23 BINARY CALCULATION DEVICE WITH IMPROVED INPUTS

Publications (2)

Publication Number Publication Date
FR2620839A2 FR2620839A2 (en) 1989-03-24
FR2620839B2 true FR2620839B2 (en) 1991-01-18

Family

ID=26225851

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8713146A Expired - Lifetime FR2620839B2 (en) 1987-03-18 1987-09-23 BINARY CALCULATION DEVICE WITH IMPROVED INPUTS

Country Status (1)

Country Link
FR (1) FR2620839B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3767906A (en) * 1972-01-21 1973-10-23 Rca Corp Multifunction full adder
JPS58211252A (en) * 1982-06-03 1983-12-08 Toshiba Corp Total adder

Also Published As

Publication number Publication date
FR2620839A2 (en) 1989-03-24

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Legal Events

Date Code Title Description
TP Transmission of property