FI71437B - DIGITAL SANNOLIKHETSKORRELOMETER - Google Patents

Description

71437

Digital probability correlator

The present invention relates to digital computers and more particularly to digital probability 2 autumn correlators.

The present invention can be used in the study and control of stochastic processes, for example in hydrometeorology, biology, telecommunications, metallurgy, the textile industry, etc.

20 The processing of stochastic data involves the calculation of various statistical properties such as mathematical expectation, autocorrelation and cross-correlation function, etc. The above properties make it possible to estimate the amplitude, frequency and phase parameters of the stochastic processes, the interdependencies of the processes, etc.

The computational procedures used to determine statistical properties, such as correlation functions, involve a large number of similar arithmetic operations - multiplications and additions. For example, to compute a correlation function of 64 ordinate values of a stochastic process with 10,000 ordinates, it is necessary to perform an addition of about 64,000 times. These operations, performed sequentially with multi-digit numbers of 25 to 1a, take a long time (several hours when using general purpose computers), which makes it difficult to use such an important procedure in the study of stochastic processes as a rapid means of analysis.

The principle of the statistical test method (Monte-Carlo method) can be successfully used to reduce the time required to process stochastic data.

Several special calculators are known which use the principle of probability coding, which involves converting digital information into a probability form and performing various arithmetic operations on digital signals whose statistical properties are determined by the values of the converted data.

5 The main role in probability coding is that it can reduce the number of word numbers from what they are in the original words by replacing all or part of the word numbers with a single number. In probability coding, the original multi-digit word is compared to a random number, and a single-digit number (zero or one) is formed based on the comparison result.

To perform multiplication operations, digital correlators operating on the principle of probability coding have two reference units, a random number generator and a logic circuit, the inputs of which are connected to the outputs of the reference unit. The first inputs of the comparison units are supplied with digital signals to be multiplied, while the second inputs are supplied with digital signals 2o of the outputs of the random number generator. As a result, the logic circuit develops a binary pulse train for its output, the frequency of which is determined by the input of the signals to be multiplied. This binary pulse train is input to the input of the data battery and said battery generates a code corresponding to the value of the input.

25 Currently, the correlation function is computed using an algorithm that assumes that the stochastic process under study is a stationary ergodic centralized process. In their practical work, however, researchers are mainly concerned with decentralized stochastic processes 30. Thus, digital correlators are usually equipped with eliminations that concentrate the input data representing the process. Such an element includes an adder to which an input signal is applied to one input and the mathematical expectation value of the input signal is input to the other input.

A digital correlator is known, which comprises an adder, one input of which is connected to the output of a 3 71437 switch, the input of which selects the code of the mathematical expectation value of the stochastic process to be examined, a memory unit, the input of which is connected to the output of an adder, a random number generator ka one input is connected to the output of a random number generator and the other input is supplied with a signal determined as the difference between the ordinate values of the stochastic process under study and the mathematical expectation value of said process, a logic circuit having one input connected to the output of the reference unit circuit, and a timing unit adapted to synchronize the operation of the correlator units (cf. SIJTL's Inventor Certificate No. 705 457).

The known correlator also comprises a second comparator 15, one input of which is connected to the second output of the random number generator and the other input of which is connected to the output of the memory unit and the output of which is connected to the second input of the logic circuit.

As is well known, the implementation of a multi-digit compare-20 country capable comparison unit is a difficult problem. For example, if SN 74 and SN 54 series microcircuits manufactured by Texas Instruments, Inc. are used, then a circuit that performs a comparison of two one-byte words would comprise six SN 7400 or (SN 5400-) 25 series microcircuits and four SN 7401 - (or SN 54010-) series of integrated circuits, each encapsulated in its own housing. In addition, in such a circuit, the number code entered in the second multi-digit input of the reference unit should be inverted. This requires the use of integrated circuits with both non-inverted and inverted inputs, or the use of additional inverters, which further complicates the circuit. In modern correlators with a capacity of many bytes, the number of parts forming the reference unit becomes correspondingly larger.

35 The need to use complex 4 71437 control units comprising a number of separate components leads to a significant increase in the degree of complexity as well as the cost of the correlator circuit.

The main object of the present invention is to provide a digital probability correlator in which the comparison of the words to be told with random numbers is performed in such a way as to make at least another comparison unit unnecessary and thus simplify the correlator circuit and reduce its cost.

With this main purpose in mind, a digital probability correlator is provided comprising an adder, one input of which is connected to the output of a selector, the input of which selects the mathematical expectation code of the stochastic process under study, a memory unit, the input of which is connected to the output of an adder, a random number generator, one input connected to the output of the random number generator and the other input being supplied with a signal determined by the difference between the ordinate values of the stochastic process under study and the mathematical expectation value of said stochastic process, the logic circuit , and a timing unit adapted to synchronize the operation of the parts of the correlator 25, in which correlator according to the invention the selector has a second input connected to the second output of the random number generator, the second input of the logic circuit is connected to the summator. en, the second input of the adder is connected to the output of a register, the input of the register-30 of which is connected to the output of the second selector circuit, the input of which selects the ordinate value of the stochastic process to be examined and the second input of which is connected to the output of the memory unit.

In such a correlator, the comparison of the numbers stored in the memory unit with the random numbers is performed by means of a subtraction count in the gutter used to centralize the process input data. This makes it possible to use only one reference unit, thus simplifying the correlator circuit and reducing its cost.

The second input of the reference unit can be connected to the output of the adder via the second register.

When using a correlator equipped with two inputs, for example to calculate a cross-correlation function, it is recommended to use a second adder that concentrates the signal input to the second input of the correlator and compares the values of this signal with random numbers. In this case, the reference unit is an adder whose one input is connected via the second register to the output of the third selector, the second input of the selector is connected via the third register to the output of this adder and the second input is supplied with ordinate values of the second stochastic process under study, the second input being connected to the output of the random number generator 20 by a fourth selector, one input of which selector is connected to the output of the random number generator and the mathematical expectation code of the second process to be examined is input to the second input, and the memory output of this sum is connected to the second input of the logic circuit 25.

Such a correlator circuit makes it possible to completely eliminate the need to use a special reference circuit, which further simplifies the correlator circuit and reduces its cost.

The invention will now be described, by way of example only, with reference to the preferred embodiments thereof, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a digital probability correlator according to an embodiment of the invention; Fig. 2 is a block diagram of a 6,71437 digital probability correlator according to a second embodiment of the invention.

In Fig. 1, the digital probability correlator comprises an adder 1, the input 2 of which is connected to the output of the selector 3, a multi-digit memory unit 4, the input 5 of which is connected to the output 5 of the adder 1, a random number generator 6, the second output 7 of which is connected to the input 8 of the comparison unit 9. the second input 10 is connected via the register 11 to the output 5 of the adder 1. The output of the comparison circuit 9 is connected to the input 13 of the logic circuit 10, the second input 15 of the logic circuit is connected to the memory number 12 output of the adder 1, while the output of the logic circuit 14 is connected to the data accumulator 16.

The selector 3 has two inputs 17 and 18. The input 17 is connected to the output of a register 19, which register is used to store the code of the mathematical expectation value of the stochastic process to be examined. The input 18 is connected to the second output 20 of the random number generator 6.

In addition, the correlator comprises a selector 21 with two inputs 22 and 23 and a register 24. The input 22 of the selector 20 is the input of the correlator. The input 23 of the selector 21 is connected to the output of the memory unit 4. The output of the selector 21 is connected to the input of the register 24, the output of the register of which is connected to the second input 25 of the adder 1.

The correlator further comprises a timing unit 26, the outputs of which are connected to the control inputs of the respective elements of the correlator.

The data battery 16 comprises a multi-digit memory unit 27, a multi-bit binary counter 28, the input 29 of which is connected to the output of the memory unit 27 and the output of which is connected to the input of the memory unit 27, the count input 30 of the counter 28 forming the data battery 16 input.

The output of counter 28 is the output of the correlator.

The memory unit 27 is made in the same way as the memory unit 4, but it has more number positions than 35 in the memory unit 4.

7 71437

The inputs 2 and 25 of the adder 1 and the output of its calculation result 5, the inputs and outputs of the selectors 3 and 21, the memory units 4 and 27, and the registers 11, 19 and 24, the outputs 7 and 20 of the random number generator 6, the outputs 8 5 and 10 of the comparison unit 9, and the input 29 and output of the counter 28 represent multi-digit inputs and outputs and consist of a plurality of digital parallel buses.

The memory unit 4 is formed from a plurality of shift registers, the inputs of which respectively form the input bus of the memory unit 10, the outputs of the shift registers form the output bus of the output bus of the memory unit 4, the interconnected control inputs forming the output of the memory unit 4.

The random number generator 6 is a known device which generates multi-digit evenly distributed random numbers of an independent series for each of its outputs.

Logic circuit 14 is an AND gate. In general, the logic circuit 14 may be more complex and comprise several logic components.

The timing circuit 26 is a device controlled by a microprogram, which generates for its control signals which are generated in a certain order, which depends on the operation algorithm of the correlator.

The digital probability correlator shown in Figure 1 is designed to calculate the autocorrelation function of the stochastic process.

Figure 2 is a block diagram of a digital probability correlator designed to calculate the cross-correlation function of two stochastic processes.

In Fig. 2, the digital probability correlator 30 comprises, in addition to the counter 1, the memory unit 4, the random number generator 6, the selectors 3 and 21, the logic circuit 14, the registers 19 and 24, the data accumulator 16 and the timing unit 26, two selectors 32 and 3 3 and three registers 34, 35 and 36. The correlation unit 9 of the corrugator-35 shown in Fig. 1 (Fig. 1) and the register 11 8 71437 are not used in the correlator shown in Fig. 2 because their functions are performed by the adder 31 and the register 35, respectively.

The second input 37 of the adder 31 is connected to the output of the selector 5 32. The second input 38 of the adder 31 is connected via a register 35 to the output of the selector 33. The second input 39 of the selector 32 is connected to the output of a register 34, which register is used to store the mathematical expectation value of the second stochastic process. The second input 10 to 40 of the selector 32 is connected to the output 7 of the random number generator 6. The second input 41 of the selector 33 represents the second input of the correlator. The second input 42 of the selector 33 is connected via a register 36 to the output 43 of the calculation result of the adder 31, the output 44 of the memory number of the adder 31 being connected to the input 13 of the logic circuit 14.

The inputs 37 and 38 of the adder 31 and the output 43 of the calculation result, as well as the inputs and outputs of the selectors 32 and 33 and the registers 34, 35 and 36, represent multi-digit inputs and outputs and consist of a plurality of digital rin-20 click buses.

In other respects, the correlator shown in Figure 2 does not differ from the correlator shown in Figure 1.

As is known, the calculation of the cross-correlation function of two stochastic processes is performed by the following formula: Np K (p) = -> (x. - m) (y. - m), (1) yx np / 1_p x 1 y 30 i = 1 where KyX (p) is the value of the "p" of the cross-correlation function computed with respect to process "x" of process "y"; 25 p is the ordinal number of the correlation function; 9 71437 N is the number of process ordinates used in the calculation; x ^ is the stochastic process "x" "i": the value of the nth ordinate; ^ is the value of the "i" th ordinate of the stochastic process "y"; i is the ordinate number of the stochastic process; mx is the mathematical expectation value of process "x"; m is the mathematical expectation value of the process "y". The autocorrelation function of a stochastic process is calculated according to the following formula: N-p is Κχχ (ρ> = · ^ y, χλ ’(xi-p'V 'u) i = 1 where K (p) is the autocorrelation function of the process" x "

X X

the value of the "p" th ordinate.

2o A correlator designed for calculating the autocorrelation function and shown in Fig. 1 operates as follows.

The coded ordinate values of the stochastic process to be examined are input to the input 22 of the selector 21 while the code of the mathematical expectation value of the stochastic process is input to the input 17 of the selector 3, which is calculated by known methods.

The calculation procedure of the autocorrelation function of the stochastic process "x" using N ordinate values returns N periods, each of which involves receiving and centering the previous ordinate value of the stochastic process, generating inputs of type (χ.-m) (x._ -m), and aggregation of said income according to formula (2).

35 Consider the operation of the correlator during the "i" period, that is, during the period in which the value of the "i" ordinate of the stochastic process "x" is processed.

At the beginning of the cycle, a command is introduced from the corresponding dose of the timing unit 26 to the control input of the memory unit 4, from which it follows that the information stored in the memory unit is transferred. When this is done, selectors 3 and 21 remain open. The memory units 4 and 27 are made so that the data transfer direction is from the input of the memory units to the input, so that at the beginning of the cycle the first group (counting the dose ot-1Q) of the memory registers of the memory unit 4 is set to zero. the data at the end will be lost.

The current ordinate-15 value x 1 of the stochastic process is written from the input 22 of the selector 21 to the register 24 and transferred to the input 25 of the adder 1 when the corresponding command is imported from the timing unit 26 to the control input of the selector 21. At the same time, the mathematical expectation value m of this stochastic process is taken from register 19 to the input of adder 1 Λ 20 2 when the corresponding command is imported into the control input of selector 3.

At the same time, when importing a command into the control input of adder 1, its mathematical expectation value is subtracted from the value of the ordinate of the stochastic process, as a result of which adder 1 develops a value of 5 in its output. code and generating the value of the ordinate shown for this stochastic process, i.e. a value equal to (xi ~ m).

The result obtained is written to the first (listed in the output) of the registers of the memory unit 4 when the command is imported into the control input of the memory unit 4 and at the same time this result is written to the register 11 and passed to the input 10 of the comparison unit 9.

The number of flip-flops of each shift register of the memory units 4 and 27 is equal to the number "q" of the coordinates of the correlation function to be computed.

11 71437 At the beginning of the "i" period (before the transfer and resetting of the first flip-flop group), the memory unit 4 contains the centered values x ^ _ ^, ^ i-2 '* · *' ^ iq 'with the number "q", so that the ordinates, having a smaller sequence number 5 are stored in those flip-flops which are placed closer to the output of the memory unit 4. Thus, after the data has been transferred in the memory unit 4 at the beginning of the "i" th period, the flip-flops of the registers of this memory unit contain the following values (from the sample to the output read-10 te Ituna): O, x. ^, ° i_2 '- ·· » ° i-q + i · The value x ^ is then written to the first flip-flop group of the memory unit 4, after which a series of sub-periods begins, during which the inputs are accumulated in the data accumulator 16.

During the first sub-period, the value x ^ is multiplied by ar-15 and the result is added to the contents of the corresponding flip-flop group of the memory unit 27.

For this purpose, the selector 21 is set to a state in which the information input to the input 23 of the selector 21 is transferred to the input of the register 24, whereby a value from the last flip-flop group of the memory unit 4 is introduced into said register 20. Simultaneously, as a result of the command introduced into the control input of the counter 28, information from the last flip-flop group (dose) of the memory unit 27 is transferred to this counter. Then, the data stored in the memory units 4 and 27 is transferred. After the transfer, the information stored in the last flip-flop group of the memory units 4 and 27 before the transfer is found in the register 24 and the counter 28, respectively, while the first flip-flop group of the memory units is set to zero.

30 Then to the numbers x. and x. which are stored in registers 11 and 24, respectively, a probability multiplication is performed. To do this, a random number obtained from the output 20 of the random number generator 6 is introduced into the input 2 of the adder 1 via the selector 3, and a subtraction command is introduced into the control input of the adder 1.

12 71 4 3 7

If the number acting on the input 25 of the adder 1 is greater than the number acting on the output 20 of the random number generator 6, then a logical one of the input 12 of the memory number 12 of the adder 1 is applied to the input 15 of the logic circuit 14, otherwise a logic zero is applied to the input 15. Similarly, if the number acting on the output 12 of the register 11 is greater than the number acting on the output 7 of the random number generator 6, then a logical one of the output of the reference unit 9 is applied to the input 13 of the logic circuit 14, otherwise a logical zero is introduced to the input 10 13. If a logical one is applied to both inputs 13 and 15 of the logic circuit 14, then a logic one of the output of the logic circuit 14 is introduced into the calculation input of the counter 28 by the command received from the timing unit 26, whereby the contents of the counter 28 increase by one. In other cases, a logic zero is applied to the input 30 of the counter 28 and the contents of the counter 28 do not change.

For greater computational accuracy, the process of comparing the numbers stored in registers 11 and 24 with random numbers in outputs 7 and 20 of random number generator 6 may be repeated several times at different numbers in outputs 7 and 20, which numbers are exchanged by importing a corresponding command from timer control unit 6 random number. In this case, the change in the contents of the counter 28 is determined by the sum of the logic signals provided by the logic circuit 14.

Thus, the correlator shown in Fig. 1 performs a probability multiplication of the centralized ordinate values of the stochastic process under study using only one comparison unit 9, and the comparison of the respective 30 ordinate values and the random number of the process is performed in adder 1.

At the end of the first sub-period, when importing a command from the timing unit 26 to the control inputs of the memory units 4 and 27, the value S._q + 1 is transferred from the register 24 to the first flip-flop group of the memory unit 35, while the contents of the counter 28 13 71 4 37 have changed by x ^ x ^ + ^ f is written to the first flip-flop group of the memory unit 27. After this, the first subsection ends.

The operating sequence of the correlator parts during the second 5 and subsequent sub-periods does not differ from the operating sequence of the first sub-period.

During the second sub-period, the values x, Λ ~, x are stored, listed from sample to output. ,. , x., x. ,, ..., ^ j__q + 3 to the flip-flop groups of the memory unit 4 while a logic signal corresponding to the probability value of the input S ^ x ^ _ 2 is applied to the calculation input 30 of the counter 10 28 and added in the counter 23 to the information available from the last memory unit 27 at the end of the first sub-period. At the end of the second sub-period, the contents of the memory unit 27 15 are shifted by one step, and the counter 23 writes to the first flip-flop group of the memory unit 27 information that has changed by x ^ x ^ _ ^ + 2. During the following sub-periods, the data in the memory units 4 and 27 are forwarded again and the value x 1 is multiplied by the following ordinate values of the stochastic process stored in the registers of the memory unit 4 in 20 order. During the last, "q", sub-period, the value x ^ is calculated. At the end of the last subsection, the memory unit 4 contains the following values (listed from sample to output); o o o. . . . ......

25 x ^, ..., x - [_ q + p ', that is, its contents are exactly the same as before the beginning of the first sub-period of the' 'i' period, while the flip-flops of the memory unit 27 contain (listed from sample to output) the values, which have changed by ar- o 2 oooo by x., xx. £ ..., xx.

J 11 i-lf l i-q + 1 30 After this, the next (i + 1) th period of correlator operation begins. During this period, the operating sequence of the correlator elements does not differ from the operating sequence of the previous or "i" period described above. At the beginning of the (i + 1) th period, the value jL + ^ of the next 14 71 4 37 ordinate of the stochastic process to be examined is introduced into the register 24 via the selector 21 35. The contents of the registers of the memory unit 4 are then transferred, with the result that the first flip-flop group of the memory unit 4 is set to zero and the value x ^ _q + 2 'is transferred to the next flip-flop group. At this point, the data stored in the last flip-flop group 4 of the memory unit 4 (value x. . Next, in the adder 1, the mathematical expectation value i-q + 1 is subtracted from the value xi + ^ and the centralized value xi + ^ is stored in the first flip-flop group of the memory unit 4.

At the end of the first sub-period of the 10th (i + 1) second period, the value $ ^ _ q + 2 from the last flip-flop group of the memory unit 4 is introduced into the register 24 while the counter 23 writes the contents of the last flip-flop group of the memory unit 27, which represents "i" during the first subperiod. number of variables. J l i-q + 1. This is followed by the values of x ... and x. , ~ multiplying each other and exporting the result of the multiplication to the calculation input of the counter 28 and adding it to the number stored in the counter 28. Thus, during the first sub-period of each period 20, the contents of the counter 28 change by a value equal to the product of the ordinate of the stochastic process and its previous ordinate, the sequence number of the previous ordinate differing from the sequence number of the last ordinate by (q-1).

During the first sub-period, the data in the memory units 4 and 27 are transferred and the contents of the counter 28 are transferred to the first flip-flop group of the memory unit 27. During the second and subsequent sub-periods, the information 30 written to the first flip-flop group of the memory unit 27 during the first sub-period does not change, but is only forwarded several times in succession until it reaches the last flip-flop group of the memory unit 27 at the end of the "q" sub-period. Thus, at the end of the first sub-period of the Nth period, the first flip-flop group of the memory unit 27 contains the result of the summing of the sum i7 71 437 and is equal to (y ^ -m). This value is written to register 36.

Thereafter, at the same time as the centered ordinate value of the process "x" is stored in the first flip-flop group of the memory unit 5 4, the selector 33 is set to the state in which the centered value y is brought by the corresponding command brought to its control input. transferred from register 36 to register 35.

The true-10 visibility multiplication of the ordinate values of stochastic processes takes place as follows.

At the beginning of the first sub-period of the "i" period, a value x is stored in register 24. , The control inputs of the selectors i-q + 1 19 and 32 are then supplied with commands that cause the random numbers to be imported from the outputs 20 and 7 of the random number generator 15 into the adder 2 input 2 and the adder 31 input 37, respectively, while the control inputs of the adder 1 and 31 are subtracted. It follows that the input 15 of the logic circuit 14 (from the memory number 12 of the adder 1) is supplied with a logical one if the value written to the re-20 register 27 is greater than the number effective at the output 20 of the random number generator 6, and a logical zero if the value is less than the random number 6 of the random number generator 6. dose 20 effective figure. Similarly, the input 13 of the logic circuit 14 (input 44 of the memory number 25 of the adder 31) is supplied with a logical one if the value ^ written to the register 35 is greater than the number acting on the output 7 of the random number generator 6, and logical zero if the value ^ is less than the value 7 of the random number generator 6 number. For greater accuracy, the comparison of the numbers stored in the registers 24 and 25 with the numbers affecting the outputs 7 and 20 of the random number generator 6 can be performed several times when the numbers affecting the outputs 7 and 20 have different values. Thus, at the end of the first sub-period 35 of the "i" period of the correlator operation, the logic circuit 14 generates a logic signal 71437 (or a sequence of logic signals) representing the centered value y1 and the centered value xi-q + 1 of the process "y". ^ er't ° las ^ un probability result.

During the following sub-periods of the “i” period, the value 5 is multiplied by the values Xp_q + 2 '° i_q + 3 ine * f which is obtained by successively passing the contents of the memory unit 4 and writing information about the last flip-flop group of the memory unit 4 to the register 21 as described above. During the last sub-period of the "i" th period, i.e. the "q" th period 10, the logic circuit 14 generates a probability input jiLx ^ for its output.

Thus, the correlator shown in Fig. 2 performs a probability multiplication of the centralized ordinate values of the two stochastic processes to calculate the cross-correlation function according to formula (1) without using special comparison units whose operations are performed by adders 1 and 31.

The values of the inputs obtained during the same sub-periods with the same sequence number of the different periods are calculated in the data accumulator 16 in the same way as described above. As a result of this summation, the data battery 16 contains values

N N N N

Σοο \ p o \ o o \ o o

Xiyi 'Xi-lyi' l_j xi-lyi '* · * i-4 + lyi' i = l i = l i = l i-1 which are proportional to the ordinate values of the cross-correlation function calculated with respect to process "x" of process "y". 3Q After the calculation, these values can be read from the data accumulator 16 and used for the graphical display of the cross-correlation function or they can be further processed in a digital computer.

i7 71 437 concentration result and which is equal to (y ^ -m). This value is written to register 36.

Thereafter, at the same time as the centered ordinate value of the process "x" is stored in the first flip-flop group of the memory unit 5 4, the selector 33 is set to a state where the centered value y ^ is transferred from register 36 to register 35.

The realistic multiplication of the ordinate values of stochastic processes takes place as follows.

At the beginning of the first sub-period of the "i" period, a value x is stored in register 24. ... Then the control inputs of the selectors i-q + 1 19 and 32 are supplied with commands that cause the import of random numbers from the outputs 20 and 7 of the random number-15 generator 6 to the input 1 of the adder 1 and the input 37 of the adder 31, respectively, while the control inputs of the adder 1 and 31 a subtraction command is imported. It follows that the input 15 of the logic circuit 14 (from the memory number 12 of the adder 1) is supplied with a logical one if the value written to the re-20 register 27 is greater than the number effective at the output 20 of the random number generator 6, and a logical zero if the value is less than the random number 6 of the random number generator 6. dose 20 effective figure. Similarly, the input 13 of the logic circuit 14 (input 44 of the memory number 25 of the adder 31) is supplied with a logical one if the value ^ written to the register 35 is greater than the number acting on the output 7 of the random number generator 6, and logical zero if the value ^ is less than the value 7 of the random number generator 6 number. For greater accuracy, the comparison of the numbers stored in the registers 24 and 25 with the numbers affecting the outputs 7 and 20 of the random number generator 6 can be performed several times when the numbers affecting the outputs 7 and 20 have different values. Thus, at the end of the first sub-period 35 of the "i" period of the correlator operation, the logic circuit 14 generates a logic sig- isis 71437 signal (or a sequence of logic signals) representing the multiplication of the centered value of the process "y" and the centered value Χχ-q + 1. the probability of the result.

during the following subsections of the "i" period, the value of y. multiplied by the values of x. x. etc., which is obtained by successively passing the contents of the memory unit 4 forward and writing information about the last flip-flop group of the memory unit 4 to the register 21 as described above, during the last "i" period of the "i" period, the logic circuit 14 develops a probability of input. S ^ x ^.

Thus, the correlator shown in Figure 2 performs a two-stochastic process to calculate the probability multiplication of the centralized ordinate values to calculate the cross-correlation function according to formula (1) without using special reference units whose operations are performed by adders 1 and 31.

The values of the inputs obtained during the same sub-periods with the same sequence number of the different periods are calculated in the data accumulator 16 in the same way as described above. As a result of this summation, the data battery 16 contains values

N N N N

Σοο \ oo \ oo \ O o __ Xiyi '/ j i-lyi' xi-lYi '··' '/, xi — 4 + lyi' i = li = li = li = l which are proportional to the process "y" to the ordinate values of the cross-correlation function calculated with respect to "x". After calculation, these values can be read from the data accumulator 16 and used for the graphical display of the cross-correlation function or further processed in a digital computer.

Claims (3)

A digital probability correlator comprising a memory unit (4) of an adder (1), the second input (2) of which is connected to the output of a selector (3), the second input (17) of the selector (3) being input to a mathematical expectation code of the stochastic process to be examined. the input of which is connected to the output of the calculation result of the adder (1) (5), the random number generator (6), the reference 1Q unit (9), the second input (8) of which is connected to the output (7) of the random number generator (6) and the second input (10) introducing a signal determined by the difference between each ordinate value of the stochastic process under study and the mathematical expectation value of this stochastic process, a data accumulator (16) of a logic-15 circuit (14) connected to the output of the reference unit (9) the input is connected to the output of a logic circuit (14), and a timing unit (26) adapted to synchronize the operation of the correlator parts, characterized in that in the selector (3) the second input (18) is connected to the random number generator (6) to the second output (20), the second input (15) of the logic circuit (14) is connected to the output (12) of the memory number of the adder (1), the second input (25) of the adder (1) is connected to the output of the register (24) to the output of the selector (21), the ordinate values of the stochastic process to be examined are input to the second input (22) of the second selector (21), and that the second input (23) of the second selector (21) is connected to the output of the memory unit (4). Probability-30 correlator according to Claim 1, characterized in that the second input (10) of the reference unit (9) is connected via a second register (11) to the output (5) of the calculation result of the adder (1). Probability correlator according to Claim 2, characterized in that the reference unit 35 is an adder (31), the second input (38) of which is connected via the register (35) to the output of the third selector (33). whose second input (42) of the selector is connected via a third register (36) to the output (43) of the calculation result of this suppressor (31) and which selects the ordinate values of the second stochastic process to be examined, and that the adder ( 31) the second input (37) is connected to the output (7) of the random number generator (6) via a fourth selector (32), the second input (39) 10 of which selects the mathematical expectation code of the second stochastic process to be examined, and that this adder (31) the memory number output (44) is connected to the second input (13) of the logic circuit (14). 2i 71437